JPH05175838A - D/a conversion circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a D / A conversion technology capable of reducing an output offset voltage without being affected by deterioration of accuracy of resistance ratio among a plurality of resistance elements which are constituent elements. To do. [Structure] Terminals T1 and T2 to which two voltages are applied
A plurality of resistors R1 to R8 connected in series with the resistor R1 and R8, which are opened and closed according to a digital input signal, and are obtained at the connection points between the resistors R1 to R8 and between the resistors R1 and R8 and the terminals T1 and T2. Switches SW1 to S for extracting voltage
W8, a reference voltage generation circuit REF whose input is connected to a connection point corresponding to the reference voltage of the analog output signal among the intermediate voltages of the resistors R1 to R8, and a switch SW at one input.
The analog output voltage is input via 1 to SW8, and the other input is composed of a differential circuit DEF to which the output from the reference voltage generation circuit REF is connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a D / A (digital
The present invention relates to an analog / analog conversion technology, and more particularly to a D / A conversion technology suitable for use in the field of digital servo integrated circuits and the like that require a low offset voltage.

[0002]

2. Description of the Related Art For example, in the field of controlling industrial equipment using a computer, a D / A conversion circuit for converting a digital signal into an analog signal is widely used. As such a D / A conversion circuit, one having a configuration illustrated in FIG. 5 is generally known.

That is, in FIG. 5, DEC is a decoding circuit, VREF is a reference voltage generating circuit, DEF is a differential circuit, M is a position control motor, R1 to R8 and R13,
R14 is a resistance element, SW1 to SW8 are switches, and AMP
1 to AMP2 are operational amplifiers, and T1 to T4 and D0 to D2 are terminals.

A conventional D / A will be described below with reference to FIG.
An example of the operation of the conversion circuit will be described.

The circuit configuration and operation of this type of D / A conversion circuit are described in documents such as Japanese Patent Laid-Open No. 1-164125, and detailed description thereof will be omitted.

The D / A conversion circuit illustrated in FIG.
It is a resistance voltage dividing type 3-bit D / A conversion circuit, and has a terminal D0.
A digital input signal using a two's complement expression applied to D2 to D2 is converted into an analog voltage, and the position control motor M is driven and controlled via the differential circuit DEF.

Specifically, between the terminals T1 and T2, depending on the resolution (3 bits) in D / A conversion,
Two (resolution) power = 2 ³ = 8 resistors R1 to R8 are connected in series. For example, a voltage of 3V is applied to the terminal T1, a voltage of 2V is applied to the terminal T2, and the resistors R1 to R8 are set to have the same resistance value, for example.

The decoding circuit DEC has a switch SW in accordance with a digital input signal applied to the terminals D0 to D2.
2V is closed by closing a switch at a predetermined position among 1 to SW8.
A desired intermediate voltage out of eight intermediate voltages of 2.875 V is output to the differential circuit DEF via the voltage follower configured by the operational amplifier AMP1.

On the other hand, the reference voltage generating circuit VREF generates a signal reference voltage of the output analog signal output from the decoding circuit. The analog output voltage corresponding to this signal reference voltage is 2.5 V generated at the contact points of the resistor R4 and the resistor R5. For example, 5 V is applied to the terminal T3, the terminal T4 is grounded, and the resistance R1 is applied.
3 and the resistor R14 have the same resistance value. As a result, the potential of the contact point between the resistor R13 and the resistor R14 becomes about 2.5 V, and this voltage is output via the voltage follower composed of the operational amplifier AMP2.

The differential circuit DEF receives, for example, a differential voltage between two inputs from each of the voltage follower and the reference voltage generation circuit REF, multiplies the gain by a predetermined gain, and outputs a differential voltage between the two outputs. Therefore, a voltage in both positive and negative directions according to the digital input signal is supplied to the position control motor M to control the position of the controlled object.

For example, the digital input signal is + 3 =
When (0, 1, 1) ₂ is set, the output voltage of the decoding circuit DEC becomes 2.875V. Since the output voltage of the reference voltage generation circuit REF is constant at 2.5V, the output voltage of the differential circuit increases by 0.375V, which is a gain multiple of 0.375V.
That is, a negative voltage is applied to the position control motor M, and the position of the controlled object moves in the negative (or positive) direction.

Conversely, the digital input signal is given by -4 = (1,
When 0, 0) ₂ , the output voltage of the decoding circuit DEC is 2V. The output voltage of the reference voltage generator REF is 2.
Since it is 5V, the output voltage of the differential circuit is 0.5 in the positive direction.
The voltage multiplied by the gain of V increases. That is, a negative voltage is applied to the position control motor M, and the position of the controlled object moves in the positive (or negative) direction.

Further, the digital input signal is 0 = (0,
If 0,0) ₂ , the output voltage of the decoding circuit DEC is 2.5V. The output voltage of the reference voltage generator REF is
Since it is 2.5V, the output voltage of the differential circuit is 0V,
Theoretically, no voltage is applied to the position control motor M, and the position of the controlled object does not change.

[0014]

DISCLOSURE OF INVENTION Problems to be Solved by the Invention
In the / A conversion circuit, the digital input signal is 0 = (0,
When 0, 0) ₂ , the position of the controlled object theoretically does not change as described above.

However, in the conventional D / A conversion circuit, an offset voltage is actually generated, and a voltage of about several mV to several hundreds of mV is applied to the position control motor M, which causes a digital input. Although the signal is 0, a malfunction that causes the movement of the controlled object occurs. Considering the cause of this malfunction, fluctuations in the analog output voltage when the digital input signal is 0 due to deterioration of the ratio accuracy between the total resistance value of the resistors R1 to R4 and the total resistance value of the resistors R5 to R8, and the resistance It is considered that the signal reference voltage fluctuates due to the deterioration of the ratio accuracy of the resistance value of R13 and the resistance value of R14.

For example, when the accuracy of the resistance ratio between the resistors R13 and R14 is degraded by 1%, the signal reference voltage is ± 25 m.
Voltage fluctuation of V occurs. Further, the resistors R1 to R4
Similarly, if the resistance ratio accuracy between the total resistance value of R1 and the total resistance value of resistors R5 to R8 deteriorates by 1%, a voltage fluctuation of ± 5 mV occurs in the analog output signal, and the differential circuit D
The offset voltage at the input of the EF reaches a total of ± 30 mV.

That is, the conventional D / having the above-mentioned configuration is used.
In the A conversion circuit, the countermeasure against the deterioration of the resistance ratio accuracy between the plurality of resistance elements which are the constituent elements is insufficient, and
There is a problem that the offset voltage at the output of the / A conversion circuit becomes large.

The object of the present invention is to reduce the output offset voltage without being affected by the deterioration of the resistance ratio accuracy among a plurality of resistance elements as constituent elements.
It is to provide A conversion technology.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0020]

Among the inventions disclosed in the present application, a typical one will be briefly described as follows.
It is as follows.

That is, the D / A conversion circuit of the present invention is connected between the first and second terminals and the first and second terminals, and is formed by connecting a plurality of resistance elements in series. In a D / A conversion circuit including a resistor group and a decode circuit that outputs a voltage at a predetermined resistance connection point among a plurality of connection points in the series resistance group according to a digital input signal from the outside, a series resistance group Of a plurality of resistance connection points in the input circuit, an input is connected to a predetermined resistance connection point that generates a voltage corresponding to the output signal reference voltage, and a reference voltage generation circuit that generates the output signal reference voltage; And a differential circuit having the other input connected to the output of the reference voltage generating circuit.

[0022]

According to the D / A conversion circuit of the present invention described above, for example, the digital input signal in the decoding circuit is 0.
By extracting the output voltage for the differential circuit at the same time from the same resistance connection point as the reference voltage generation circuit, fluctuations in the output voltage of the reference voltage generation circuit and the decoding circuit input to the differential circuit are canceled out. Therefore, the offset voltages of the two inputs to the differential circuit become substantially zero, regardless of variations in the resistance ratio accuracy in the resistive element group used, and the offset voltage is reliably reduced.

[0023]

First Embodiment A D / A conversion circuit which is an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a D / A conversion circuit according to an embodiment of the present invention.

The D / A conversion circuit of this embodiment is provided with a plurality of resistors R1 to R8 of equal resistance connected in series between a terminal T1 and a terminal T2 to which a predetermined reference voltage is applied. The input terminal of the operational amplifier AMP1 of the decoding circuit DEC is connected to the connection point of these resistors R1 to R8 via a plurality of switches SW1 to SW8.

The output of the operational amplifier AMP1 is one input of two differential circuits DEF. The switches SW1 to SW8 are opened and closed from the outside by terminals D0 and D.
1, controlled according to the value of the 3-bit digital input signal input to the terminal D2.

The output of the reference voltage generating circuit REF is connected to the other input of the differential circuit DEF. The reference voltage generation circuit REF is a voltage follower type operational amplifier AMP2 that outputs an input voltage as it is as an output voltage.
The input terminal of the operational amplifier AMP2 is connected to the connection point between the resistors R4 and R5 among the connection points of the resistors R1 to R8 connected in series. .. That is, the resistor R4 and the resistor R4 are connected to the input on the side of the reference voltage generation circuit REF of the differential circuit DEF.
The voltage taken out from the connection point with 5 is input.

Further, in the case of the present embodiment, the 3-bit digital input signal inputted to the terminals D0 to D2 is treated as a 2's complement, and when all of the 3 bits are 0 (0, 0,
In the case of 0) ₂ , the switch SW4 corresponding to the connection point between the resistors R4 and R5, which is the same as the connection point to which the input terminal of the reference voltage generation circuit REF is connected, operates to close.

In the case of this embodiment, for example, the voltages applied to the terminals T1 and T2 are 3V and 2V, respectively.
At this time, an example of the relationship between the opening / closing operation of the switches SW1 to SW8 according to the bit pattern of the digital input signal to the terminals D0 to D2 and the voltage value output from the operational amplifier AMP1 to the differential circuit DEF is shown in FIG. Like

In the case of the present embodiment, for example, when the position control motor M is driven and controlled by the differential circuit DEF, the differential circuit DEF is applied to the position control motor M.
Input voltage from is 0V, digital input signal =
(0,0,0) ₂ is assigned as a stationary command.

An example of the operation of the D / A conversion circuit of this embodiment will be described below.

In the configuration of FIG. 1, when the digital input signal (0,0,0) ₂ is input to the terminals D0 to D2, only the switch SW4 is closed, so that the decode circuit DEC outputs it to the differential circuit DEF. The analog voltage is the resistance R
4 corresponds to the intermediate voltage generated at the connection point of the resistor R5.

Here, consider a case where the resistance ratio accuracy between the total resistance value of the resistors R1 to R4 and the total resistance value of the resistors R5 to R8 is degraded by 1%. In this case, the potential at the connection point between the resistors R4 and R5 is the design center voltage 2.5.
It varies ± 5 mV from V. Therefore, when the digital signal is (0,0,0) ₂ , the output analog signal output from the decoding circuit DEC to one input of the differential circuit DEF also fluctuates ± 5 mV, and the input from the same connection point. Similarly, the signal reference voltage output from the reference voltage generating circuit REF that takes out the voltage to the other input of the differential circuit DEF also fluctuates ± 5 mV. However, the fluctuation of the output analog signal output from the decoding circuit DEC and the reference voltage generating circuit R
The fluctuation of the signal reference voltage output by the EF matches the fluctuation voltage and the fluctuation polarity, and the differential input voltage at the two inputs of the differential circuit DEF is the voltage fluctuation in the decode circuit DEC and the reference voltage generation circuit REF. It is always constant at 0V regardless of.

As a result, no voltage is supplied from the differential circuit DEF to the position control motor M, and the position of the controlled object driven by the position control motor M remains unchanged and remains stationary. That is, according to the D / A conversion circuit of the present embodiment, fluctuations in the offset voltage due to variations in the resistance ratios of the resistors R1 to R8, etc. that form the D / A conversion circuit are reliably reduced.

[0035]

[Embodiment 2] FIG. 2 shows another embodiment of a D / A according to the present invention.
It is a circuit diagram which shows an example of a structure of a conversion circuit.

In the case of the second embodiment, the decoding circuit D
A variable gain amplifier ATT is provided between the EC and the differential circuit DEF.
The difference from the case of the first embodiment is that the interposition is provided.

The variable gain amplifier ATT is a decoding circuit D.
A plurality of resistors R9 connected in series between the terminal T3 to which the analog voltage is input from EC and the terminal T4 to which the signal reference voltage output from the reference voltage generation circuit REF is applied.
~ R12 and a plurality of switches SW9 connected so that voltages can be individually taken out from these connection points ~
SW12 and voltage follower type operational amplifier AMP
3 is included in the configuration.

An example of the operation of the D / A conversion circuit in this embodiment will be described below.

In the above description of the operation of the prior art shown in FIG. 5 and the operation of the embodiment shown in FIG. 1, the offset voltage of the operational amplifier AMP1 of the decoding circuit DEC and the offset voltage of the operational amplifier AMP2 of the reference voltage generating circuit REF are shown for the sake of simplicity. The explanation of the effect is omitted. For example, in both the embodiment of FIG. 1 and the conventional technique of FIG. 4, the sum of the offset voltage of the operational amplifier APM1 and the offset voltage of the operational amplifier APM2 is generated at the input of the differential circuit DEF.

Therefore, in the D / A conversion circuit of the second embodiment, it is necessary to reduce the offset voltage due to the variation of the resistance ratio and to avoid the influence of the offset voltage of the operational amplifier forming the D / A conversion circuit. It works as follows.

Here, before explaining the operation of the second embodiment, first, a supplementary explanation will be given regarding the control of the voltage applied to the position control motor M. When a movement request for the controlled object driven by the position control motor M occurs, first, a relatively large voltage is applied to the position control motor M, and high-speed movement to the target position is started. Next, when the controlled object approaches the target positioning position, the applied voltage to the position control motor M is gradually reduced, and when the controlled object reaches the target position, the voltage is supplied to the position control motor M. Stop.

After that, a minute position correction voltage for stopping at the target position is continuously applied to the position control motor M, and at this time, the presence or absence of the offset voltage is a problem in terms of accuracy of maintaining control of the current position of the controlled object. Becomes Therefore, in the D / A conversion circuit of the second embodiment, such a problem is avoided as follows.

That is, in the D / A conversion circuit of the second embodiment illustrated in FIG. 2, the gain of the D / A conversion circuit is reduced and the digital input signal is changed in the gain in the position correction state as described above. Use after making a predetermined correction according to
To improve apparent resolution and reduce offset voltage.

As described above, the output of the decoding circuit DEC is connected to the terminal T3 of the variable gain amplifier ATT,
The output of the reference voltage generation circuit REF is a variable gain amplifier ATT.
Of the other terminal T4. In the case of this embodiment,
The resistance ratio of the plurality of resistors R9 to R12 connected between the terminals T3 and T4 of the variable gain amplifier ATT is, for example, R9: R10: R11: R12 = 4: 2: 1: 1,
Is set to. The switches SW9 to SW12 respectively include a connection point between the resistor R9 and the terminal T3, a connection point between the resistors R9 and R10, a connection point between the resistors R10 and R11, and a resistor R11 and R11.
The switches SW9 to S are respectively connected to 12 connection points.
The other end of W11 is commonly connected to the input of the voltage follower of the operational amplifier APM3. Further, the output of the operational amplifier APM3 is connected to the input of one of the differential circuits DEF.

The switches SW9 to SW12 operate so that only a specific one is closed and the other are opened by a separately input gain switching signal (not shown).

As a result, the input signal voltage between the two terminals T3 and T4 of the variable gain amplifier ATT is 1 times when the switch SW9 is closed and 1 / when the switch SW10 is closed due to the gain switching signal. Double, switch SW1
When 1 is closed, it is 1/4 times, and when the switch SW12 is closed, it is attenuated to 1/8 times the gain and input to the differential circuit DEF.

When the position control motor M closes the switch SW12 so that the gain of the variable gain amplifier ATT becomes ⅛ in the position correction state during the operation of maintaining the stationary state of the connection point object. Consider the offset voltage at the input of the differential circuit DEF.

The offset voltage at the input of the differential circuit DEF is 1/8 times the offset voltage of the operational amplifier APM3 and the offset voltage of the operational amplifier APM1 and the operational amplifier APM2. For example, operational amplifier APM1,
When the variations in the offset voltage of APM2 and APM3 are all equal ± 10 mV, the offset voltage at the input of the differential circuit DEF is ± 10 mV ± (10 mV + 10 mV)
× 1/8 = ± 12.5 mV. On the other hand, in the D / A conversion circuit of the first embodiment illustrated in FIG. 1 and the conventional D / A conversion circuit illustrated in FIG. 5, ± 20 mV is reached under the same conditions, and the D / A conversion of the second embodiment is performed. In the A conversion circuit, the offset voltage due to the operational amplifier can be reduced to 1/2.

That is, according to the D / A conversion circuit of the second embodiment, not only the fluctuation of the offset voltage caused by the variation of the resistance ratio in the resistance element group as a constituent element but also the offset voltage caused by the operational amplifier is reduced. There is an advantage that the occurrence can be reduced.

[0050]

[Third Embodiment] FIG. 3 is a block diagram showing an example of the configuration of a D / A conversion circuit which is still another embodiment of the present invention.

In the case of the third embodiment, the variable gain amplifier ATT forms an inverting amplifier circuit in which the variable resistance circuit VR1 and the resistor R15 as feedback resistors are added to the operational amplifier APM3. Different from the case of Example 2.

That is, one end of the resistor R15 is connected to the decoding circuit D via one terminal T3 of the variable gain amplifier ATT.
The other end is connected to the output of the EC and the opposite phase input of the operational amplifier APM3 and one end of the variable resistance circuit VR1. The other terminal T4 of the variable gain amplifier ATT is connected to the positive phase input of the operational amplifier APM3. The output terminal of the variable gain amplifier ATT is connected to the output of the operational amplifier APM3 and the variable resistance circuit VR1.

The gain of the inverting amplifier circuit constituted by the operational amplifier APM3, the resistor R15 and the variable resistance circuit VR1 is determined by the ratio of the resistance value of the resistor R15 and the resistance value of the variable resistance circuit VR1. The variable resistance circuit VR1 is composed of, for example, a plurality of resistance elements and a switch, and can change the resistance value to a desired value by performing a switching operation of the switch in accordance with a separately input gain switching signal (not shown). It is possible. This gain switching is controlled in the same manner as the second embodiment illustrated in FIG.

Here, in the position correction state of the position control motor M described in the second embodiment of FIG. 2, the resistance value of the variable resistance circuit VR1 is changed to ⅛ times the resistance value of the resistance R15. , Consider the offset voltage at the input of the differential circuit DEF when the gain in the variable gain amplifier ATT is set to 1/8.

Operational amplifiers APM1, AMP2, AMP3
If the offset voltages of are all equal ± 10 mV,
Offset voltage at the input of differential circuit DEF is ± 10m
V × 9/8 ± (10 mV + 10 mV) × 1/8 = ± 13.
In contrast to the voltage of 75 mV, the first embodiment of FIG.
In the prior art, since ± 20 mV is reached under the same conditions, it can be seen that the offset voltage can be reduced to about 1/2 in the case of the third embodiment.

That is, according to the D / A conversion circuit of the third embodiment as well, not only the fluctuation of the offset voltage caused by the variation of the resistance ratio in the resistive element group as a constituent element but also the generation of the offset voltage caused by the operational amplifier are generated. It is possible to obtain the effect of being able to reduce

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0058]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the D / A conversion circuit of the present invention, it is possible to significantly reduce variations in resistance ratio between resistance elements and variations in offset voltage due to operational amplifiers and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a D / A conversion circuit that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a D / A conversion circuit which is another embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a configuration of a D / A conversion circuit which is still another embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of an operation in a D / A conversion circuit which is an embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a configuration of a conventional D / A conversion circuit.

[Explanation of symbols]

 AMP1 to AMP3 operational amplifier ATT variable gain amplifier D0 to D2 terminal DEC decoding circuit DEF differential circuit M position control motor R1 to R15 resistance REF reference voltage generation circuit SW1 to SW12 switch T1 to T4 terminal VR1 variable resistance circuit VREF reference voltage generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiko Sato 2880 Kozu, Odawara City, Kanagawa Stock Company Hitachi Ltd. Odawara Factory

Claims (1)

[Claims] 1. A series resistance group, which is connected between the first and second terminals and the first and second terminals and is formed by connecting a plurality of resistance elements in series, and a digital input signal from the outside. A D / A conversion circuit including a decoding circuit for outputting a voltage at a predetermined resistance connection point among a plurality of connection points in the series resistance group, the plurality of resistance connection points in the series resistance group. A reference voltage generating circuit for generating an output signal reference voltage, the input of which is connected to a predetermined resistance connection point for generating a voltage corresponding to the output signal reference voltage,
And a differential circuit having one input connected to the output of the decoding circuit and the other input connected to the output of the reference voltage generation circuit.