JPH05161075A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce a signal charge storage time of each picture element less than a time required to read all picture elements and to attain image pickup even when an intense optical signal is received. CONSTITUTION:Photo diodes 11 (picture elements) are arranged in 2-dimensions and sources of reset and read MOSFETs 12, 13 are connected in common to each cathode. The charge integrated in the picture element selected by read vertical horizontal shift registers 14, 16 is read by a read amplifier 17. Moreover, the picture element selected by reset use vertical shift register 18, 20 is reset by a reset use power supply 21 independently of the signal read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device having a two-dimensional array of light-receiving elements that generate a charge amount corresponding to the amount of incident light.

[0002]

2. Description of the Related Art Conventionally, as a solid-state image pickup device of this type,
For example, there is a MOS type solid-state imaging device configured by using a MOSFET (MOS type field effect transistor).
This MOS type solid-state image pickup device has a selection M for selecting pixels.
OSFET and M that sequentially controls the selection switch
It is composed of an OS shift register. Among such MOS type image pickup devices, there is one in which a preamplifier for signal reading is formed on the same chip, and FIG. 6 shows the configuration of the MOS type solid state image pickup device in this case.

The photodiodes 1 are arranged two-dimensionally, and the source of a MOSFET 2 which is a selection switch is connected to each photodiode 1. Each of these M
The gates of the OSFETs 2 are commonly connected for each row and controlled by the read vertical register 3. Further, each drain is commonly connected to each column, and a line selection MOSFET 4 is provided for each column. The line selection MOSFET 4 is controlled by the read horizontal shift register 5.

The photodiode 1 also serves as a charge storage portion, and the charge generated in the photodiode 1 during the integration period of the incident optical signal is stored in the capacitance of the photodiode 1 itself. This accumulated charge is transferred to the MOSFET 2 by the read vertical shift register 3 and the horizontal shift register 5.
Is selected, the image signal is read out by the read amplifier 6. The read timing at this time is shown in the timing chart of FIG.

1A to 1C are voltage pulse signals ΦV1 to ΦV3 output from the read vertical shift register 3 to each row line, and FIGS. 1D to 1F are from the read horizontal shift register 5. The voltage pulse signals ΦH1 to ΦH3 output to each column line are shown. Further, FIG. 3G shows the photodiode 1 located at the coordinate (1,1) in the first row and the first column.
Photodiode potential VPD (1,1) of FIG. 1 (h) is the photodiode 1 located at the coordinate (1,2) in the first row and second column.
Shows the photodiode potential VPD (1,2). As the pulse signal ΦV1 is output from the vertical shift register 3, a voltage is applied to the first row line, while the horizontal shift register 5 outputs pulse signals ΦH1, ΦH2, ΦH3.
Is output, the M of each column located in the first row is output.
The OSFETs 2 are sequentially selected, and signals are read from the pixels on the first row. Thereafter, similarly to this, the row lines to be selected are sequentially shifted by the vertical shift register 3 to perform two-dimensional image reading.

[0006]

However, in the above-mentioned conventional solid-state image pickup device, signal reading for discharging the charges generated in the photodiode 1 and charging of the discharged charges of the photodiode 1 to the original charge amount are performed. It is being performed at the same time as the reset. For this reason, the second signal read-out for a certain pixel can be performed only after the first signal read-out for all pixels is completed. Therefore, the accumulation time of the signal charge due to the incident light becomes longer than the time when the reading is completed for all the two-dimensional pixels. That is, the photodiode 1 located at the coordinate (1,1) reset at the time t1 in FIG. 7 accumulates the signal charge until the time t3 selected for the next reading. Similarly, the photodiode 1 located at the coordinate (1,2) is reset at time t2 and read at time t4. In addition, the minimum signal read time per pixel is the capacitance of the video line connected to the read amplifier 6, the on-resistance of the MOSFET 2,
It is determined by the speed of the read amplifier 6 and the like. Therefore, the minimum time required to read out signals from all the pixels is the minimum reading time per pixel multiplied by the total number of pixels. Therefore, the accumulation time of the signal charge in each pixel is at least the above-described one cycle time required to read out all the pixels. As a result, the minimum value of the signal charge storage time was defined by the time required to read all pixels, and the signal charge storage time could not be set below the time required to read all pixels. ..

The amount of charge Q that can be accumulated in the photodiode 1 is the capacitance C of the photodiode 1 itself.
And the reset voltage V is determined. Here, when strong light is incident on the photodiode 1, electric charges are generated in an amount equal to or more than the electric charge amount Q that can be accumulated in the photodiode 1. Therefore, the electric charge accumulated in the photodiode 1 is saturated and overflows from the photodiode 1. Therefore, when intense light is applied to the entire light receiving portion, all the photodiodes 1 are saturated and it becomes impossible to capture an image.

The present invention has been made to solve such a problem, and the signal charge storage time of each pixel can be made shorter than the time required to read out all pixels, and a strong optical signal is emitted. It is an object of the present invention to provide a solid-state image pickup device capable of performing image pickup even if it is performed.

[0009]

SUMMARY OF THE INVENTION According to the present invention, a plurality of two-dimensionally arranged light receiving elements for generating charges according to the amount of incident light, and each light receiving element for interrupting the flow of charges to these light receiving elements. First and second switching elements provided for each of the first and second switching elements, and a read row selection circuit that selects a first switching element group arranged in the row direction among the first switching elements for signal reading. , A read column selection circuit for selecting a first switching element group arranged in the column direction among the respective first switching elements for signal reading, and 1 selected by the read row selection circuit and the read column selection circuit. A signal readout circuit for reading out the amount of electric charge generated in the light receiving element corresponding to each of the first switching elements, and a second switching element group arranged in the row direction among the second switching elements A reset row selection circuit that selects for signal reset, a reset column selection circuit that selects a second switching element group arranged in the column direction among the second switching elements for signal reset, and these reset rows. The solid-state imaging device is configured to include a signal reset power supply that resets the electric charge of the light receiving element corresponding to the one second switching element selected by the selection circuit and the reset column selection circuit.

[0010]

The signal reading for each light receiving element is performed by the read row selecting circuit, the reading column selecting circuit and the signal reading circuit, and the signal reset for each light receiving element is performed by the reset row selecting circuit, the reset column selecting circuit and the signal reset power supply. Done. Therefore, the signal reading and the signal resetting are performed by separate and independent circuits.

[0011]

1 is a diagram showing the configuration of a MOS type solid-state image pickup device according to a first embodiment of the present invention.

The photodiodes 11 are light receiving elements that generate electric charges according to the amount of incident light, and are arranged two-dimensionally in the row direction (X direction) and the column direction (Y direction). The reset MOSFET 12 and the read MOSFET 13 whose sources are commonly connected are connected to the cathodes of the photodiodes 11. Each of these MOSF
The ETs 12 and 13 interrupt the flow of charges to the photodiodes 11.

Each photodiode 1 arranged in the X direction
The gates of the respective read MOSFETs 13 provided for 1 are commonly connected by a read gate control line L1. This read gate control line L1
Is a vertical shift register 1 for reading when reading a signal.
One of them is selected by 4. The drains of the read MOSFETs 13 provided for the photodiodes 11 arranged in the Y direction are commonly connected by a read line L2. Each of these read lines L2 has a read line selection MOSFE.
T15 is provided, and these read line selection MOSFETs 15 are read horizontal shift registers 16
Controls the gate. That is, the read horizontal shift register 16 causes the video line VL
The read line L2 connected to is selected.

The gate voltage of the signal reading MOSFET 13 is applied to the reading gate control line L1 selected by the reading vertical shift register 14. Further, a voltage is applied to the gate of the read line selection MOSFET 15 selected by the read horizontal shift register 16, and the read line selection MOSFET 15 is supplied with a voltage.
The read line L2 connected to the OSFET 15 is connected to the video line VL. Therefore, the read gate control line L1 selected by the read vertical shift register 14 and the read horizontal shift register 16 are selected.
The signal reading MOSFET 13 arranged at the crossing position of the read line L2 selected by is turned on, and the charges generated in the photodiode 11 arranged at this crossing position are guided to the video line VL via the read line L2 and read. It is amplified and output by the amplifier 17.

Each reset MOSFET provided for each photodiode 11 arranged in the X direction.
The gates of 12 are commonly connected to the reset gate control line L3. This reset gate control line L3
At the time of resetting, one of them is selected by the reset vertical shift register 18. Further, the drains of the reset MOSFETs 12 provided for the photodiodes 11 arranged in the Y direction are commonly connected by a reset line L4. Each reset line L4 has a reset line selection MOSFET 1
9 is provided for these reset line selection MOs.
The gate of the SFET 19 is controlled by the reset horizontal shift register 20. That is, the reset horizontal shift register 20 causes the reset signal line RSL
The reset line L4 connected to is selected.

The gate voltage of the reset MOSFET 12 is applied to the reset gate control line L3 selected by the reset vertical shift register 18. In addition, a voltage is applied to the gate of the reset line selection MOSFET 19 selected by the reset horizontal shift register 20, and the reset line selection MOSF
The reset line L4 connected to ET19 is connected to the reset signal line RSL. Therefore, the reset gate control line L3 selected by the reset vertical shift register 18 and the reset horizontal shift register 20 are selected.
The reset MOSFET 12 arranged at the intersection of the reset line L4 selected by is turned on. Therefore, the photodiode 11 arranged at this intersection position is charged with electric charges corresponding to the amount of electric charge discharged at the time of signal reading, from the reset signal line RSL to the photodiode 11 via the reset line L4, and the photodiode 11 is reset. It is reset by the power source 21.

FIG. 2 shows a timing chart of signals at various parts in such a configuration. FIGS. 9A to 9C show voltage pulse signals ΦVRES1 output from the reset vertical shift register 18 to each reset gate control line L3.
~ ΦVRES3, (d) and (e) are voltage pulse signals ΦVRO1, ΦVRO2 output from the read vertical shift register 14 to each read gate control line L1, and (f) in the same figure.
(H) is a voltage pulse signal ΦHRES1 output from the reset horizontal shift register 20 to each reset line selection MOSFET 19 connected to each reset line L4.
.About..PHI.HRES3 and (i) to (k) of FIG. 5 show voltage pulse signals .PHI.HRO1 to .PHI.HRO3 output from the read horizontal shift register 16 to the read line selection MOSFETs 15 connected to the read lines L2. In addition, the time axis of each of these diagrams is represented by the same time scale.

At time t1, as shown in FIG. 1A, a high-level voltage pulse signal ΦVR is applied to the reset gate control line L3 in the first row located at the uppermost stage in FIG.
ES1 is output, and as shown in FIG. 2 (f), the reset line selection MOSF connected to the reset line L4 in the first column located on the leftmost side in FIG.
The high-level voltage pulse signal ΦHRES1 is output to the ETF 19. Therefore, at time t1, the coordinates (1,1)
The reset MOSFET 12 provided for the photodiode 11 located at is turned on, and a path is formed from the photodiode 11 to the reset power supply 21 via the reset line L4 and the reset signal line RSL. It is reset by the reset power supply 21. Further, at this time t1, as shown in (i) of the figure, the read line L2 of the first column is
The high-level voltage pulse signal ΦHRO1 is output to the readout line selection MOSFET 15 connected to.
However, since no pulse is output from the read vertical shift register 14, a path from the photodiode 11 to the read amplifier 17 is not formed. Therefore,
The signal charge is not read from the photodiode 11.

At time t2, as at time t1, the voltage pulse signal Φ output to the reset gate control line L3 is output.
VRES1 remains at high level but does not change, but the same figure (g)
As shown in, the high level voltage pulse signal ΦHRES2 is output to the reset line selecting MOSFET 19 connected to the reset line L4 in the second column. Therefore, at time t2, the reset MOSFET provided for the photodiode 11 located at the coordinate (1, 2)
12 is turned on, and the photodiode 11 located at this coordinate (1, 2) is reset by the reset power supply 21. Further, at this time t2, as shown in FIG. 7J, the high-level voltage pulse signal ΦHRO2 is output to the read line selection MOSFET 15 connected to the read line L2 in the second column. However, at time t2, as with time t1, since no pulse is output from the read vertical shift register 14, the signal charge is not read.

At time t3, similarly, the photodiode 11 located at the coordinate (1, n) on the first row and the n-th column is reset by the voltage pulse signal ΦHRESn shown in FIG. Absent. At the end, each photodiode 11 located in the first row is reset. The time t4 is a blank period.

Next, at time t5, the voltage pulse signal ΦVR output from the reset vertical shift register 18 is output.
ES1 falls, and the voltage pulse signal ΦVRES2 shown in FIG. At this time, the reset horizontal shift register 20 outputs the voltage pulse signal ΦHRES1 shown in FIG. Therefore, the voltage pulse signal ΦVRES2 raises the potential of the reset gate control line L3 in the second row, and the voltage pulse signal ΦHRES1 causes the reset line L4 in the first column to reset signal line RSL.
Connected to. Therefore, the reset MOSFET 12 provided for the photodiode 11 located at the coordinate (2, 1) in the second row and the first column is turned on, and the photodiode 11 is reset by the reset power supply 21.
At this time t5, the high-level voltage pulse signal ΦVRO1 shown in FIG. 7D is transferred from the read vertical shift register 14 to the read gate control line L1 of the first row.
Is being output. In addition, the voltage pulse signal ΦHRO1 shown in FIG.
Is output, and the read line L2 in the first column is connected to the video line VL. Therefore, the readout MOSFET 13 provided for the photodiode 11 located at the coordinate (1,1) is turned on. Therefore, the photodiode 11 is connected to the read amplifier 17 via the read line L2 of the first column and the video line VL,
The charges accumulated in the photodiode 11 located at the coordinates (1,1) are read.

As a result, the photodiode 11 located at the coordinate (1,1) is reset at time t1 and at time t5.
Then, the signal is read out, and the photocurrent integration time becomes (t5-t1). Therefore, this photocurrent integration time is determined by the photodiodes 11 located in the first row in the horizontal direction.
Is a time corresponding to one horizontal scan time for scanning.

At time t6, as at time t5, the reset line selecting MOSFET connected from the reset horizontal shift register 20 to the reset line L4 in the second column is used.
The high-level voltage pulse signal ΦHRES2 shown in FIG. Even at this time t6, the potential of the reset gate control line L3 in the second row is still rising, so that the photodiode 11 located at the coordinates (2, 2) is reset via the reset signal line RSL. Further, at the time t6, the read horizontal shift register 16 outputs the voltage pulse signal ΦHRO2 shown in FIG. 9 (j), and the read line L2 in the second column is connected to the video line VL. Since the potential of the read gate control line L1 in the first row has risen, at time t6, as at time t5, the coordinates (1, 2) are set.
The charges accumulated in the photodiode 11 located at are read out.

Similarly at time t7, the coordinates (2, n)
The photodiode 11 located at the reset power source 21
Then, the photodiode 11 located at the coordinates (1, n) is read by the read amplifier 17. At the end, the resetting of the photodiodes 11 in the second row and the signal reading of the photodiodes 11 in the first row are completed.

Thereafter, after time t9, similarly, the reset processing for each pixel on the third row and the read processing for each pixel on the second row are performed, and finally, the reset processing for all pixels and the signal are performed. The reading process will be performed.

According to the first embodiment as described above, the time required for resetting and reading out per pixel, that is, the photocurrent integration time is one scan time per row of the reset vertical shift register 18. become. Therefore, the photocurrent integration time in the solid-state imaging device according to the present embodiment is significantly shorter than that of the conventional solid-state imaging device in which the signal read time of all pixels is longer.

In the above description of the embodiment, the photocurrent integration time is reset to the horizontal 1 of the vertical shift register 18 for resetting.
Although the scan time has been described, the scan time is not limited to this. For example, this can be explained as follows using the timing chart of FIG. In the figure, the same or corresponding portions as those in FIG. 2 are depicted by the same reference numerals as those in FIG. 2, and the description thereof will be omitted. The difference between these figures is that at the timing of FIG. 3, each output pulse ΦVRO of the read vertical shift register 14 is changed to each output pulse ΦVR of the reset vertical shift register 18.
The point is that it is delayed by two horizontal scan times from ES.
That is, the time from the reset of each pixel in the first row to the reading of each pixel in the first row is not the horizontal 1 scan time of the vertical shift register 18 but double the horizontal 2 scan times. The scan time has come. For example, focusing on the photodiode 11 located at the coordinates (1, 1), the photodiode 11 is reset at time t1 and the signal is read at time t9. Therefore, the time interval between resetting and reading, that is, the photocurrent integration time becomes the time corresponding to the two horizontal scan times as described above, and the photocurrent integration time is set to twice as long as that in the above embodiment. It was done.

Further, when it is desired to set the integration time to be long, it is set to 1 after resetting each pixel in the first row.
It suffices to further lengthen the time until the signal reading of the row is performed. For example, if the horizontal one scan time of the reset vertical shift register 18 is T _V, and if the photocurrent integration time of the photodiode 11 is to be set to 5 T _V ,
It suffices to set a time interval of 5 horizontal scans after resetting each pixel on the first row and before reading each pixel on the first row. Thus, according to the first embodiment described above, the photocurrent integration time is equal to the time T _V
Although there is a constraint that it is an integer multiple of, it is possible to set it arbitrarily by changing the time from reset processing to read processing.

Next, a MOS according to a second embodiment of the present invention
The solid-state imaging device will be described. The configuration of the solid-state image pickup device according to the second embodiment is similar to that shown in FIG. 1, but the reset vertical and horizontal shift registers 18, 2 are reset.
0, and vertical and horizontal shift registers 14 for reading,
The timing of each pulse signal output from 16 is different as shown in FIG. In addition, in FIG.
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted. That is, in the solid-state imaging device according to the first embodiment, as shown in FIGS. 2A to 2E, the pulse signal ΦVRES output from the reset vertical shift register 18 and the read vertical shift register 14 are output. The rising and falling timings of the output pulse signal ΦVRO were the same. However, FIG.
In this embodiment shown in the timing charts (a) to (e), the rising and falling timings of these pulse signals ΦVRES and ΦVRO are different. Also,
In the solid-state imaging device according to the first embodiment, as shown in FIG.
As shown in (f) to (h), the generation timings of the pulse signal ΦHRES output from the reset horizontal shift register 20 and the pulse signal ΦHRO output from the read horizontal shift register 16 were the same. .. However, in the present embodiment shown in the timing charts of FIGS. 4F to 4J, the generation timings of the pulse signals ΦHRES and ΦHRO are different. The scanning of each pixel in this embodiment performed at such pulse generation timing is performed as follows.

First, at time t1, the photodiode 11 at the coordinates (1, 1) is reset by the pulse signal ΦVRES1 shown in FIG. 9A and the pulse signal ΦHRES1 shown in FIG. . Next, at time t2, the pulse signal ΦHRES2 shown in FIG. 9G is output while the potential of the pulse signal ΦVRES1 shown in FIG.
The photodiode 11 in 2) is reset. At time t3, the pulse signal Φ shown in FIG.
The output of HRES3 resets the photodiode 11 at the coordinates (1, 3). Time t4
Then, by outputting the pulse signal ΦHRES4 shown in (i) of the figure, the photodiode 11 at the coordinates (1, 4) is reset. Also, at times t3 and t4
Then, as shown in (k) and (l) of the same figure, the pulse signals ΦHRO1 and ΦHRO2 are read from the read horizontal shift register 16.
Is output, but a pulse is not output from the read vertical shift register 14, so the signal read processing is not executed. Horizontal shift register 2 for reset at time t5
The pulse signal ΦHRESn is output from 0, and the coordinates (1, n)
The photodiode 11 located at is reset. As a result, the reset operation for each pixel in the first row ends.

At time t6, the blank period is seen from the reset circuit, but the nth column video line VL is selected from the read circuit.

Next, at time t7, the pulse signal ΦVRES2 shown in FIG. 9B rises, the potential of the reset gate control line L3 in the second row rises, and the pulse signal ΦHRES1 shown in FIG. By being output, the reset line L4 in the first column is connected to the reset signal line RSL. Therefore, the photodiode 11 at the coordinates (2, 1) is reset, and reset for each pixel in the second row is started. The time t7 is a blank period as seen from the reading circuit. Next, at time t8,
While the potential of the pulse signal ΦVRES2 shown in (b) of the figure remains rising, the pulse signal ΦVRO1 shown in (d) of the figure rises. By outputting the pulse signal ΦHRES2 shown in FIG. 7G, the photodiode 11 at the coordinates (2, 2) is reset. Next, at time t9, the read horizontal shift register 16 outputs the pulse signal ΦHRO1 shown in FIG. Since the pulse signal ΦVRO1 output from the reading vertical shift register 14 has risen, signal reading is performed for the photodiode 11 at the coordinates (1, 1). Further, the photodiode 11 located at the coordinates (2, 3) is reset. At time t10, similarly, the signal reading of the photodiode 11 located at the coordinates (1, 2) and the resetting of the photodiode 11 located at the coordinates (2, 4) are performed. Hereinafter, similarly, the reset process and the read process are sequentially performed in time series for the pixels in each row unit.

That is, according to the second embodiment, the optical signal accumulation time of the photodiode 11 at the coordinate (1,1) corresponds to the time from t1 to t9. This time corresponds to the delay time of each rising time of the read vertical shift register 14 with respect to the reset vertical shift register 18. That is, in the second embodiment, the photocurrent integration time is set under the condition that the pulse signals ΦVRES and ΦVRO output from the reset vertical shift register 18 and the read vertical shift register 14 do not rise at the same time. It can be set to any time longer than one horizontal scan time of the reset vertical shift register 18. Therefore, according to the solid-state image pickup device of the second embodiment, the photocurrent integration time is not restricted to an integral multiple of one scan time of the reset vertical shift register 18 as in the first embodiment, and the photocurrent integration time is arbitrary. It is possible to set the time.

Next, a MOS according to a third embodiment of the present invention
The solid-state imaging device will be described. The configuration of the solid-state image pickup device according to the third embodiment is similar to that shown in FIG. 1, except that reset vertical and horizontal shift registers 18, 2 are provided.
0, and vertical and horizontal shift registers 14 for reading,
The timing of each pulse signal output from 16 differs as shown in FIG. 7A to 7C are voltage pulse signals ΦVRES1 to ΦVRES3 output from the reset vertical shift register 18, and FIGS. 8D to 8F are voltage pulse signals output from the read vertical shift register 14. ΦVRO1 to ΦVRO3, the figure (g) shows coordinates (1, 1)
Represents the voltage between the terminals of the photodiode 11 located at, and the time axis of each of these diagrams is represented by the same time scale. Further, each voltage pulse signal ΦHRES output from the reset horizontal shift register 20
Are the voltage pulse signals ΦVRES1 to Φ shown in FIGS.
The voltage pulse signal ΦHRO generated in the high level period of VRES3 and output from the read horizontal shift register 16 is the voltage pulse signal ΦVRO1 shown in FIGS.
Although it is generated during the high level period of ~ ΦVRO3, it is omitted in the figure.

The solid-state image pickup device according to the third embodiment differs from the first embodiment described above in that the resetting of each pixel is repeated several times instead of once while reading out one two-dimensional image. Is. Hereinafter, this reset method is called a multi-reset method. According to the third embodiment, the following effects can be obtained. In other words, when light that is strong enough to obtain an optical signal integration time that is equal to or less than the time required to read one screen is incident on the device, only one reset is performed for each pixel for each scan of all pixels. A phenomenon called so-called blooming occurs. In this blooming, when the time from when a signal is read out to a pixel is reset until the pixel is reset next, the charge generated by the light that has entered the photodiode during that period overflows from the photodiode, causing it to leak to other photodiodes. This is a phenomenon that begins to flow. In addition, a phenomenon such as smear that occurs when the overflowed charges flow out to the video line VL also occurs. However, according to the third embodiment, as described below, each pixel is reset several times while reading one screen, so that the resetting is performed before the photodiode is saturated. Therefore, even when intense light is irradiated, the electric charge does not overflow from the photodiode, and the phenomenon such as blooming or smear does not occur.

That is, paying attention to the photodiode 11 located at the coordinates (1, 1), as shown in FIG. 5G, at time t1, the pulse ΦVRES1 shown in FIG. This photodiode 11 is reset by a pulse ΦHRES1 (not shown) generated during the period. After that, accumulation of charges is started by the optical signal incident on the photodiode 11.
Next, at time t2, the photodiode 11
Signal is read by the pulse signal ΦVRO1 shown in FIG. 6D and the pulse ΦHRO1 (not shown) generated during this high level period, and at the same time, the read amplifier 17 pulls up and resets. After that, when the photodiode 11 at the coordinates (1,1) is not reset (single reset) as in the conventional image pickup apparatus, a large amount of electric charge generated by strong light incidence causes the photodiode potential. Goes down along the chain double-dashed line shown in FIG. 9G, and finally the electric charge is saturated at time t5 and overflows from the photodiode 11. However, according to the multi-reset method according to the third embodiment, after the signal is read at time t2, the photodiode 11 is reset at times t3, t4, and t6. Therefore, the potential of the photodiode 11 is reset each time before the potential of the photodiode 11 is completely lowered, and the electric charge does not overflow from the photodiode 11. Therefore, according to the third embodiment, the phenomenon such as blooming and smear described above does not occur, and it is possible to capture an image even when strong light is emitted.

[0037]

As described above, according to the present invention, the signal reading for each light receiving element is performed by the read row selecting circuit, the reading column selecting circuit and the signal reading circuit, and the signal reset for each light receiving element is the reset row. It is performed by a selection circuit, a reset column selection circuit, and a signal reset circuit. Therefore, the signal reading and the signal resetting are performed by separate and independent circuits. Therefore, the signal charge accumulation time of each pixel can be made shorter than the time required to read out all the pixels, and furthermore, it is possible to perform imaging without saturating each pixel even when a strong optical signal is emitted. Become.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a MOS solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts in the solid-state imaging device according to the first embodiment.

FIG. 3 is a timing chart of signals of respective parts in the solid-state imaging device obtained by modifying the first embodiment.

FIG. 4 is a timing chart of signals of respective parts in the solid-state imaging device according to the second embodiment of the present invention.

FIG. 5 is a timing chart of signals of respective parts in the solid-state imaging device according to the third embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional solid-state imaging device.

FIG. 7 is a timing chart of signals of respective parts in the conventional solid-state imaging device.

[Explanation of symbols]

11 ... Photodiode, 12 ... Reset MOSFE
T, 13 ... MOSFET for reading, 14 ... Vertical shift register for reading, 15 ... MO for reading line selection
SFET, 16 ... Horizontal shift register for reading, 17
... reading amplifier, 18 ... reset vertical shift register, 19 ... reset line selecting MOSFET, 20 ...
Reset horizontal shift register, 21 ... Reset power supply.

Claims (2)

[Claims] 1. A plurality of two-dimensionally arrayed light receiving elements for generating charges according to the amount of incident light, and a first light emitting element provided for each of the light receiving elements for interrupting the flow of charges to these light receiving elements. And a second switching element, a read row selection circuit that selects a first switching element group arranged in the row direction among the first switching elements for signal reading, and the first switching element. Of the elements, a read column selection circuit that selects a first switching element group arranged in the column direction for signal reading, and one first switching selected by the read row selection circuit and the read column selection circuit A signal readout circuit for reading out the amount of electric charge generated in the light receiving element corresponding to the element, and a signal resetting circuit for the second switching element group arranged in the row direction among the second switching elements. A reset row selection circuit, a reset column selection circuit for selecting a second switching element group arranged in the column direction among the second switching elements for signal reset, and a reset row selection circuit. And a signal resetting power supply that resets the electric charge of the light receiving element corresponding to the one second switching element selected by the circuit and the reset column selection circuit. 2. A plurality of photodiodes arranged two-dimensionally, a reset MOSFET and a read MOSFET whose sources are commonly connected to the cathodes of the photodiodes, and the photodiodes arranged in the row direction. The read vertical selection circuit that selects the read gate control line that commonly connects the gates of the read MOSFETs, and the drain of each read MOSFET that is provided in each of the photodiodes arranged in the column direction are common. A read line selection MOSFET provided for each read line to be connected, and the read line selection M
A readout horizontal selection circuit that performs gate control of the OSFET to select each readout line connected to a video line, a readout gate control line selected by the readout vertical selection circuit, and a readout horizontal selection circuit. Of the reset MOSFETs provided in the photodiodes arranged in the row direction and the signal readout circuit that reads out the amount of charge generated in the photodiodes arranged at the positions where the readout lines intersect with each other through the video lines. A reset vertical selection circuit that selects a reset gate control line that commonly connects the gates, and a reset line that commonly connects the drains of the reset MOSFETs provided in the photodiodes arranged in the column direction MOS for reset line selection FET and M for selecting this reset line
A reset horizontal selection circuit that performs gate control of the OSFET to select each of the reset lines connected to the reset signal line, a reset gate control line selected by the reset vertical selection circuit, and a selection by the reset horizontal selection circuit Solid-state imaging device including a signal reset power supply that resets the charges of the photodiodes arranged at the positions where the reset lines intersect with each other via the reset signal lines.