JPH05160823A - Clock interruption detection circuit - Google Patents

Abstract

PURPOSE:To prevent clock interruption mis-detection by having only to vary a voltage given externally even when a frequency of a clock being a detection object is changed. CONSTITUTION:When a clock pulse appears at a clock input (CLK), a P-channel MOS transistor(TR) 3 is turned on for a clock pulse rising period and an N- channel MOS TR 4 is turned off simultaneously and a charge is accumulated in a capacitor 5. The P-channel MOS TR 3 is turned off for a clock pulse trailing period and simultaneously the N-channel MOS TR 4 is turned on and the charge in the capacitor 5 is discharged. An output pulse rising of a comparator 6 is kept while a clock is inputted consecutively by selecting a discharge time constant larger than a charging time constant. When the clock frequency is changed, mis-detection of the clock interruption is prevented by adjusting a reference voltage VB1 when the clock frequency is chanted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detection circuit.

[0002]

2. Description of the Related Art In a circuit that uses a clock, it is often necessary to perform processing on the inside or the outside of the circuit depending on whether or not the clock is interrupted. For example, in the transmission circuit, since the clock failure is an abnormal state, it is necessary to control so that an unnecessary signal is not output at the time of the clock failure or to control the output end to high impedance.
Therefore, a circuit for detecting a clock break is required, and a conventional clock break detection circuit is composed of a time constant circuit using a resistor and a capacitor.

That is, the conventional clock loss detection circuit is
As illustrated in FIG. 4, a clock input (CLK) is applied to a time constant circuit composed of a resistor 8 and a capacitor 5 through inverters 1 and 7, and its output is connected to a first input terminal (IN1) of a comparator 6. It is configured. A reference voltage (V _B2 ) is connected to the second input terminal (REF) of the comparator 6, and a signal indicating the presence or absence of a clock is obtained at the output (OUT) of the comparator 6.

As shown in FIG. 5, a clock input (CL
When a clock pulse appears at K), it is integrated by the time constant circuit of the resistor 8 and the capacitor 5, and the voltage of the first input terminal (IN1) of the comparator 6 becomes the second input terminal (REF) of the comparator 6. _Becomes higher than the reference voltage (V _B2 ) input to the output terminal, and the pulse of the output (OUT) rises and is held.
After that, when the clock is no longer input, the voltage of the first input terminal (IN1) of the comparator 6 gradually decreases, and the reference voltage (V _B22 input to the second input terminal (REF) of the comparator 6 is input. ), The pulse of the output (OUT) falls to detect the wlock disconnection.

In the operation of such a conventional circuit, as shown in FIG.
As shown in, when the frequency of the clock input becomes lower, the discharge time during integration of the time constant circuit becomes longer, so that the voltage at the first input terminal (IN1) of the comparator 6 is higher than the reference voltage (V _B2 ). Occurs during a period in which the clock continues to be input, the output from the comparator 6 (OU
During T), a pulse trailing edge indicating a clock disconnection occurs.

[0006]

As described above, in the conventional clock loss detection circuit, since the time constants of the resistor 8 and the capacitor 5 are constant, erroneous detection of clock loss occurs when the frequency of the input clock changes, and this is prevented. In this case, the constant value of the resistor or capacitor must be changed according to the clock frequency, and the circuit is not versatile. In particular, when the clock frequency is low, it is necessary to increase the value of resistance or capacitance, which has a disadvantage of increasing the layout area.

[0007]

A clock loss detection circuit according to the present invention selects one of a first reference voltage and a ground voltage in accordance with an inverter to which a clock input is connected, and on / off of a pulse of the clock input. A switch circuit for sending, a source connected to a power source, a P-channel MOS transistor having a gate connected to the output of the inverter, a drain connected to the drain of the P-channel MOS transistor, and a gate connected to the output of the switch circuit. And an N-channel MOS transistor whose source is connected to the ground voltage, a capacitor connected between the drain of the P-channel MOS transistor and the ground voltage, and a first input terminal to the drain of the P-channel MOS transistor. The input terminal of is connected to the second reference voltage,
And a comparator that outputs a pulse indicating the high and low of both the voltages of the first and second input terminals.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
In the figure, the clock input (CLK) is the inverter 1
To the first input terminal (SW) of the switch circuit 2 and the second input terminal (IN2) of the switch circuit 2.
Is a reference voltage (V _B1 ), and the third input terminal (IN
A ground voltage is connected to 3). A power supply (VDD) is connected to the source of the P-channel MOS transistor 3, the output of the inverter 1 is connected to the gate, and a P-channel MO transistor 4 is connected to the drain of the N-channel MOS transistor 4.
The drain of the S transistor 3, the output (Q) of the switch circuit 2 is connected to the gate, and the ground voltage is connected to the source. The capacitor 5 is connected between the drain of the P-channel MOS transistor 3 and the ground, and the drain of the P-channel MOS transistor 3 is used as a reference for the first input terminal (IN1) of the comparator 6 and the second input terminal (REF). The voltage (V _B2 ) is connected to the output (OUT) so that a pulse indicating the clock detection result is obtained.

In this embodiment, as shown in FIG. 2, when a clock pulse appears at the clock input (CLK), the output pulse of the inverter 1 falls during the rising period of the clock pulse and the P-channel MOS transistor 3 turns on. Become. At the same time, the switch circuit 2 outputs the ground voltage input to the third input terminal (IN3), and the N-channel MOS transistor 4 is turned off accordingly. That is, in the rising period of the clock pulse, the P channel MOS transistor 3 is turned on and the N channel MOS transistor is turned on.
Since the transistor 4 is turned off, the capacitor 5 is charged with electric charges, and the voltage of the first input terminal (IN1) of the comparator 6 becomes higher accordingly, and when the voltage becomes higher than the reference voltage (V _B2 ), the output is made. The (OUT) pulse rises. afterwards,
In the falling period of the clock pulse, the output pulse of the inverter 1 rises and the P-channel MOS transistor 3 is turned off. At the same time, the switch circuit 2 outputs the reference voltage (V _B1 ) input to the second input terminal (IN2). If this reference voltage (V _B1 ) is set to a gate-source voltage at which the N-channel MOS transistor 4 turns on, it is discharged through the on-resistance of the N-channel MOS transistor 4. If the discharge time constant is made larger than the charge time constant, the voltage of the first input terminal (IN1) of the comparator 6 is always higher than the reference voltage (V _B2 ) while the clock is continuously input. Also becomes higher, and the output of the comparator 6 (O
UT) holds the pulse rise. After that, when the clock is no longer input, the first input terminal (IN
When the voltage of 1) decreases and becomes lower than the reference voltage (V _B2 ), the pulse of the output (OUT) falls and the clock interruption is detected.

In this embodiment, when changing the frequency of the clock to be detected, the on-resistance (R _ON ) of the N-channel MOS transistor is given by the following equation (1) by changing the reference voltage (V _B1 ). ..

[0012] _{R ON = L / μC O W} (V SG -V T) ......... (1) where μ is the mobility, C _O is the capacitance per unit area, W is the gate width, L is the gate The length, V _GS is the gate-source voltage, and V _T is the threshold voltage.

In the equation (1), μ, C _O , and V _T are constants determined by the process of the integrated circuit, and W and L are determined by the shape of the gate of the transistor. Therefore, R _ON is determined by V _GS. It can be changed.

When the clock frequency is lowered as shown in FIG. 3, the discharge time constant can be changed by adjusting the reference voltage (V _B1 ) as described above, and the broken line waveform can be changed to the solid line waveform. Detection can be prevented.

[0015]

As described above, according to the present invention, the discharge time constant of the time constant circuit is adjusted by changing the gate resistance of the N-channel MOS transistor according to the frequency of the input clock and adjusting the ON resistance thereof. The layout area can be reduced since the on-resistance of the transistor can be used instead of the resistance, while it can be varied and the versatility of the circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a signal timing chart according to the embodiment of the present invention.

FIG. 3 is a signal timing diagram according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional clock loss detection circuit.

FIG. 5 is a signal timing chart in a conventional circuit.

FIG. 6 is a signal timing diagram in a conventional circuit.

[Explanation of symbols]

 1,7 Inverter 2 Switch circuit 3 P channel MOS transistor 4 N channel MOS transistor 5 Capacitor 6 Comparator 8 Resistance

Claims (1)

[Claims] 1. An inverter having a clock input connected thereto,
A switch circuit for selectively transmitting one of a first reference voltage and a ground voltage according to ON / OFF of a pulse of the clock input, and a P-channel MOS transistor having a source connected to a power supply and a gate connected to the output of the inverter. When,
Between an N-channel MOS transistor having a drain connected to the drain of the P-channel MOS transistor, a gate connected to the output of the switch circuit, and a source connected to the ground voltage, and the drain of the P-channel MOS transistor and the ground voltage. Connected capacitor and first
Has an input terminal connected to the drain of the P-channel MOS transistor and a second input terminal connected to a second reference voltage, and outputs a pulse indicating the level of both the voltages of the first and second input terminals. A clock loss detection circuit comprising: a comparator.