JPH05167033A - Semiconductor device, semiconductor memory device, and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] In a semiconductor device in which the side wall of a groove dug in a substrate serves as a channel region, the distance from the bottom of the groove to the diffusion layer in the substrate surface region is defined as the plane dimension in the channel direction By making the length longer, it is possible to provide a semiconductor device in which a short channel effect and punch through do not occur even in a very fine dimension in plan view, and realize an ultrafine semiconductor memory device using this semiconductor device. .. A dynamic random access memory having a semiconductor device having a groove formed in a substrate as a channel 9 and a storage capacitor of a trench type or a laminated capacitance type. A static random access memory having a plurality of the above semiconductor devices. A non-volatile memory having a floating gate in the trench gate 11. [Effect] By forming the above-mentioned groove type channel,
It is possible to realize a semiconductor device and a semiconductor memory device which have no deterioration in characteristics even when the plane dimension is made fine or compared with conventional devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor memory device in which the short channel effect and punch through which become apparent with the miniaturization of the semiconductor device are completely controlled.

[0002]

2. Description of the Related Art A semiconductor memory device represented by a dynamic random access memory has realized a fourfold increase in the degree of integration in three years, and a mass production system for a 4-megabit memory has already been established. The research and development for the 16-megabit memory is underway. This high integration has been achieved by miniaturizing the element size. Along with this miniaturization, the storage capacitance decreases, which causes a problem such as a decrease in the signal-to-noise ratio. In this respect, the storage capacitance portion has a three-dimensional shape, that is,
The effective storage capacitance area has been increased by forming a trench in the semiconductor substrate or depositing a conductive film on the semiconductor substrate and using the surface of the conductive film as a storage capacitance portion.

As a result, even in a large scale memory,
Although it has become possible to secure a sufficient storage capacity, little attention has been paid to the problems associated with miniaturization in semiconductor devices that control the movement of charges to the storage capacity section. Among the problems of semiconductor devices associated with miniaturization, the most important problems are reduction in threshold voltage and reduction in punch-through breakdown voltage. The reduction in the threshold voltage makes it impossible to completely bring the channel of the semiconductor device into the non-conducting state, and it becomes impossible to store charges in the storage capacitor. Moreover, when punch-through occurs, the flow of charges moving in the channel region cannot be controlled.

As a structure capable of coping with the problem associated with the miniaturization of such a semiconductor device, I-E-E's International-Electronic-Devices-Meeting, Abstract (1986), shown in FIG.
p.132 (IEEE International Electron Devices Meeti
ng Abstract, 1986 p.132), by using the side wall of the trench dug in the silicon substrate as a channel,
A semiconductor memory device has been proposed which increases the effective channel length. In addition, in JP-A-59-61064, similarly,
A semiconductor memory device having a planar type memory cell and a groove type gate structure is shown. In FIG. 7, 1
Is a semiconductor substrate, 5 is a storage capacitance insulating film, 4 is a storage capacitance plate electrode, 7 is a nitride film, 9 is a trench gate, 10 is a gate oxide film, 11 is a gate electrode, 15 is a diffusion layer, and 16 is an interlayer insulation. The film 17 is a data line wiring.

[0005]

In the conventional trench gate semiconductor device shown in FIG. 7, the planar dimension of the trench in the channel direction is the same as the planar dimension of the gate electrode. In reality, the gate electrode (11) completely covers the groove-type channel (9) and also covers the diffusion layer region (15) on the surface of the semiconductor substrate. Because, if the gate electrode is not arranged in such a manner, a region of the gate oxide film (10) that is not covered with the gate electrode (11) is formed when the pattern alignment of the gate electrode (11) and the groove is bad. This is because. As a result of such a gate electrode arrangement, the capacitance to the substrate between the gate electrode (11) and the diffusion layer region (15) increases, the gate electrode delay increases, and the operating speed decreases. In addition, there is also a problem that a sufficient breakdown voltage cannot be ensured with other conductive layers. Therefore, the distance between the gate electrode (11) and the diffusion layer region (15) must be increased.

By the way, in the above-mentioned publicly known example, even in the case of a semiconductor device of a normal structure type, it has been discussed that the threshold voltage is sufficiently lowered and the punch-through phenomenon can be controlled. No special conditions are specified for the distance to the diffusion layer. However, as the miniaturization of semiconductor devices progresses further and becomes about 0.1 μm or less that can realize a memory of 1 gigabit or more, the distance from the bottom surface of the groove to the diffusion layer becomes smaller than the planar dimension in the channel direction of the groove. In a small semiconductor device, the characteristic deterioration cannot be suppressed even in the groove type channel. This is because the dimension of about 0.1 μm is such that the depletion layer extending from the diffusion layer overhangs to the bottom surface of the groove type channel. Therefore, in the future ultra-fine semiconductor device, the distance from the bottom surface of the groove to the diffusion layer is
It must be sufficiently large compared to the planar dimensions of the channel.

Further, the relationship between the power supply voltage and the threshold voltage becomes a big problem in the ultrafine semiconductor device. Up to the design dimension of 0.8 μm, 5V has been adopted, but with miniaturization, it has become necessary to lower the power supply voltage in order to ensure the reliability of the semiconductor device. According to this tendency, it is expected that the voltage will be 1.5 V in the age of 0.1 μm. However, the threshold voltage cannot be lowered correspondingly, and is expected to be about 0.5V. This is because a decrease in the threshold voltage causes an increase in leak current, which leads to an increase in power consumption and deterioration of charge storage characteristics.
As a result, there arises a problem that the operating margin and the signal-to-noise ratio are lowered.

Considering the above, it is considered that the power supply voltage cannot be lowered according to the tendency so far. However, there is an upper limit to the substrate concentration from the viewpoint of reliability, and it is necessary to widen the distance between the bottom surface of the groove and the diffusion layer even in the semiconductor device having the groove type gate. as a result,
In a semiconductor device having a gate plane dimension of 0.1 μm or less, the distance from the groove bottom surface to the diffusion layer is larger than the groove plane dimension.

[0009]

In order to solve some of the above problems, in the present invention, as shown in FIG. 1, on the surface of a semiconductor substrate (1) having an element isolation region (2), A structure was devised in which an insulating film (7) was deposited, a hole for forming a channel region was opened in this insulating film, and a side wall insulating film (8) was provided on the side wall of the hole. Further, the depth of the groove serving as the channel is set to be sufficiently deep with respect to the depth of the diffusion layer determined by ion implantation and subsequent heat treatment. Therefore, the depth of the groove is set so that the dimension in the channel direction of the groove defined by the region sandwiched by the sidewall oxide film (8) becomes smaller than the distance from the bottom surface of the groove to the end of the diffusion layer. Was set.

Here, 1 is a semiconductor substrate, 2 is an element isolation region, 7 is an insulating film, 8 is a sidewall insulating film, 9 is a groove to be a channel, 10 is a gate oxide film, 11 is a gate electrode, and 12 is a gate. An oxide film on the electrode, 13 is a sidewall oxide film, 14 is a pad to be a stacked diffusion layer, 15 is a diffusion layer, 16 is an interlayer insulating film, and 19 is a metal wiring.

[0011]

By the insulating film (7) on the semiconductor substrate,
Compared with the conventional structure in which the gate electrode is in direct contact with the substrate, the breakdown voltage and capacitance between the gate electrode and the substrate do not pose a problem. Further, since the size of the trench type gate to be dug in the substrate is determined by the interval sandwiched by the sidewall oxide film (8), it is possible to realize a trench dimension smaller than the minimum dimension by lithography. This indicates that ultra-fine processing of 0.1 μm can be performed by the current optical lithography of about 0.3 μm and the control of the thickness of the sidewall oxide film. Further, in the structure of the present invention, the sidewall insulating film (8) also serves as an overlap region between the gate electrode and the substrate, so that the gate size can be set to the minimum size. As a result, miniaturization of the semiconductor device is promoted.

Further, since the distance from the bottom surface of the groove to the diffusion layer is sufficiently separated, even if the power supply voltage does not decrease, the short channel effect and punch through can be effectively performed without increasing the substrate concentration. The phenomenon can be suppressed.

FIG. 8 shows the result of an experimental examination of this. Here, the black circles represent the relationship between the threshold voltage and the planar dimensions of the channel when the bottom surface of the groove and the edge of the diffusion layer are substantially aligned and the white circles are separated by about 0.2 μm. Apparently, the longer the distance from the edge of the diffusion layer to the bottom of the groove, the better the short channel characteristics.

[0014]

EXAMPLE A method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

First, a first conductivity type region (121) and a second conductivity type region (12) are formed on a first conductivity type semiconductor substrate.
2) is formed. Although details of the forming method are omitted, impurities can be separately implanted by an ion implantation method, or an oxide film serving as a mask for ion implantation can be grown in one region by using a known selective oxidation method, and then the impurities can be removed. There are methods such as breaking up. An element isolation oxide film (2) is formed on this substrate. In this example, a well-known trench isolation method was adopted to form a deep groove and to control a leak current on the side wall, and an oxide film was formed up to 0.5 μm from the substrate surface. Then, an impurity layer (15) which will be a diffusion layer of the semiconductor device is further formed by ion implantation.
At this time, needless to say, a mask of an organic film is necessary in order to implant impurities different from the conductivity type of the substrate. Here, the reason for implanting the impurities in advance is that the surface of the substrate is covered with an insulating film as described later in this embodiment. The impurity concentration should be about 1 × 10 ²⁰ / cm ³ ,
The amount of driving was controlled.

On this, as shown in FIG. 15, an insulating film of about 100 nm is deposited by a known vapor deposition method. In this embodiment, since the oxide film (2) is used for element isolation,
A nitride film was used as the insulating film. An opening reaching the surface of the substrate is opened by using an organic film pattern for this nitride film (7). Further, a nitride film (8) is deposited again on this surface, and the whole surface is etched by a known anisotropic etching. As shown in the figure, a sidewall insulating film (8) is formed on the sidewall of the opening. It That is, even if the opening of the nitride film (7) is 0.3 μm, if the sidewall nitride film is 0.1 μm, the opening of 0.1 μm can be obtained in a self-aligned manner.

Further, as shown in FIG. 16, the nitride film (7, 8) is used as a mask to form a groove penetrating the diffusion layer region (15) on the substrate surface. The depth of the diffusion layer is 0.1μ
The groove size was about 0.1 μm, and the groove depth was 0.3 μm.

Next, as shown in FIG. 17, after removing contamination and damage due to substrate processing by cleaning and sacrificial oxidation, a gate oxide film (10) is grown on the surface of the groove, and a gate electrode and a gate electrode are formed on the gate oxide film. To deposit a conductive layer. Usually, polycrystalline silicon containing impurities is used, but in this embodiment, since the substrate surface is covered with a relatively thick insulating film (7), it is preferable to use a high melting point low resistance metal such as tungsten. it can. On the other hand, in the conventional semiconductor device, this tungsten must be processed on the thin gate oxide film, but since the selection ratio between tungsten and the oxide film is small,
Until now, it has been difficult to process. If a metal such as tungsten is used, the gate resistance can be reduced. On the gate electrode (11), an oxide film (1
2) is deposited and processed into a gate electrode shape, and the gate electrode is processed using the oxide film (12) as a mask.

Further, as shown in FIG. 18, only the side wall of the gate electrode is covered with the side wall oxide film (13) to insulate the gate electrode in a self-aligned manner. Further, the nitride film (9) deposited on the surface of the substrate is removed to expose the diffusion layer of the substrate.

Next, a conductive layer (14) of polycrystalline silicon is deposited on the entire surface of the substrate, and this is separated as shown in FIG. In each semiconductor device, the conductivity type of the exposed diffusion layer is different, so that the conductive layer polycrystalline silicon (14) has the same conductivity type as the diffusion layer (15) in contact. , Separate impurities.

Finally, as shown in FIG. 20, the interlayer insulating film (1
4) is deposited and flattened, contact holes reaching the stacked diffusion layer of the underlying layer are opened, and metal wiring (19) is formed to complete the semiconductor device of the present invention.

FIG. 2 shows a semiconductor device according to the second embodiment of the present invention. The structure of the trench gate is the same as that of the first embodiment of FIG. 1, except that the stacked diffusion layer (1
4) is formed first, and this is used instead of the insulating film (7) in FIG. 1 to form a groove. As a result, the distance from the stacked diffusion layer to the end of the gate electrode of the semiconductor device can be reduced, so that the resistance of the diffusion layer can be reduced. Although details of the manufacturing method are omitted, a conductive film (1) is used instead of the nitride film (7) in Example 1 of FIG.
4) and an oxide film (12) are used to form an opening, and a sidewall nitride film (8) is used to form a groove in a self-aligned manner.

Next, an embodiment of a semiconductor memory device using the semiconductor device of the present invention will be described with reference to FIG. In this embodiment, a trench capacitor cell having a trench type storage capacitance in a substrate will be described. Trench capacitor cells employ a structure in which the periphery of the trench is covered with an oxide film in order to narrow the cell spacing while suppressing the leak current between adjacent cells. Also in this embodiment, the oxide film (3) is formed on the side wall of the trench dug in the substrate (1). Although the details of the manufacturing method will be described later, an insulating film (7) is deposited on the surface of the substrate having the trench capacitor,
Only the region to be the channel is exposed, and the sidewall insulating film (8) is further formed to determine the dimension of the channel region. Using this insulating film (8) as a mask, a groove type channel (9) as shown in the figure is dug to form a gate oxide film (10) and a gate electrode (11). In addition, the data line (17),
A metal wiring (19) is attached to complete the memory cell. Here, 1 is a semiconductor substrate, 2 is an element isolation oxide film, 3 is a trench sidewall oxide film, 4 is a plate electrode, 5 is a capacitor insulating film, 6 is a counter electrode, 7 is a substrate insulating film, and 8 is a substrate. Side wall insulating film of insulating film, 9 is a channel groove, 10 is a gate oxide film, 11 is a gate electrode, 12 is a gate electrode oxide film, 13 is a side wall oxide film of a gate electrode, 14 is a diffusion layer of a transistor and a capacitor. Is a pad for connecting to the counter electrode of, a diffusion layer, 16 is an interlayer insulating film, 17 is a data line, 18 is an interlayer insulating film, and 19 is a metal wiring. Figure 9
FIG. 4 shows a plan view of the memory cell of FIG. In this example, the known folded data line system is adopted, but as shown in the figure, the plate electrode (32) has a slanted layout, so that it is different from the conventional folded data line system. , The layout is slightly different.
The minimum design dimension is 0.15 μm. This is 256
It is a size that can realize memory from megabit to 1 gigabit. Here, 30 is a pattern for forming an active region of the transistor and growing an inter-element isolation oxide film on the other surface. Reference numeral 31 is a pattern for digging a trench, and 32 is a plate electrode. Normally, the plate electrode is arranged so as to cover the entire surface of the trench. However, when the plate electrode becomes extremely fine as in the memory cell shown in the present embodiment, the plate electrode must be arranged in such an inclined manner.
After forming the trench capacitor, an insulating film is deposited on the entire surface of the substrate, and a region shown as a groove type channel is opened using the pattern shown by 33. As described above, the actual dimensions of the channel are determined by the film thickness of the sidewall insulating film in the opening formed by this pattern. Therefore, as described above, no overlap region as a mask alignment margin is required between the word electrode 34 and the groove formation pattern 33, and a margin corresponding to the film thickness of the sidewall oxide film can be provided. .. After forming the word electrodes, 35 pads are arranged. This pad plays a role of an intermediate conductive layer when connecting the counter electrode of the trench capacitor and the diffusion layer or connecting the data line and the diffusion layer. Furthermore, as a data line contact,
36 contact holes are arranged. In addition to these, there are data line wiring and metal wiring, but they are omitted in this figure for simplicity.

Next, a method of manufacturing the semiconductor memory device of the third embodiment will be described with reference to FIGS. In this description, only the memory cell is focused and the description of the other peripheral circuits is omitted. However, the complementary semiconductor device used in the peripheral circuit is also referred to as a semiconductor memory device as described in the first and second embodiments. It can be created in exactly the same process.

Next, a method of making will be described.

First, as shown in FIG. 21, an element isolation oxide film (2) is formed on the surface of the semiconductor substrate (1). At this time, in this embodiment, in order to form a groove type channel, the trench element isolation method is used in which the edge of the oxide film is substantially perpendicular to the substrate. As a result, even if a groove type channel is formed, it is possible to prevent a side wall leakage current along the element isolation. The film thickness of the element isolation oxide film is 0.5 μm, and the surface is almost flat.

An organic film serving as a mask is applied to the substrate on which the element isolation oxide film is formed, and trenches (21) are dug as shown in FIG. The depth of the trench is about 2 μm and the diameter of the trench is about 0.2 μm. The trench is also formed in the inter-element isolation oxide film region as shown in the plane pattern of FIG.

Next, as shown in FIG. 23, trenches (21)
An oxide film (3) covering the inner surface of the substrate and the substrate surface is deposited to a film thickness of about 30 nm using a known chemical vapor deposition method.
This oxide film has a role of preventing a leak current between the trenches. Further, if a known vapor deposition method is used, an oxide film can be deposited even inside such a deep trench.

Further, as shown in FIG. 24, a polycrystalline silicon film (4) to be a plate electrode of the trench capacitor is deposited on the entire surface of the substrate to a film thickness of about 20 nm. At this time, in this embodiment, a method of depositing polycrystalline silicon containing impurities was adopted. This is to introduce a gas containing impurities into the reaction furnace together with a gas containing silicon. In practice, phosphine gas was introduced together with monosilane gas to form a polycrystalline silicon film containing phosphorus. Then, an organic film (22) pattern as shown in FIG. 24 is formed in order to obtain the plate electrode shape shown by the plane pattern of FIG. Here, a method is adopted in which the inside of the trench is once backfilled with an organic film and a pattern is formed thereon. Then, using this pattern, the plate electrode is processed into a desired shape.

After forming the plate electrode (4), a capacitor insulating film (5) is grown on the surface of the polycrystalline silicon as shown in FIG. The capacitor insulating film is made of a laminated film of an oxide film and a nitride film and has a film thickness of 5 nm. Further, a polycrystalline silicon film (6) to be a counter electrode is deposited on this capacitor insulating film. Here, similarly to the plate electrode, a polycrystalline silicon film containing phosphorus as an impurity was deposited. Then, of this polycrystalline silicon (6), only the portion exposed on the substrate surface is selectively removed to obtain the structure shown in FIG. At this time, in order to leave the plate electrode (4) on the substrate, the processing of the counter electrode (6) must be stopped by the thin capacitor insulating film (5) on the plate. In order to achieve this, when etching the polycrystalline silicon, between the capacitor insulating film,
A sufficient selection ratio must be secured. At present, the selection ratio is about 50, which is sufficient to perform the processing of this embodiment.

Next, as shown in FIG. 26, the entire surface is
Cover with insulating film. In this example, a 100 nm silicon nitride film (7) was deposited. A known vapor deposition method was also used for depositing the nitride film.

On the nitride film (7), as shown in FIG. 27, a pattern is formed with an organic film (22). The shape of this pattern is as shown in the plan view of FIG. Then, using this pattern, the nitride film (7) and the oxide film (3) thereunder are processed to expose the substrate surface.

After removing the organic film (22) used as a mask, a nitride film (8) is deposited again, and the entire surface of this nitride film is etched by a known anisotropic etching method, as shown in FIG. In addition, the nitride film remains only on the side wall. The film thickness of the deposited nitride film is 100 nm. As a result, for example, 0.3
Even if the groove is opened with a dimension of .mu.m, the sidewall nitride film (8) can realize a planar dimension in the channel direction of about 0.1 .mu.m in a self-aligned manner. Further, using this nitride film as a mask, the exposed silicon substrate is dug down as shown in FIG. In this example, 0.3 μm was dug.

After the contamination and damage of the substrate due to the above dry etching are removed by a method such as cleaning and sacrificial oxidation, a gate oxide film (10) is formed on the surface of the groove as shown in FIG. Grow by thermal oxidation method. The oxidation temperature is 800 ° C., and the oxidizing atmosphere is a mixed atmosphere of oxygen and water vapor. The thickness of the gate oxide film is 5 to 10 nm.
A gate electrode (11) is deposited thereon by a known vapor deposition method. In this embodiment, the doped polysilicon deposition method is used in which polycrystalline silicon containing impurities is deposited in consideration of the fine grooves. The film thickness is 100 nm. Generally, polycrystalline silicon is used, but as described in the first embodiment, a refractory metal such as tungsten or an alloy film such as silicide can be used as the gate electrode. When such a low resistance metal is used for the gate electrode, the resistance of the gate electrode is lowered, and thus the metal wiring (19) as described later is unnecessary.
An oxide film (12) is deposited to 100 nm on this gate electrode. This oxide film not only insulates the gate electrode, but is also used as a mask for processing the gate electrode (11). As a result of this processing, the structure shown in FIG. 30 is obtained.

Further, as shown in FIG. 31, an oxide film (13)
Is deposited and the entire surface is etched by a known anisotropic etching method, the oxide film (13) remains only on the side wall of the gate electrode, and this and the oxide film (12) on the gate electrode form a gate. The electrode (11) is completely and self-alignedly insulated.

Then, as shown in FIG. 32, a contact hole for connecting the data line contact portion, the diffusion layer of the transistor and the counter electrode inside the trench capacitor is opened. At the time of opening the contact, the oxide film (12, 13) covering the gate electrode (11) is used as a mask and the nitride film (7) thereunder is first etched.
Since a selection ratio can be secured during dry etching between the oxide film and the nitride film, under the condition that the nitride film is preferentially etched, the nitride film can be processed without reducing the film thickness of the oxide film. It is possible. Further, the oxide film (3) under the nitride film (7) must also be etched, but since this is thinner than the oxide film (12) on the gate electrode, it is difficult to process it. At this time, the gate electrode is not exposed. It goes without saying that, in processing, not only the difference in the selection ratio is used, but also the organic film is used as a mask.

Next, as shown in FIG. 33, polycrystalline silicon is embedded in the contact hole to form a pad (14) which is an intermediate conductive layer. This pad (14)
Is a conductive layer that connects the counter electrode (6) inside the trench capacitor and the diffusion layer (15), and also a conductive layer that connects the data line and the diffusion layer, as described later. The diffusion layer (15) is formed by diffusing impurities from this pad.

Next, as shown in FIG. 34, an oxide film (16) for interlayer insulation is deposited on the entire surface and flattened. In this embodiment, an oxide film containing high concentrations of boron and phosphorus is deposited and planarized by a method of fluidizing the oxide film at about 850 ° C. Further, as shown in the figure, the data line contact is opened to form the data line (17). Tungsten was used as the material of the data line.

Finally, as shown in FIG. 26, an interlayer insulating film (18) is again deposited and planarized, and then a contact for connecting to an underlying conductive layer is opened, and then a metal wiring (19) is formed. ) Is formed. A laminated film mainly made of aluminum was used for the wiring. This metal wiring (19)
Is used to reduce the resistance of the gate electrode (11),
Here, it is connected to the gate electrode at a place not shown. As described above, if a low resistance metal is used for the gate electrode (11), this metal wiring becomes unnecessary and the number of manufacturing steps can be reduced.

Through the steps described above, the semiconductor memory device of the third embodiment of the present invention shown in FIG. 3 is completed.

Next, a fourth embodiment will be described with reference to FIG. In this embodiment, a case of a laminated capacitive cell will be described. Unlike the above-described embodiment, the stacked capacitance type cell has the charge storage capacitor formed on the semiconductor substrate. This has the characteristic that it is easy to make because it has the same essential structure as the planar type cell adopted up to 1 Mbit memory. Therefore, many manufacturers have adopted this structure up to about 16 Mbits.

The feature of this structure is that the charge storage capacitors (4, 5, 6) extend to above the word electrode (11). As a result, the storage capacitance can be increased as compared with a simple planar structure.

In this embodiment, the grooved gate semiconductor device of the present invention is applied to this laminated capacitance type cell. The fabrication method of this embodiment will be described later, but it is essentially the same as the case of the trench cell described above, and the insulating film (7) on the substrate and the sidewall insulating film (8) thereof are used as a mask to form the substrate (1 ) To dig a groove (9). The numbers described in FIG. 4 correspond to those in FIG. Here, 23 is an oxide film.

FIG. 10 shows a plan view of the semiconductor memory device according to the embodiment shown in FIG. Here, as in the third embodiment, the folded data line type memory cell is shown. Reference numeral 30 is a pattern that determines the active region. With this, an active region and an element isolation region are determined, and an insulating film is deposited on the active region and the element isolation region, and this is separated into 33 patterns in a pattern parallel to the word electrode (34). In the above-described third embodiment, the opening pattern that exposes only the region to be the channel is used, but this is a device for not exposing the plate electrode, and in this embodiment, such a periodic pattern is used. This is more convenient for forming a fine pattern by the phase shift method. Reference numeral 35 is a storage capacitor portion, and 36 is a data line contact.

Next, a method of manufacturing the semiconductor memory device according to the fourth embodiment will be described with reference to FIGS.

First, an element isolation oxide film (2) for electrically isolating each element is formed on a semiconductor substrate (1).
Here, as in the case of the third embodiment, a well-known trench element isolation method is used in which a groove is formed in the substrate and the groove is filled back. The thickness of the oxide film (2) is 0.5 μm.

Next, as shown in FIG. 37, an insulating film (7) is deposited on the surface of the substrate by a known vapor deposition method. The film thickness was 0.1 μm, and a nitride film was used as in the third embodiment.

An organic film (22) is applied on this, and an opening is formed on this by using a lithographic technique as shown in FIG. Then, using this organic film as a mask, the underlying nitride film (7) is dry-etched to expose the substrate. At this time, as shown in FIG.
The openings are provided using a pattern (33) parallel to 4).

Further, after removing the organic film and cleaning the surface, a nitride film (8) is deposited again and the entire surface is etched by a known anisotropic dry etching method, as shown in FIG. Then, the above-mentioned nitride film remains only on the side wall of the nitride film (7), and the side wall nitride film (8) is formed. This allows the openings to be self-aligned and smaller than the dimensions determined by lithography.

Further, using the nitride films (8, 9) as a mask, trenches (9) are dug in the substrate as shown in FIG.
The dug depth is 0.3 μm.

After removing damage and contamination of the substrate due to the above dry etching by cleaning and sacrificial oxidation, as shown in FIG. 41, a gate oxide film is grown around the groove. The method of growing the gate oxide film and the film thickness thereof are as described above.

Next, as shown in FIG. 42, polycrystalline silicon containing impurities, tungsten or the like is deposited as a word electrode (11). Further, an oxide film (12) is deposited on this, and as described above, the oxide film is first processed into a gate electrode pattern, and this is used as a mask to process the underlying word electrode (11).

Next, an oxide film (100 nm) is deposited on the entire surface of the substrate, and the entire surface is etched by anisotropic dry etching to form a sidewall oxide film (13) as shown in FIG. Further, a hole is opened in the nitride film (7) by utilizing the selection ratio of the oxide film (12, 13) covering the word electrode (11) and the nitride film (7) covering the substrate. At this time, although the mask pattern of the organic film is formed as described above, it is omitted here.

Further, an oxide film (23) is formed on the surface of this substrate.
(50 nm) is deposited to expose only part of the substrate as shown in FIG. As will be described later, this oxide film has a function of protecting the data line contact region sandwiched by the word electrodes (11) when forming the storage capacitor.

Polycrystalline silicon (6) containing impurities is deposited on this, and this is processed into a pattern of storage electrodes as shown in FIG. In the stacked capacitance type cell, the surface area of the storage capacitor portion determines the amount of stored charge. In this example, 0.3 μm of polycrystalline silicon was deposited.

Next, as shown in FIG. 46, a capacitor insulating film (5) is formed on the surface of the storage electrode (6).
As the capacitor insulating film, a high dielectric constant film such as tantalum pentoxide can be used in addition to the laminated film of the oxide film and the nitride film shown in the third embodiment. The reason is that, unlike the trench type cell, there is no high temperature heat treatment after the formation of the capacitor insulating film. A plate electrode (4) is formed on the capacitor insulating film (5) and processed to open a data line contact region surrounded by a word line (11). For this plate electrode (4), tungsten or the like can be used in addition to polycrystalline silicon.

Thereafter, as shown in FIG. 47, the entire surface of the substrate is covered with an interlayer insulating film (16) and planarized, and a data line contact is opened in this to form a data line (17). Tungsten is used in this embodiment. The film thickness is about 0.2 μm.

Finally, as shown in FIG. 48, the interlayer insulating film (18) is formed again, the metal wiring (19) is formed, and the semiconductor memory device of the fourth embodiment of the present invention shown in FIG. 4 is completed. To do. As described above, when a low resistance metal is used for the gate electrode (11), the metal wiring (19) can be omitted.

By the way, in the above-mentioned fourth embodiment, the laminated capacitance type cell having the simplest structure has been described. However, in the cell having this structure, it is difficult to deal with the decrease in the amount of accumulated charges as the cell area is reduced. The reason for this is that the data line contacts the substrate through the opening of the plate electrode, and the plate electrode opening limits the area of the storage electrode.

There is a possibility that this problem can be solved.
6 is a fifth embodiment of the present invention shown in FIG. In this semiconductor memory device, the data line (1
7) is characterized in that it is below the storage capacitor section (4, 5, 6). Therefore, the plate electrode (4) does not need an opening, and the storage capacitor lower electrode (6) can be arranged in the minimum space determined by the minimum processing size. As a result, it is possible to obtain about 1.5 times the accumulated charge amount as compared with the above-mentioned stacked capacitive cell.

FIG. 11 shows a plan view of the semiconductor memory device of this embodiment. The feature of this layout is that the pattern forming the active region (30) is different from that of the word electrode (3).
4) and the point which is inclined with respect to the data line (omitted). This is to secure the space for opening the contact hole reaching the substrate through the gap between the word line and the data line because the storage capacitance is performed after the formation of the data line. Also in this layout, the pattern (33) for digging a groove in the substrate is a pattern parallel to the word electrode (34). Here, 37 is a storage capacitor contact, 3
Reference numeral 8 is a storage capacity. As described above, the storage capacitor patterns (38) are arranged in the closest arrangement with the minimum processing size.

Next, a method of manufacturing the semiconductor memory device of the present invention will be described with reference to FIGS. Since the structure of the present invention is essentially the same as that of the laminated capacitance cell shown in the fourth embodiment, the material of the film to be deposited, its thickness, etc. are omitted in this embodiment.

First, as shown in FIG. 49, an element isolation oxide film (2) is formed on a substrate. A nitride film (7) is deposited on this (FIG. 50), and as shown in FIG.
Using the organic film (22) as a mask, the nitride film (7) is processed to expose the substrate. A nitride film (8) is again deposited on this nitride film (7) and anisotropically etched to form a sidewall nitride film (8) as shown in FIG. Using this nitride film (7) as a mask, the substrate is dug down to form a groove serving as a channel, as shown in FIG. Then, as shown in FIG. 54, a gate oxide film (10) is grown around the groove. Then, the gate electrode (11) and the oxide film (12) thereon are deposited, and the gate electrode is processed by using this oxide film as a mask (FIG. 55). After that, a sidewall oxide film (13) is formed on the sidewall of the gate electrode to insulate the gate electrode in a self-aligned manner (FIG. 56).

The subsequent steps are different from those of the semiconductor memory device of the fourth embodiment. First, an oxide film (23) is deposited on the entire surface of the substrate (FIG. 57). Here, the oxide film (23) in the bit line contact portion sandwiched by the word electrodes is removed to expose the substrate. Next, as shown in FIG. 58, an electrode (17) to be a data line is deposited and an oxide film (12) is formed thereon. Before forming this data line,
A so-called flattening process is performed to eliminate the unevenness due to the word lines, but it is omitted here. A silicide wiring was used for the data line. Further, as shown in FIG. 59, the sidewall of the data line (17) is covered with the sidewall oxide film (13) to insulate the data line. At this time, a portion where the storage capacitor is in contact with the substrate is opened. Further, one diffusion layer (15) of the transistor is formed by impurity diffusion from the data line. Then, as shown in FIG. 60, the lower electrode (6) of the storage capacitor is made of polycrystalline silicon. Storage electrode (6)
Are formed on word lines and bit lines. After this,
A capacitor insulating film (59) and a plate electrode (4) are formed to form the structure shown in FIG. Since the plate electrode has no opening, the storage electrode (6) can be laid out as large as possible, as described above. Finally, as shown in FIG. 62, the interlayer insulating film (18) and the metal wiring (19) are formed to complete the semiconductor memory device of the fifth embodiment of the present invention.

The semiconductor memory device having the semiconductor device of the present invention is not limited to the dynamic random access memory,
It is applicable to all kinds of semiconductor devices. An example thereof will be described using the example of the static random access memory shown in FIG. As shown in the circuit diagram of FIG. 12, this semiconductor memory device has a P-type MOSFET (Metal O
xide Semiconductor Field
A so-called flip-flop circuit in which the gate input terminals of two sets of semiconductor devices each consisting of an Effect Transistor (111) and an N-type MOSFET (110) are used as a trap, and an N-type MOSFET (109) for signal transmission is connected to the output terminal. Is configured. This allows the memory to be retained as long as the charge is supplied from the power source. This is a big difference from the dynamic type in which the refresh operation must be performed at regular intervals, and the power consumption can be reduced.
However, there is a drawback that the cell area becomes large because six FETs are required. Also in this static random access memory, when the gate length of the FET becomes small and the short channel effect becomes remarkable, the FET that must be non-conductive becomes conductive, and it becomes impossible to retain the memory. The semiconductor device of the present invention is also an effective solution to this problem. In FIG. 6, 101 is a transmission transistor and corresponds to the transistor 109 in FIG. Reference numeral 102 denotes a driving transistor, which corresponds to the transistor 110 in the plan view.

In this embodiment, as a P-type MOSFET, a MOSFE having stacked polycrystalline silicon as a substrate is used.
T is used. Reference numeral 104 denotes a gate electrode of a P-type MOSFET, and a polycrystalline silicon film (106) serving as a substrate is deposited via a gate oxide film (105). The gate electrode (104) is in contact with the substrate via the intermediate conductive layer (14). In this figure, 103 is a ground electrode, 1
Reference numeral 07 is an interlayer insulating film, and 108 is a wiring.

FIG. 13 shows a part of a plan view of this semiconductor memory device. Here, the active area (112)
, And only the word electrode (115) and the mask of the groove type channel are shown. By arranging the groove-type channel mask in this way, a static semiconductor memory device can be obtained.
The semiconductor device of the present invention can be applied.

Next, a method of manufacturing the semiconductor memory device of the sixth embodiment will be described with reference to FIGS. First, as shown in FIG. 63, an element isolation oxide film (2) is formed on a semiconductor substrate (1). The element isolation oxide film is the same as in the previous embodiments. Next, as shown in the figure, an impurity region (15) to be a diffusion layer is previously formed by a known ion implantation method. It goes without saying that there is no problem even if it is formed by impurity diffusion from polycrystalline silicon as in the above-described embodiments.

Next, as shown in FIG. 64, a nitride film (7) is deposited on the surface of the substrate. The film thickness is about 0.1 μm.
A nitride film (8) is deposited again on this nitride film (7),
As shown in FIG. 65, the sidewall nitride film (8) is formed by the anisotropic etching method. Then, using this nitride film as a mask, as shown in FIG. 66, a groove (9) to be a channel is formed in the substrate.
Dig in. Further, as shown in FIG. 67, a gate oxide film (10) is grown around the groove. Then, as in the above-described embodiments, the gate electrodes (101, 102) and the oxide film (12) thereon are deposited, and the gate electrode is processed using the oxide film (12) as a mask ( 68). Next, the periphery of the gate electrode is covered with an oxide film (13) to insulate the gate electrode (FIG. 69).

Further, the oxide film (1
3, 12) and the organic film not shown here are used as a mask to remove the nitride film (7) at a desired position to expose the substrate (FIG. 70). Polycrystalline silicon (14) is embedded in the exposed portion of the substrate to form an intermediate conductive layer (FIG. 7).
1). Polycrystalline silicon (103), a part of which serves as a ground electrode, is deposited on this intermediate conductive layer and processed into a desired shape. The processing of the polycrystalline silicon (103) is performed on the oxide film formed on the gate electrode. Therefore, it is necessary to open a contact hole where it is desired to make contact with the intermediate conductive layer (14) below. Yes (Fig. 72). Furthermore, FIG.
As shown in FIG. 6, the interlayer insulating film (18) covers the surface of the substrate to expose a part of the intermediate conductive layer (14).
Polycrystalline silicon (104), which will be the gate electrode of the stacked P-type MOSFET, is deposited and processed into a desired shape. Furthermore, P-type MOSF is formed on this polycrystalline silicon.
An oxide film (105) to be the gate oxide film of ET is formed, and n-type polycrystalline silicon (106) to be the substrate of the stacked FET is further deposited (FIG. 74). A p-type diffusion layer is formed on this polycrystalline silicon.
Impurities are implanted using a mask not shown. Further, as shown in FIG. 75, the interlayer insulating film (1
8) to form the first-layer metal wiring (19), and finally, as shown in FIG. 76, the second-layer interlayer film (107) and wiring (108) are formed to form the sixth embodiment of the present invention. The semiconductor memory device of the above embodiment is completed.

The structure of the present invention can also be applied to a non-volatile memory. FIG. 77 shows a cross-sectional structure of a conventional nonvolatile memory having a floating gate structure. Where 1
Is a semiconductor substrate, 15 is a diffusion layer, and 116 is a high-concentration layer having the same conductivity type as the substrate. This concentrates the electric field at the drain end and effectively generates hot carriers, which tunnel through the gate oxide film, and the charges are stored in the electrode (11) which is the floating gate. Even with such a structure, when the area of the gate electrode becomes smaller, there is a problem that a sufficient amount of charge cannot be stored.

On the other hand, as shown in FIG. 78, in the structure of the present invention in which the floating gate (11) is provided in the groove type channel, a sufficient charge amount can be secured even with an element having a fine gate length. Therefore, the problems described above can be solved. In addition, the floating gate (11) and the diffusion layer region (15,
Since the overlap of 16) can be increased, there is a possibility that the write voltage can be lowered.

[0073]

As described above with reference to some embodiments, in the semiconductor memory device having the trench type gate of the present invention, the short channel effect and the punch through phenomenon are suppressed while the planar size is reduced. Since a transistor that does not generate at all can be manufactured, a dynamic random access memory having excellent charge retention characteristics or a static random access memory with low power consumption can be manufactured. Further, in principle, the plane size can be set to 0.05 μm or less, which means that a 16 Gbit class memory is also possible.

[0074]

[Brief description of drawings]

FIG. 1 is a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 5 is a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 6 is a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 7 is a conventional trench capacitor semiconductor memory device having a trench gate.

FIG. 8 is a diagram showing short channel characteristics of the trench gate MOSFET of the present invention.

FIG. 9 is a plan view of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 10 is a plan view of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 11 is a plan view of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 13 is a plan view of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 16 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 17 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the invention.

FIG. 18 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 19 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 20 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 21 is a manufacturing process diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 22 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 23 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 24 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 25 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 26 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 27 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 28 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 29 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 30 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 31 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 32 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 33 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 34 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 35 is a manufacturing process diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 36 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 37 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 38 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 39 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 40 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 41 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 42 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 43 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 44 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 45 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 46 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 47 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 48 is a manufacturing process diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 49 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 50 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 51 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 52 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 53 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 54 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 55 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 56 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 57 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 58 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 59 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 60 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 61 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 62 is a manufacturing process diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 63 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 64 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 65 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 66 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 67 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 68 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 69 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 70 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 71 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 72 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 73 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 74 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 75 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 76 is a manufacturing process diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 77 is a nonvolatile memory using a conventional transistor structure.

FIG. 78 is a nonvolatile memory using the transistor structure of the present invention.

[Explanation of symbols]

1-semiconductor substrate, 2-element isolation oxide film, 3-trench sidewall oxide film, 4-plate electrode, 5-storage capacitor insulating film, 6
-Storage capacitor counter electrode, 7-Groove type gate forming insulating film, 8
-Sidewall insulating film of trench type gate forming insulating film, 9-Groove type channel region, 10-Gate oxide film, 11-Gate electrode, 1
2-gate electrode insulating film, 13-gate electrode sidewall insulating film, 14-pad electrode, 15-diffusion layer, 16-interlayer insulating film, 17-data line, 18-interlayer insulating film, 19-wiring,
21-trench hole, 22-organic film, 23-interlayer insulating film
30-active area of transistor, 31-trench, 32
-Plate electrode, 33-groove type gate forming pattern, 34
-Word electrode, 35-Pad electrode, 36-Data line contact, 37-Storage capacitor contact, 38-Storage capacitor,
101-Transmission transistor, 102-Driving transistor, 103-Grounding electrode, 104-Layered P-type transistor gate electrode, 105-Layered P-type transistor gate insulating film, 106-Layered P-type transistor channel conductivity Layer, 107-interlayer insulating film, 108-wiring, 1
09-circuit symbol of transmission transistor, 110-circuit symbol of driving transistor, 111-circuit symbol of laminated P-type transistor, 121-semiconductor region of first conductor, 12
2-Semiconductor region of the second conductor.

Claims (11)

[Claims] 1. A gate of a first conductivity type semiconductor substrate having an element isolation region, second conductivity type semiconductor regions formed at a certain interval, and being in contact with the semiconductor substrate via an insulating film. By applying a voltage to the electrodes, a current flowing between the semiconductor regions of the second conductivity type is controlled.
l Oxide Semiconductor) type semiconductor device, a part of an activation region which is a channel of the semiconductor device and which controls charge transfer is formed on a sidewall of a groove dug in a semiconductor substrate in which the semiconductor device is formed. The semiconductor device is characterized in that the distance from the bottom surface of the groove to the diffusion layer of the semiconductor device is longer than the planar dimension of the groove in the channel direction. 2. The semiconductor device according to claim 1, wherein a part of the second-conductivity-type semiconductor region is formed on the surface of the first-conductivity-type semiconductor substrate. 3. A complementary semiconductor device in which the semiconductor device according to claim 1 is formed in regions of different conductivity types on the same substrate. 4. A semiconductor memory device comprising a combination of a plurality of semiconductor devices according to claim 1, or a semiconductor memory device comprising a combination of the semiconductor device according to claim 1 and a charge storage capacitor. 5. An insulating film is present on the surface of the semiconductor substrate,
The trench is formed in the substrate through the opening of the insulating film and the sidewall insulating film formed in the opening in a self-aligned manner, and a part of the gate electrode of the semiconductor device includes the insulating film and the sidewall. The semiconductor device according to claim 1 or 2 and the semiconductor memory device according to claim 3, which are formed on an insulating film. 6. The gate electrode is a high melting point film typified by tungsten, and the gate insulating film is a high dielectric constant insulating film typified by tantalum pentoxide. A semiconductor device according to claims 1 and 2, and a semiconductor memory device according to claim 3. 7. The insulating film and the sidewall insulating film are silicon nitride films, claim 1;
The semiconductor device according to claim 2, and the semiconductor memory device according to claim 3. 8. A semiconductor device, wherein the dimension of the groove in the channel direction is determined by the dimension of the opening of the insulating film and the film thickness of the sidewall insulating film formed on the sidewall of the opening. Manufacturing method. 9. A sidewall insulating film of the gate electrode of the semiconductor device is used as a part of a mask to open a hole reaching the semiconductor substrate in the insulating film to expose an in-substrate diffusion layer region of the semiconductor device. A method for manufacturing a semiconductor device, comprising: 10. A semiconductor memory device comprising a combination of a semiconductor device and a charge storage capacitor, wherein as a mask pattern for forming the opening in the insulating film, in a region where the semiconductor memory device group is formed, A method of designing a mask pattern, wherein the pattern is an inverted pattern of the gate electrode. 11. A laminate comprising a first conductive film, a second insulating film, and a second conductive film, with a first insulating film formed on the surface of the semiconductor substrate interposed in the groove dug in the semiconductor substrate. A semiconductor memory device, wherein a film is present, and electrons or holes that have passed through the first insulating film are accumulated in an electrically insulated first conductive film.