JPH05166969A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05166969A JPH05166969A JP4010422A JP1042292A JPH05166969A JP H05166969 A JPH05166969 A JP H05166969A JP 4010422 A JP4010422 A JP 4010422A JP 1042292 A JP1042292 A JP 1042292A JP H05166969 A JPH05166969 A JP H05166969A
- Authority
- JP
- Japan
- Prior art keywords
- foil
- sides
- plate
- thickness
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H10W70/047—
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H10W40/255—
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】
【目的】実装した半導体素子からの放熱を良くするため
にCu張りAl2 O3 基板の厚さを薄くした場合に、Cu箔か
らAl2 O3 板に加わる応力により発生しやすくなる亀裂
を防止する。
【構成】両面のCu箔間の絶縁確保のためにCi箔の縁とAl
2 O3 板の端面との間に設けられる寸法の差をAl2 O3
板の厚さが0.26〜0.29mmのときに0.5mm以下の範囲に抑
えることにより、両面での応力の均衡をとらせて、亀裂
の発生を防止する。さらに、両面のCu箔に上下に重なり
合うパターンを持たせることにより応力の均衡が向上す
る。
(57) [Abstract] [Purpose] This is caused by the stress applied from the Cu foil to the Al 2 O 3 plate when the thickness of the Cu-clad Al 2 O 3 substrate is reduced to improve heat dissipation from the mounted semiconductor element. Prevent cracks that are easy to do. [Structure] To secure insulation between Cu foils on both sides, the edges of the Ci foil and Al
The difference in dimension provided between the end surface of the 2 O 3 plate and Al 2 O 3
When the thickness of the plate is 0.26 to 0.29 mm, the stress is balanced on both sides by suppressing the range to 0.5 mm or less to prevent the occurrence of cracks. In addition, stress balance is improved by providing Cu foils on both sides with a pattern that overlaps vertically.
Description
【0001】[0001]
【産業上の利用分野】本発明は、モータ制御、エアコン
等のインバータあるいはNC制御などに使用されるパワ
ーモジュールのように、表面に銅箔が張られたアルミナ
からなる絶縁基板上に半導体素子が実装される半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on an insulating substrate made of alumina having a copper foil on its surface, such as a power module used for motor control, inverters for air conditioners or NC control. The present invention relates to a mounted semiconductor device.
【0002】[0002]
【従来の技術】近年の電子機器の発達は著しく、高集積
化、小型軽量化が急激に進んでおり、その中核を担って
いるのは半導体装置である。その中で上記のような制御
用に用いられるパワーモジュールは、通常電力用半導体
素子のほかに付属回路の素子を含む複数の素子を一つの
容器内に収容して小型化を図っている。このようなパワ
ーモジュールでは、素子相互間あるいは素子との絶縁の
ために、両面にろう付け可能な金属箔を張った絶縁基板
を用いて素子を実装していた。以前は、このパワーモジ
ュールの絶縁基板の材料のセラミックとしては、アルミ
ナ (Al2 O3 ) を用いたものが主流であったが、新型素
子の小型化, 高機能化にともない、熱伝導率がさらに高
い窒化アルミニウム (AlN) 基板などが使用されるよう
になった。2. Description of the Related Art Electronic devices have been remarkably developed in recent years, and high integration, small size, and light weight have been rapidly advanced, and semiconductor devices play a central role in these. Among them, the power module used for control as described above is usually miniaturized by accommodating a plurality of elements including an element of an auxiliary circuit in a single container in addition to a power semiconductor element. In such a power module, in order to insulate elements from each other or between elements, the elements are mounted using an insulating substrate having brazable metal foils on both sides. Previously, alumina (Al 2 O 3 ) was mainly used as the ceramic for the insulating substrate of this power module, but with the miniaturization and high functionality of new elements, the thermal conductivity has increased. Higher aluminum nitride (AlN) substrates have come into use.
【0003】[0003]
【発明が解決しようとする課題】AlNの熱伝導率は80〜
140 W/(m・k) で、Al2 O3 の17W/(m・k) の約5
倍であり、基板を通じての放熱の大幅な改善が期待でき
るが、価格が高いために特殊用途に限定されている。そ
こで、安価なAl2 O3 基板の厚さを薄くして熱伝導を良
好にすることが考えられるが、薄くすることにより応力
耐性が低下する。すなわち、従来用いられていた0.635m
m の厚さのAl2 O3 基板の抗折強度は8kgであるのに対
し、0.275mmに薄くすると抗折強度が2kgとなり、75%
も低下する。従って組立時の熱履歴で亀裂が発生するお
それがある。[Problems to be Solved by the Invention] The thermal conductivity of AlN is 80-
140 W / (m ・ k), about 5 times that of Al 2 O 3 17 W / (m ・ k)
Although it can be expected that the heat dissipation through the substrate will be greatly improved, it is limited to special applications due to the high price. Therefore, it is conceivable to reduce the thickness of the inexpensive Al 2 O 3 substrate to improve the heat conduction, but reducing the thickness lowers the stress resistance. That is, 0.635m which was used conventionally
The bending strength of an Al 2 O 3 substrate with a thickness of m is 8 kg, whereas when it is thinned to 0.275 mm, the bending strength becomes 2 kg, which is 75%.
Also drops. Therefore, cracks may occur due to heat history during assembly.
【0004】本発明の目的は、安価なAl2 O3 を材料と
し、厚さを薄くすることによって熱伝導を良くした絶縁
基板を用い、しかも組立熱履歴で亀裂の発生することの
ない半導体装置を提供するものとする。It is an object of the present invention to use an insulating substrate made of inexpensive Al 2 O 3 as a material and having good heat conduction by reducing the thickness thereof, and moreover, a semiconductor device which is free from cracks during the assembly heat history. Shall be provided.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、Al2 O3 からなる平板の両面にCu箔が
張られた絶縁基板の一面上に半導体素子が実装される半
導体装置において、両面のCu箔の縁とAl2 O3 板の端面
とのそれぞれの寸法の差の絶対値が0.5mm 以下であるも
のとする。さらに、両面のCu箔が基板面に垂直方向から
見て上下に重なるようなパターンを有することが有効で
ある。また、Al2 O3 板の厚さが0.26〜0.29mmであるこ
とが有効である。In order to achieve the above-mentioned object, the present invention mounts a semiconductor element on one surface of an insulating substrate having a Cu foil stretched on both surfaces of a flat plate made of Al 2 O 3. In the semiconductor device, the absolute value of the dimensional difference between the edges of the Cu foil on both sides and the end faces of the Al 2 O 3 plate is 0.5 mm or less. Further, it is effective to have a pattern in which the Cu foils on both sides are vertically overlapped with each other when viewed from the direction perpendicular to the substrate surface. Further, it is effective that the thickness of the Al 2 O 3 plate is 0.26 to 0.29 mm.
【0006】[0006]
【作用】絶縁基板の両面のCu箔をAl2 O3 板の端面まで
張ると、沿面距離がAl2 O3 板の厚みのみとなり、絶縁
耐圧が得られないので、端面までは張っていない。すな
わち図2に示すように、Al2 O3 板1の両面で端面から
それぞれ寸法A、Bだけ引下がってた位置までCu箔2、
3が張られている。組立熱履歴で亀裂の発生する個所を
調べて見ると、AとBの寸法の大きい方、すなわちAl2
O3 板1の端面からの引下がりが大きい方のCu箔の縁の
下のAl2 O3 板に亀裂が発生することがわかった。これ
は、両面のCu箔の引下がりが異なると、温度変化時にセ
ラミックに働く応力が異なり、引下がりの大きい方のCu
箔の縁に応力が集中するためと考えられる。組立熱履歴
での冷却時にAl2 O3 板の両面に発生するセラミックへ
の引張り応力を有限要素法を用いて計算した場合、技術
計算値によるある物理定数での応力値のA−B値に対す
る依存性を図3に示す。計算の根拠として、Al2 O3板
1の厚さを0.27mm、Cu箔2、3の厚さをそれぞれ0.25mm
とした。図の冷却時に実線31がCu箔2のAl2 O3 板1に
及ぼす引張り応力であり、点線32がCu箔3のAl 2 O3 板
1に及ぼす引張り応力である。引張り応力はCu箔の縁が
Al2 O3 板1の端面から遠ざかるにつれて大きくなる。
すなわち、線31に示すようにCu箔2のAl 2 O3 板1に及
ぼす引張り応力はA−Bの値が正に大きくなったときに
大きくなり、負に大きくなったときに小さくなる。逆
に、線32に示すようにCu箔3のAl2O3 板1に及ぼす引
張り応力は控え寸法A−Bが正に大きくなったときに小
さくなり、負に大きくなったときに大きくなる。この両
者から控え寸法A−Bの絶対値にAl2 O3 板が割れない
ための適正範囲がでてくる。さらに一歩進めてA−B=
0にすると共に、Cu箔のパターンを絶縁基板面に垂直方
向から見て上下に重なるようにすれば、組立時に両面の
Cu箔がAl2 O3 板に及ぼす応力は釣合うことになり、亀
裂の発生するおそれがなくなる。[Operation] Cu foil on both sides of the insulating substrate is Al2O3Up to the edge of the board
When stretched, the creepage distance is Al2O3Insulation only with the thickness of the plate
Since the pressure resistance cannot be obtained, the end face is not stretched. sand
That is, as shown in FIG.2O3From both sides of board 1 from the edge
Cu foil 2 to the position where only the dimensions A and B were pulled down,
3 is stretched. Identify where cracks occur in the assembly heat history
Looking up, the larger of A and B, namely Al2
O3The edge of the Cu foil that has the largest pull-down from the edge of plate 1
Lower Al2O3It was found that the plate cracked. this
If the pulling down of the Cu foil on both sides is different, the
Cu with different pulling force and larger pull down
It is considered that the stress is concentrated on the edge of the foil. Assembly heat history
Al when cooled in2O3To ceramic generated on both sides of the plate
If the tensile stress of the
For the A-B value of the stress value with a certain physical constant calculated
Figure 3 shows the dependence of As the basis of calculation, Al2O3Board
The thickness of 1 is 0.27mm, the thickness of Cu foils 2 and 3 is 0.25mm respectively.
And When cooling the figure, the solid line 31 is the Al of the Cu foil 2.2O3On board 1
The tensile stress exerted, the dotted line 32 being the Al of the Cu foil 3. 2O3Board
The tensile stress exerted on 1. The tensile stress is
Al2O3The distance increases from the end face of the plate 1.
That is, as shown by the line 31, the Al of the Cu foil 2 2O3To board 1
Boss tensile stress is when the value of AB becomes positively large.
It becomes large and becomes small when it becomes negative. Reverse
And the Al of the Cu foil 3 as shown by the line 322O3Pull on plate 1
Tensile stress is small when the dimension AB is positively increased.
It becomes small and becomes large when it becomes negatively large. Both of these
To the absolute value of size AB2O3The board does not break
There will be an appropriate range for Take it a step further, AB =
Set to 0 and make the Cu foil pattern perpendicular to the insulating substrate surface.
If you make it overlap vertically when viewed from the direction,
Cu foil is Al2O3The stress on the plate will be balanced and the turtle
There is no risk of cracking.
【0007】[0007]
【実施例】0.275mm の厚さのAl2 O3 板1上に厚さ0.25
mmのCu箔2、3を張ったセラミック絶縁基板を用いてパ
ワーモジュールの組立てを行った。Cu箔2、3の張り方
を種々変えて控え寸法R=|A−B|を変化させたとこ
ろ、組立熱履歴でAl2 O3板に亀裂の発生するものがあ
った。図1はその亀裂発生率とRとの関係を示す。図よ
り明らかなように控え寸法Rが0.5 以下のときには亀裂
が発生せず、0.5 を超えると急激に亀裂の発生が多くな
る。この結果を参照してR≦0.5に設定して絶縁基板を
準備したところ、組立時の不良の発生なしにパワーモジ
ュールを製作することができた。Example: A thickness of 0.25 is formed on an Al 2 O 3 plate 1 having a thickness of 0.275 mm.
A power module was assembled using a ceramic insulating substrate having Cu foils 2 and 3 of mm. When the restraint dimension R = | AB | was changed by changing the tensioning of the Cu foils 2 and 3, various cracks occurred in the Al 2 O 3 plate due to the heat history of assembly. FIG. 1 shows the relationship between the crack generation rate and R. As is clear from the figure, cracks do not occur when the dimension R is 0.5 or less, and cracks rapidly increase when the dimension R exceeds 0.5. When the insulating substrate was prepared by setting R ≦ 0.5 with reference to this result, the power module could be manufactured without causing defects during assembly.
【0008】図4は本発明の別の実施例を示し絶縁基板
の上下両面の平面図でAl2 O3 板1の上のCu箔2、3の
パターンが線対称の形状をもち、基板面に垂直の方向か
ら見て重なるようになっている。従来は素子を実装する
側のCu箔2はパターニングされているが、放熱体として
のCu基板とはんだ付けされる側のCu箔3はパターニング
されていなかったのに対し、このように両面をパターニ
ングされることにより、組立時の熱履歴の際に生ずる応
力が均衡する。なお、Cu箔3はその下のはんだ層と共に
素子からの熱の放熱基板への径路になるが、Cu箔2の上
に実装される素子の直下には必ずCu箔3が存在するの
で、放熱に対する影響はない。FIG. 4 is a plan view of the upper and lower surfaces of an insulating substrate according to another embodiment of the present invention, in which the patterns of the Cu foils 2 and 3 on the Al 2 O 3 plate 1 have a line-symmetrical shape and the substrate surface It is designed to overlap when viewed from the direction perpendicular to. Conventionally, the Cu foil 2 on the side on which the element is mounted is patterned, but the Cu foil 3 on the side to be soldered to the Cu substrate as the heat radiator is not patterned. By doing so, the stress generated during the thermal history during assembly is balanced. The Cu foil 3 serves as a path for heat radiation from the device to the heat dissipation board together with the solder layer below, but since the Cu foil 3 is always present immediately below the device mounted on the Cu foil 2, heat dissipation is ensured. Has no effect on.
【0009】[0009]
【発明の効果】本発明によれば、半導体素子を実装する
絶縁基板を薄くして放熱を良好にし、安価にする場合
に、両面に張られたCu箔の縁とAl2 O3 板の半導体素子
面との間の距離の差の絶対値を0.5mm以下とすることに
より、両面でのCu箔のAl2 O3 板に及ぼす応力の均衡が
とれることから、Al2 O3板の破損が少なくなる。これ
によって、高集積化、小型化が可能になる。さらに、絶
縁基板両面のCu箔に上下に重なり合うパターンを持たせ
ることにより、一層の応力の均衡を図ることができる。According to the present invention, when the thickness of the insulating substrate on which the semiconductor element is mounted is reduced to improve the heat dissipation and reduce the cost, the edge of the Cu foil stretched on both sides and the semiconductor of the Al 2 O 3 plate are used. By setting the absolute value of the distance difference from the element surface to 0.5 mm or less, the stress exerted on the Al 2 O 3 plate of the Cu foil on both sides can be balanced, resulting in damage to the Al 2 O 3 plate. Is less. This enables high integration and miniaturization. Further, by providing the Cu foils on both sides of the insulating substrate with a pattern that vertically overlaps each other, it is possible to further balance the stress.
【図1】本発明の効果を示す控え寸法の絶対値と亀裂発
生率の関係線図FIG. 1 is a diagram showing the relationship between the absolute value of a spare dimension and the crack occurrence rate showing the effect of the present invention.
【図2】本発明の実施される絶縁基板の端部断面図FIG. 2 is a sectional view of an end portion of an insulating substrate according to the present invention.
【図3】絶縁基板の両面における応力計算値と控え寸法
との関係線図FIG. 3 is a diagram showing the relationship between the stress calculation values on both sides of the insulating substrate and the spare dimensions.
【図4】本発明の別の実施例における両面のCu箔パター
ンを(a)、(b) に示す平面図FIG. 4 is a plan view showing Cu foil patterns on both sides in another embodiment of the present invention, as shown in (a) and (b).
1 Al2 O3 板 2 Cu箔 3 Cu箔1 Al 2 O 3 plate 2 Cu foil 3 Cu foil
Claims (3)
れた絶縁基板の一面上に半導体素子が実装されるものに
おいて、両面の銅箔の縁とアルミナ板の端面とのそれぞ
れの寸法の差の絶対値が0.5mm以下であることを特徴と
する半導体装置。1. A semiconductor element is mounted on one surface of an insulating substrate having a copper foil stretched on both sides of a flat plate made of alumina, wherein the dimensions of the edges of the copper foil on both sides and the end surface of the alumina plate are different. A semiconductor device characterized in that the absolute value of the difference is 0.5 mm or less.
下に重なるようなパターンを有する請求項1記載の半導
体装置。2. The semiconductor device according to claim 1, wherein the copper foils on both sides have a pattern in which they are vertically overlapped with each other when viewed in a direction perpendicular to the substrate surface.
求項1あるいは2記載の半導体装置。3. The semiconductor device according to claim 1, wherein the thickness of the alumina plate is 0.26 to 0.29 mm.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4010422A JPH05166969A (en) | 1991-10-14 | 1992-01-24 | Semiconductor device |
| GB9220725A GB2260650B (en) | 1991-10-14 | 1992-10-01 | Insulating substrate for mounting semiconductor devices |
| DE4234506A DE4234506A1 (en) | 1991-10-14 | 1992-10-13 | INSULATING SUBSTRATE FOR FASTENING SEMICONDUCTOR COMPONENTS |
| US08/168,407 US5403651A (en) | 1991-10-14 | 1993-12-17 | Insulating substrate for mounting semiconductor devices |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3-264174 | 1991-10-14 | ||
| JP26417491 | 1991-10-14 | ||
| JP4010422A JPH05166969A (en) | 1991-10-14 | 1992-01-24 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11651999A Division JP3199058B2 (en) | 1991-10-14 | 1999-04-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05166969A true JPH05166969A (en) | 1993-07-02 |
Family
ID=26345679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4010422A Pending JPH05166969A (en) | 1991-10-14 | 1992-01-24 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH05166969A (en) |
| DE (1) | DE4234506A1 (en) |
| GB (1) | GB2260650B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002084046A (en) * | 2000-09-07 | 2002-03-22 | Toshiba Corp | Ceramic circuit board |
| JP2015035501A (en) * | 2013-08-09 | 2015-02-19 | 日本特殊陶業株式会社 | Heat dissipation module and semiconductor module |
| JP2017069275A (en) * | 2015-09-28 | 2017-04-06 | 三菱マテリアル株式会社 | Substrate for power module with radiator plate, and power module |
| JP2017092393A (en) * | 2015-11-16 | 2017-05-25 | 住友電工デバイス・イノベーション株式会社 | Electronic equipment |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2287131A (en) * | 1994-02-24 | 1995-09-06 | Plessey Semiconductors Ltd | Direct copper bonded substrates |
| JP3316714B2 (en) * | 1994-05-31 | 2002-08-19 | 三菱電機株式会社 | Semiconductor device |
| DE4421319A1 (en) * | 1994-06-17 | 1995-12-21 | Abb Management Ag | Low-inductance power semiconductor module |
| JP3127754B2 (en) * | 1995-01-19 | 2001-01-29 | 富士電機株式会社 | Semiconductor device |
| RU2190284C2 (en) | 1998-07-07 | 2002-09-27 | Закрытое акционерное общество "Техно-ТМ" | Two-sided electronic device |
| US7075103B2 (en) | 2003-12-19 | 2006-07-11 | General Electric Company | Multilayer device and method of making |
| JP4867793B2 (en) * | 2007-05-25 | 2012-02-01 | 株式会社豊田自動織機 | Semiconductor device |
| EP2315284A3 (en) * | 2009-10-21 | 2013-03-27 | Toshiba Lighting & Technology Corporation | Light-Emitting apparatus and luminaire |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB817635A (en) * | 1956-05-04 | 1959-08-06 | Tony Brian Harding | Improvements in or relating to printed circuit assemblies |
| US3994430A (en) * | 1975-07-30 | 1976-11-30 | General Electric Company | Direct bonding of metals to ceramics and metals |
| DE8219553U1 (en) * | 1982-07-08 | 1982-10-07 | Brown, Boveri & Cie Ag, 6800 Mannheim | SEMICONDUCTOR MODULE |
| JPS59150453A (en) * | 1982-12-23 | 1984-08-28 | Toshiba Corp | Manufacture of substrate for seiconductor module |
| SU1601788A1 (en) * | 1986-01-27 | 1990-10-23 | Предприятие П/Я В-2749 | Electronic module |
| DE3604882A1 (en) * | 1986-02-15 | 1987-08-20 | Bbc Brown Boveri & Cie | PERFORMANCE SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE MODULE |
| JPS62205615A (en) * | 1986-03-05 | 1987-09-10 | 株式会社村田製作所 | Metallization of ceramics |
| DE3610288A1 (en) * | 1986-03-26 | 1987-10-01 | Bbc Brown Boveri & Cie | PERFORMANCE SEMICONDUCTOR MODULE |
| GB2201123B (en) * | 1987-02-19 | 1990-11-14 | Marconi Electronic Devices | Electrical conductor arrangement |
| IT1202657B (en) * | 1987-03-09 | 1989-02-09 | Sgs Microelettronica Spa | MANUFACTURING PROCEDURE OF A SEMICONDUCTOR MODULAR POWER DEVICE AND DEVICE WITH IT OBTAINED |
| DE3728096C1 (en) * | 1987-07-03 | 1989-01-12 | Duerrwaechter E Dr Doduco | Flat body, especially for use as a heat sink for electronic power components |
| JPH01120886A (en) * | 1987-11-04 | 1989-05-12 | Mitsubishi Electric Corp | Ceramic substrate |
| JPH01272183A (en) * | 1988-04-25 | 1989-10-31 | Toshiba Corp | Ceramics circuit board |
| DE8808767U1 (en) * | 1988-07-08 | 1989-11-02 | Akyürek, Altan, Dipl.-Ing., Wien | Electrical module component |
| DE3924225C2 (en) * | 1988-07-22 | 1994-01-27 | Mitsubishi Electric Corp | Method for producing a ceramic-metal composite substrate and ceramic-metal composite substrate |
| JPH0272695A (en) * | 1988-09-07 | 1990-03-12 | Toshiba Lighting & Technol Corp | Hybrid integrated circuit |
| DE3930859C2 (en) * | 1988-09-20 | 1997-04-30 | Schulz Harder Juergen | Process for soldering at least two elements |
| DE3837618A1 (en) * | 1988-11-05 | 1990-05-10 | Semikron Elektronik Gmbh | Electrical or electronic arrangement |
| DE3922485C1 (en) * | 1989-07-08 | 1990-06-13 | Doduco Gmbh + Co Dr. Eugen Duerrwaechter, 7530 Pforzheim, De | |
| DE3931551C2 (en) * | 1989-09-22 | 1993-11-18 | Schulz Harder Juergen | Method of making a substrate |
| DE4004844C1 (en) * | 1990-02-16 | 1991-01-03 | Abb Ixys Semiconductor Gmbh | Copper metallisation on ceramic substrate - obtd. by bonding copper foil directly to whole surface of substrate, then masking and etching |
| DE4210900A1 (en) * | 1992-04-02 | 1993-10-14 | Hoechst Ag | Process for producing an adhesive bond between copper layers and ceramic |
-
1992
- 1992-01-24 JP JP4010422A patent/JPH05166969A/en active Pending
- 1992-10-01 GB GB9220725A patent/GB2260650B/en not_active Expired - Lifetime
- 1992-10-13 DE DE4234506A patent/DE4234506A1/en not_active Ceased
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002084046A (en) * | 2000-09-07 | 2002-03-22 | Toshiba Corp | Ceramic circuit board |
| JP2015035501A (en) * | 2013-08-09 | 2015-02-19 | 日本特殊陶業株式会社 | Heat dissipation module and semiconductor module |
| JP2017069275A (en) * | 2015-09-28 | 2017-04-06 | 三菱マテリアル株式会社 | Substrate for power module with radiator plate, and power module |
| JP2017092393A (en) * | 2015-11-16 | 2017-05-25 | 住友電工デバイス・イノベーション株式会社 | Electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2260650A (en) | 1993-04-21 |
| GB2260650B (en) | 1995-03-22 |
| DE4234506A1 (en) | 1993-04-15 |
| GB9220725D0 (en) | 1992-11-11 |
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