JPH05166940A - Formation of contact hole of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a base conductive film for the shallow contact hole of contact holes form being overshaved in a method of manufacturing the contact holes of a semiconductor device having the contact holes, which are different from each other in depth and are simultaneously opened. CONSTITUTION:A shallow contact hole 36 is formed, a protrusion 32a is formed on the part of a polysilicon film 32, which is used as a base conductive film by which a contact is made, and the etching rates of a deep contact hole 35 and the hole 36 are made to differ from each other to prevent the film 32, which is used as the base conductive film for the hole 36, from being etched more than it is needed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming contact hole openings having different depths in the manufacturing process.

[0002]

2. Description of the Related Art In semiconductor devices, especially VLSI typified by DRAM, the reduction ratio in the film thickness direction is smaller than the reduction ratio in the lateral direction for each generation. There is a tendency. Further, since the cell structure also has a three-dimensional structure such as a stacked type in order to increase the capacity, the thickness of the interlayer insulating film also varies. Under these circumstances,
The deepest contact hole and the shallowest contact hole may have a depth difference of 3 to 4 times. When these holes are simultaneously opened, in the deeper contact hole, while the bottom of the hole reaches the substrate, Underlying gate film with shallow contact holes [polysilicon (n ⁺ polycrystalline Si) film, tungsten silicide (WSix)]
The film] has already been over-etched by 400 to 500%, and the interlayer insulating film is required to have a high selection ratio with respect to the gate film.

In order to perform etching with such a high selection ratio, etching is performed by changing the gas composition, devising the pressure and power. Here, FIG. 4 briefly shows a conventional method for forming a part of a cell plate and a bit line. The processing flow is as follows. (1) As shown in FIG. 4A, a polysilicon film 2 is deposited on the silicon oxide type interlayer insulating film 1 by the LPCVD method (low pressure chemical vapor deposition method) by about 1500 Å.

(2) As shown in FIG. 4 (b), in order to reduce the resistance, POCl _{3 is} added at a concentration of 6 × 10 ²⁰ ions / c.
Phosphorus is diffused into the polysilicon film 2 using m ³ . (3) As shown in FIG. 4C, an O ₃ -TEOSBP process is performed through an etching process (not shown) for the polysilicon film 2.
SG film 3 (TEOS: tetra-etoxy-ort
ho-silicate, BPSG: boron-ph
ossosilicate glass, B ₂ O ₃ /
P ₂ O ₅ = 13/14% by weight) is deposited by the CVD method.

(4) As shown in FIG. 4D, a photoresist 4 is applied, exposed and developed to pattern holes. (5) As shown in FIG. 4 (e), the holes 5 are opened by normal dry etching, and the resist 4 [FIG.
Reference] is removed. By this etching process, bit contacts are formed in the memory cells.

As described above, the cell plate and the contact hole at the end of the memory cell are formed. Subsequently, a method of forming the bit lines in the array section will be described below. (6) Also in the array portion, as shown in FIG. 5A, holes are opened in the silicon oxide type interlayer insulating film 7 on the Si substrate 6.

(7) Next, as shown in FIG.
A polysilicon film 8 of about 1500 Å is deposited by the PCVD method. (8) As shown in FIG. 5C, the acceleration voltage is 60, for example.
An n ⁺ polysilicon film 9 is formed by ion-implanting phosphorus with KeV at a concentration of 4.0 × 10 ¹⁵ ions / cm ² .

(9) As shown in FIG. 5 (d), the first
A second layer WSi _x 10 is deposited on the layer n ⁺ polysilicon film 9 to form a polycide 11. (10) As shown in FIG. 5 (e), O ₃ -TE thereon
The OSBPSG film 12 is deposited. Then, the polysilicon side film is etched to form a contact hole 13 for connecting the n ⁺ polysilicon film 9 of the first layer and the bit line.

[0009]

However, in order to increase the selection ratio of the silicon oxide-based interlayer insulating film to the underlying film, plasma generation conditions such as high pressure and high (CHF ₃ / CF ₄ ) ratio are set as follows. Extremely cool the lower electrode temperature,
When etching is performed, the etching rate of the silicon oxide-based interlayer insulating film is reduced, the tip of the hole is tapered, the bottom area is reduced, and the side wall of the hole becomes bowed. These lead to an increase in contact resistance and deterioration in step coverage, which deteriorates the reliability of wiring. Even if the selection ratio is barely obtained without breaking the shape of the hole, the abrasion amount of the base film is 500Å to 150.
There is a problem that it reaches 0 Å, penetrates a conductive film such as WSix or n ⁺ poly Si, or reduces a removal margin of a damaged layer, thereby impairing reliability of wiring.

According to the present invention, when the above problems are eliminated and holes with different depths are simultaneously opened, if a high selection ratio of the shallower hole to the underlying conductive film is to be obtained, the processed shape of the hole is reduced. Eliminates the problem that the conductive film penetrates and the damage removal margin layer is reduced due to the variation in the film thickness even if the selection ratio gets worse or the selection ratio is barely obtained, and the reliability of the device wiring is impaired. Therefore, in a method of manufacturing a contact hole of a semiconductor device in which contact holes having different depths are simultaneously opened, a base conductive film at the bottom of a shallow contact hole is unnecessarily used under the condition that a deep contact hole is opened with high processing accuracy. An object of the present invention is to provide a method for forming a contact hole of a semiconductor device that can be etched without being cut.

[0011]

In order to achieve the above object, the present invention provides a method for forming a contact hole of a semiconductor device in which contact holes having different depths are simultaneously opened, and a shallow contact hole is contacted. Protrusions are formed on the underlying conductive film to reduce the etching rate of the shallow contact hole as compared with the etching rate of the deep contact hole so that the underlying conductive film of the shallow contact hole is not etched more than necessary. It is a thing.

Here, the protrusion of the underlying conductive film projects upward or downward, and the width of the protrusion of the underlying conductive film is made larger than the diameter of the contact hole for making contact therewith. Further, as the underlying conductive film, a first conductive film and a second conductive film having a low etching rate, such as WSi _x , formed thereon are formed. Further, the protrusions of the underlying conductive film are formed by leaving the second conductive film on the first conductive film, or the impurity concentration of the protrusions of the underlying conductive film is changed to that of the surrounding conductive film supporting the protrusions. Lower than the impurity concentration.

Further, a silicon oxide type interlayer insulating film is formed in which the film thickness above the protrusions of the underlying conductive film is increased. For example, the BPSG film is formed by the CVD method.

[0014]

According to the present invention, in a method of forming a contact hole of a semiconductor device in which contact holes having different depths are simultaneously opened, a protrusion is formed in an underlying conductive film in which a shallower contact hole is opened to form an underlying conductive film. The film thickness of the film itself or the film thickness of the interlayer insulating film on the film is increased, or another conductive film having a slower etching rate is formed only in the portion where the contact hole is opened. Further, a silicon oxide-based interlayer insulating film is formed in which the film thickness above the protrusions of the underlying conductive film is increased. For example, since the BPSG film is formed by the CVD method, it is possible to increase the margin of the abrasion amount of the underlying conductive film.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a contact hole formation state of a semiconductor device to which the present invention is applied.
Here, a hole (bit contact) connecting the Si substrate in the memory cell to the bit line and a hole connecting the cell plate (n ⁺ poly Si) at the end of the memory cell are simultaneously opened.

A method of forming a base conductive film in which a shallower hole is depressed among holes having different depths as described above will be described. (A) A first embodiment of the present invention will be described with reference to FIGS. (1) First, as shown in FIG. 2A, a polysilicon film 22 is deposited on the silicon oxide-based interlayer insulating film 21 by LPCVD (low pressure chemical vapor deposition) by about 1500 Å.

(2) Next, as shown in FIG.
A photoresist 23 is applied, and by a normal lithographic process, it is about 0.2 .mu.m wider than the planned hole system.
A 9 × 0.9 μm square resist pattern 24 is formed. (3) Next, as shown in FIG. 2C, according to the mask pattern, only the polysilicon film 22 is subjected to, for example, EC.
Using an etching apparatus using the R discharge method, high frequency power is 90 W, pressure is 0.17 Torr, gas SF ₆ /
F115 / He is etched under plasma generation conditions of 20/20/5 SCCM.

(4) Subsequently, as shown in FIG.
Using the same mask, the silicon oxide-based interlayer insulating film 21 thereunder is pressed with a pressure of 1.0 Torr and a high frequency power of 900 by using, for example, a parallel plate type discharge type etching apparatus.
W, gas Ar / CHF ₃ / CF ₄ = 800/80/80
About 1500 Å etching is performed under SCCM plasma generation conditions.

(5) After removing the resist, FIG.
As shown in FIG. 3, a polysilicon film 25 is further deposited by LPCVD method at about 3500 Å. Here, the protrusion 25a is formed below. (6) Using the same conditions as in (3) above, the polysilicon film 25 is entirely etched back by about 3500 Å as shown in FIG. 3 (c). Then, only the protrusion 25a remains.

(7) Next, as shown in FIG.
To reduce the resistance, for example, the POCl ₃ concentration is 12 × 1.
Impurities such as phosphorus are diffused into the polysilicon film 22 by using 0 ²⁰ ions / cm ³ . As described above, as in (1) to (7), the conductive film provided with the base film of the protrusion 25a is formed under the contact opening portion, and the hole in the process as shown in FIG. 1 is a low-pressure process capable of processing a hole (bit contact) having a high aspect ratio in a vertical shape as shown on the left side of FIG. 1 (for example, 0.7 Torr, 800 W,
Ar / CHF ₃ / CF ₄ = 800/80 / 80SCCM
Etching under the plasma generation condition of
Under this condition, as shown in FIG. 4, since the selection ratio of holes in the silicon oxide-based interlayer insulating film 3 to the polysilicon film 2 is only about 2 to 3, therefore, FIG.
As shown in FIGS. 6A and 6B, the polysilicon film 2 was entirely scraped or penetrated.] Here, a contact should be opened in the polysilicon film 25. Therefore, even under the above vertical machining conditions,
As shown in (e), a resist 27 is formed on the interlayer insulating film 26.
Is applied to form a contact hole 28. Then, the protrusion 25a has a thickness of about 1000 Å, the polysilicon film 25
b can be left.

In FIG. 1, for example, S ₁ is 1.
4 μm, S ₂ is 0.7 μm, and S ₃ is 0.6 μm. (B) Next, a second embodiment of the present invention will be described with reference to FIG. (1) First, as shown in FIG. 7A, a polysilicon film 32 is deposited on the silicon oxide-based interlayer insulating film 31 by LPCVD (low pressure chemical vapor deposition) by about 3000 liters.

(2) Next, as shown in FIG.
To reduce the resistance, for example, the POCl ₃ concentration is 12 × 1.
An impurity such as phosphorus is diffused into the polysilicon film 32 by using 0 ions ²⁰ / cm ³ . (3) Next, as shown in FIG. 7C, a photoresist is applied and a resist pattern 33 is formed by photolithography.

(4) Next, as shown in FIG. 7D, the polysilicon film 3 is formed using the resist pattern 33 as a mask.
Etch 2 1500 Å thick. (5) The resist pattern 33 is removed, and as shown in FIG. 7E, the protrusion 32 having a height of 1500Å and a 0.9 × 0.9 μm square is formed in the contact hole formation portion of the polysilicon film 32.
a is formed.

Here, when the projection is used as described above, there are the following merits. (1) Since the film is thickly formed above the n ⁺ poly-Si projection at the end of the memory cell, the film thickness on the left side of FIG. 1, that is, the memory cell side becomes thin, and the bit contact that is the deeper hole is About 1000-2000 Å Shallow. As a result, the difference in depth between the two holes is reduced, and the scraping amount of n ⁺ poly-Si can be further reduced by 500 to 700Å.

(2) Although omitted in FIG. 1, the array portion and the peripheral circuit portion are present on the right side of the memory cell. Since the array section and the peripheral circuit section have no capacitors for accumulating charges and the density of wirings such as word lines is sparse, the film thickness thereof is smaller than that of the memory cell section before forming the wiring layer in FIG. It is about 2000Å lower, and after forming the bit line and about 6000Å silicon oxide-based interlayer insulating film, about 4000 to 5000Å lower. Therefore, if a protrusion is formed on the bit line on the portion where a hole used for connection to the memory falls, as in the case of the cell plate, not only the margin of the scraped amount of n ⁺ poly-Si increases but also the protrusion of the array portion The membrane lifts,
The step between the memory cell section and the array section is eliminated, and the formation of the upper metal wiring becomes easy. (C) Next, a third embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 8A, a silicon oxide type interlayer insulating film, for example, BPSG is formed thereon.
(Boron phosphosilicate gl
ass, B ₂ O ₃ / P ₂ O ₅ = 13/14% by weight) Membrane 3
4 was deposited by a CVD method at about 5000 Å and heat-flowed at 900 ° C., the film thickness on the protrusion becomes thicker than the flat portion due to the step of the base. Here, it is possible to form a film thickness d ₁ of 3000 Å and a film thickness d ₂ on the protrusion of 7000 Å in a flat portion. Therefore, the time required to reach the underlying conductive film at the time of etching can be delayed by the amount of this thickness, and when the etching is performed under the same conditions as in Example 1, the abrasion amount of the polysilicon film is further reduced by 300 to 500Å. can do. Furthermore, it is also possible to use conditions where the microloading effect does not occur at low pressure.

Next, as shown in FIG. 8B, the substrate 30
Simultaneously with the formation of the deep contact hole 35 in the above, a shallow contact hole 36 is formed so as to contact the protrusion 32a of the polysilicon film 32. Here, the depth d ₃ of the deep contact hole 35 is 1.2 μm to 1.3 μm.
m, the depth d ₄ of the shallow contact hole 36 is 0.7 μm
m. (D) Next, a fourth embodiment of the present invention will be described with reference to FIG.

As described above, as shown in FIG. 2 and FIG. 7, instead of forming the protrusions, when WSix having an area approximately the same as or slightly larger than the diameter of the contact hole is formed so as to open the hole, The etching rate of WSix is about 1/3 that of n ⁺ polysilicon when the etching is performed using the parallel plate discharge type etching apparatus and the processing conditions described above. it can.

(1) First, as shown in FIG. 9A, a polysilicon film 42 is formed on the silicon oxide type interlayer insulating film 41 by LPCVD (low pressure chemical vapor deposition) to a thickness of about 150.
Deposit 0Å. (2) Next, as shown in FIG. 9B, the WSix 43 is formed to 1000 Å. (3) Next, as shown in FIG. 9C, a resist is applied to form a resist pattern 44 having a width of 0.65 to 0.75 μm.
To form.

(4) Next, using the resist pattern 44 as a mask, the WSix 43 is etched, the resist pattern 44 is removed, and a projection-shaped WSix 43 is formed as shown in FIG. 9D. (E) Next, a fifth embodiment will be described with reference to FIG. In this embodiment, as in the second embodiment, a method of slowing the etching rate of the n ⁺ poly-Si protrusion without changing the material of the protrusion itself is shown.

(1) First, as shown in FIG.
About 15 polysilicon films 52 are formed on the silicon oxide-based interlayer insulating film 51 by LPCVD (low pressure chemical vapor deposition).
00Å Deposit. (2) Next, as shown in FIG. 10B, a resist is applied on the polysilicon film 52 to form a resist pattern 53 having a width of 0.7 μm.

(3) Next, as shown in FIG.
After etching the polysilicon film 52 using the resist pattern 53 as a mask, phosphorus ions are implanted. (4) Next, as shown in FIG. 10D, the resist pattern 44 is removed to form a polysilicon film 52 on which the protrusion 52a is formed. Then, the projection 52a is undoped in which phosphorus ions are not implanted, but phosphorus ions are implanted below it. That is, the impurities are ion-implanted except for the protrusion 52a. Therefore, the protrusion 52
Since the portion just under a is under the mask like the protrusion, the impurity is not directly injected, but due to thermal diffusion, the impurity enters from the left and right of the flat portion as shown by the arrow, and the protrusion 52a The impurities are almost uniformly injected except for the above. In this case, implantation of impurities (eg phosphorus)
The etching rate of the protrusion 52a of the polysilicon film 52 which is not formed is the impurity (n ⁺ poly-Si concentration 6 × 10 io).
ns ²⁰ / cm ³ ) is reduced to about 1/3 of the etching rate of the implanted polysilicon film 52, so that the same effect as when changing the material of the protrusion is obtained.

Further, as shown in FIG. 11, WSix63 is deposited on the polysilicon film 62 having the projections 62a to form a polycide film, and the projections 63a of the WSix63 are formed.
Alternatively, the shallow contact hole 65 and the deep contact hole 61 may be simultaneously formed in the Si substrate 60, each contact hole may be filled with tungsten 67 to make a contact, and the first layer metal 68 may be wired.
66 is a silicon oxide-based interlayer insulating film.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0035]

As described above in detail, according to the present invention, the following effects can be obtained. (1) Protrusions are provided on the underlying conductive film at the portions where shallow contact holes are opened. Further, the impurity concentration of the protruding portion is changed or another material is used.

Further, since the silicon oxide type interlayer insulating film in which the film thickness above the protrusions of the underlying conductive film becomes thick is formed, when the contact holes having different depths are simultaneously etched, the deep contact holes can be processed with high accuracy. In addition to etching, it is possible to prevent the underlying conductive film from penetrating, and it is possible to expand the margin of the damage removing step. In addition, the thickness of the interlayer insulating film where the protrusion is located can be increased.

(2) By making the width of the protrusion slightly larger than the size of the contact hole, the contact area between the conductive film and the contact hole is increased, and the contact resistance is stabilized. (3) Providing a protrusion on the cell plate at the end of the memory cell can substantially reduce the depth of the bit contact, which is the deeper bit contact hole.

(4) Providing the protrusions on the bit lines of the array section eliminates the step between the memory cell and the array section, and improves the reliability and yield of the laminated metal wiring.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a contact hole formation state of a semiconductor device to which the present invention is applied.

FIG. 2 is a sectional view (No. 1) of a step of forming a contact hole in a semiconductor device showing an embodiment of the present invention.

FIG. 3 is a sectional view (No. 2) of the step of forming the contact hole of the semiconductor device showing the embodiment of the present invention.

FIG. 4 is a sectional view (No. 1) of a step of forming a contact hole of a conventional semiconductor device.

FIG. 5 is a sectional view (No. 2) of the step of forming the contact hole of the conventional semiconductor device.

FIG. 6 is a diagram illustrating a problem of contact hole formation in a conventional semiconductor device.

FIG. 7 is a sectional view of a step of forming a contact hole in a semiconductor device showing a second embodiment of the present invention.

FIG. 8 is a sectional view of a step of forming a contact hole in a semiconductor device showing a third embodiment of the present invention.

FIG. 9 is a sectional view of a step of forming a contact hole in a semiconductor device showing a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a step of forming a contact hole in a semiconductor device showing a fifth embodiment of the present invention.

FIG. 11 is a sectional view showing a contact hole formation state of a semiconductor device showing a sixth embodiment of the present invention.

[Explanation of symbols]

21, 31, 41, 51, 65 Silicon oxide-based interlayer insulating film 22, 25, 25b, 32, 42, 52, 62 Polysilicon film 23 Photoresist 24, 33, 44, 53 Resist pattern 25a, 32a, 52a, 62a , 63a Protrusions 30, 60 Substrate 34 BPSG film 35, 61 Deep contact hole 36, 64 Shallow contact hole 43, 63 WSix film 66 Tungsten 67 First layer metal

Claims (9)

[Claims] 1. A method of forming a contact hole in a semiconductor device, wherein contact holes having different depths are simultaneously opened, wherein a protrusion is formed in a portion of a base conductive film which is brought into contact with a shallow contact hole, and a deep contact hole is etched. A method of forming a contact hole in a semiconductor device, comprising: etching the shallow contact hole at an etching rate slower than the etching speed to prevent the underlying conductive film of the shallow contact hole from being etched more than necessary. 2. The method of forming a contact hole in a semiconductor device according to claim 1, wherein the projection of the underlying conductive film is projected upward. 3. The method of forming a contact hole in a semiconductor device according to claim 1, wherein the projection of the underlying conductive film is projected downward. 4. The method of forming a contact hole in a semiconductor device according to claim 1, wherein the width of the protrusion of the underlying conductive film is larger than the diameter of the contact hole with which the contact is made. 5. The contact of the semiconductor device according to claim 1, wherein the underlying conductive film is composed of a first conductive film and a second conductive film formed thereon having a low etching rate. Method of forming holes. 6. The method of forming a contact hole in a semiconductor device according to claim 5, wherein the protrusion of the underlying conductive film is formed by leaving the second conductive film on the first conductive film. 7. The method of forming a contact hole in a semiconductor device according to claim 1, wherein the impurity concentration of the projection of the underlying conductive film is set lower than the impurity concentration of the conductive film surrounding the projection. 8. The method of forming a contact hole in a semiconductor device according to claim 1, wherein a silicon oxide-based interlayer insulating film is formed so that the film thickness above the protrusion of the underlying conductive film is increased. 9. The silicon oxide-based interlayer insulating film is made of BPS.
9. The method for forming a contact hole of a semiconductor device according to claim 8, wherein the G film is formed by a CVD method.