JPH0516691B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a BTL circuit (Balanced Transformer) used as an output circuit of a power amplifier, etc.
Less circuit).

[Conventional technology]

FIG. 6 is a circuit diagram showing an example of a conventional BTL circuit.

NPN transistors (hereinafter both NPN transistors and PNP transistors are simply referred to as transistors) Q ₁ , Q ₂ and transistors Q ₃ , Q ₄ are connected in series to form a push-pull circuit,
It is connected between the power supply terminal 5 and ground. The bases of the transistors Q ₁ and Q ₂ are driven by the input signal from the input terminal 1 via the drive circuit 6.
On the other hand, the bases of transistors Q ₃ and Q ₄ are connected to input terminal 2.
It is driven via the drive circuit 7 by a reverse phase input signal from the output terminals 3 and 4, respectively. In the figure, 8 is a load.

[Problem that the invention seeks to solve]

In the conventional BTL circuit shown in FIG. 6, when transistors Q ₁ and Q ₄ are in the operating state, when output terminal 3 is grounded, and when transistors Q ₃ and Q ₂
is in operation and output terminal 4 is grounded. In the former case, an overcurrent will flow to transistor Q ₁ , and in the latter case, an overcurrent will flow to transistor Q ₃ , destroying transistors Q ₁ and Q ₃ . There was a problem with this.

An object of the present invention is to solve this problem by providing a BTL circuit equipped with a protection circuit that prevents overcurrent from flowing through the transistor even if one of the output terminals is grounded. There is a particular thing.

[Means for solving problems]

The BTL circuit of the present invention includes a first push-pull circuit in which first and second transistors are connected in series and whose midpoint is configured as a first output terminal;
a second push-pull circuit in which fourth transistors are connected in series and whose middle point is configured as a second output terminal; in the BTL circuit including the first and second drive circuits, respectively.
first, second, third, and fourth detection circuits that detect the base-emitter voltages of the second, third, and fourth transistors; and an output of the first detection circuit and a first level shift circuit. A first comparison circuit that compares the output of the fourth detection circuit via the output of the third detection circuit and the output of the second detection circuit via the second level shift circuit. a second comparator circuit;
and a control circuit that controls the second drive circuit.

[Effect]

FIG. 1 is a block diagram showing the basic configuration of the BTL circuit of the present invention.

The BTL circuit of the present invention includes a first push-pull circuit in which first and second transistors Q ₁₁ and Q ₁₂ are connected in series and whose midpoint is configured as the first output terminal 13, and a third and fourth transistor A second push-pull circuit in which Q ₁₃ and Q ₁₄ are connected in series and whose midpoint is configured as the second output terminal 14, and transistors Q ₁₁ , Q ₁₂ and Q that are input to the first and second push-pull circuits. First and second drive circuits 16 and 1 drive the bases of _Q13 and _Q14 in opposite phases, respectively.
In the BTL circuit including 7 and 7, respectively, the first and
first, second, third and fourth detection circuits 19 to 22 for detecting the base-emitter voltages V _BE of the second, third and fourth transistors Q ₁₁ to _{Q 14} ;
A first comparison circuit 25 with a differential configuration compares the output of the detection circuit 19 and the output of the fourth detection circuit 22 via the first level shift circuit 23; 2 level shift circuit 2
A second comparison circuit 26 with a differential configuration compares the output of the second detection circuit 20 via the second detection circuit 20 via the second detection circuit 20, A control circuit 27 that controls the second drive circuits 16 and 17 is included. In FIG. 1, 11 and 12 are input terminals, 15 is a power supply terminal, and 18 is a load.

The conditions for the control circuit 27 to operate are that it operates when the output of the comparison circuit 25 or the comparison circuit 26 becomes high level, and the control circuit 27 operates when the output of the comparison circuit 25 or the comparison circuit 26 becomes high level;
By cutting off the transistor Q ₁₁ ~
Q ₁₄ is rejected. Further, the outputs of the detection circuits 19 to 22 output a high level when it is detected that there is a difference between the collector currents I _C1 to I _C4 of the transistors Q ₁₁ and Q ₁₄ or Q ₁₂ and Q ₁₃ .

Next, the basic operation of the circuit shown in FIG. 1 will be explained.

The output voltage of the detection circuit 19 is _V1 , the output voltage of the detection circuit 20 is _V2 , the output of the detection circuit 21 is _V3 , the output voltage of the detection circuit 22 is _V4 , the level shift circuit 23,
The level shift voltage of 24 is V _L , the voltage of the input terminals 101 and 102 of the comparison circuit 25 is V ₁₀₁ , V ₁₀₂ , and the voltage of the input terminals 201 and 202 of the comparison circuit 26 is
Let V ₂₀₁ and V ₂₀₂ .

The output of the detection circuit 20 is sent to the input terminal 201 of the comparison circuit 26, and the output of the detection circuit 22 is sent to the input terminal 101 of the comparison circuit 26.
V ₁₀₁ , V ₂₀₁ and V ₁₀₂ ,
V ₂₀₂ becomes V ₁₀₁ (V ₂₀₁ )=V ₄ (V ₂ )−V _L ……(1) V ₁₀₂ (V ₂₀₂ )=V ₁ (V ₃ ) ……(2). If the collector currents of transistors Q ₁₁ to _{Q 14} are respectively I _C1 , I _C2 , I _C3 , and I _C4 , then during normal operation, the collector currents I _C1 and I _C4 or I _C2 and I _C3 are equal, and V ₄ ( If V ₂ )=V ₁ (V ₃ ), then equation (1) and
From the relationship in equation (2), the following relationship holds true: V ₁₀₁ (V ₂₀₁ )<V ₁₀₂ (V ₂₀₂ )...(3). Comparison circuit 25 and comparison circuit 2
6 is at a low level in the state of equation (3), and therefore the control circuit 27 is also in an off state.

Next, when there is a difference between the collector currents I _C1 and I _C4 or I _C2 and I _C3 and there is an abnormality where I _C1 > I _C4 or I _C3 > I _C2 , the output voltage of the detection circuit 19 or the detection circuit 21 is V ₁ or V ₃ becomes V ₁ (V ₃ )<V ₄ (V ₂ )−V _L ……(4), then the following relationship holds: V ₁₀₁ (V ₂₀₁ )>V ₁₀₂ (V ₂₀₂ ) ……(5). If the circuit configuration is such that the outputs of the comparator circuit 25 and the comparator circuit 26 are at a high level when the state of equation (5) is reached, the control circuit 27 operates and disconnects the drive circuits 16 and 17. As a result, transistors Q ₁₁ to Q ₁₄ are turned off.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

In FIG. 2, transistors Q ₁₀₁ and Q ₁₀₂ ,
Q ₁₀₃ and Q ₁₀₄ , Q ₁₀₅ and Q ₁₀₆ , and Q ₁₀₇ and Q ₁₀₈ are Darlington connected and together with resistors R ₂ , R ₃ , R ₅ , R ₇ and constant current sources 28 and 29, constitute an output circuit of BTL configuration. . Also, transistors Q ₁₁₁ to Q ₁₁₄ and resistors
R ₁ , R ₄ , R ₆ , R ₈ to R ₁₂ constitute a detection circuit, in which a diode D ₁ as a level shift circuit,
Contains _D2 . And transistors Q ₁₁₅ ~ _{Q 118}
A differential comparator circuit is composed of constant current sources 30 and 31 and resistors R ₁₅ and R ₁₆ , and transistors Q ₁₁₉ to
Q ₁₂₂ and resistors R ₁₇ to _{R 20} constitute a control circuit, and transistors Q ₁₀₉ and Q ₁₁₀ constitute a drive circuit. In addition, among the transistors, Q ₁₀₃ , Q ₁₀₇ , Q ₁₁₅ to _{Q 118}
is a PNP transistor and the others are NPN transistors,
32 is a ground terminal. Here, , diode D ₁
and _D2 have their forward voltages V _D1 and V _D2 respectively
As such, the base potentials of transistors Q ₁₁₆ and Q ₁₁₈ are lowered by V _D1 and V _D2 with respect to the base potentials of transistors Q ₁₁₅ and Q ₁₁₇ .

Next, the operation of this embodiment will be explained in Figs. 3, 4, and 5.
The operation will be explained with reference to an explanatory diagram of the operation shown in the figure.

Since the output circuit has a push-pull configuration, during normal operation, when transistors Q ₁₀₂ and Q ₁₀₈ are on, the current I ₁ in Figure 3 flows, and when transistors Q ₁₀₄ and Q ₁₀₆ are on, the current shown in Figure 3 flows. A current I′ ₁ flows. Transistors Q ₁₀₂ and Q ₁₀₈ are on, transistors Q ₁₀₄ and Q ₁₀₆ are off, or transistors Q ₁₀₂ and Q ₁₀₈ are off, transistors Q ₁₀₄ and
For switching to turn Q ₁₀₆ on, signals of opposite phases are applied to input terminals 11 and 12 from the outside, and switching is performed in accordance with the signals.

Also, during the on operation, the transistors Q ₁₀₂ ,
If the emitter area, DC current amplification factor h _{FE ,} etc. of Q ₁₀₈ and transistors Q ₁₀₄ and _{Q 106 are} the same, the base- _emitter voltage V _BE (hereinafter referred to _as V called _BE ) are equal.

Therefore, the voltage between the base of the detection transistor Q ₁₁₁ forming the detection circuit connected to the transistor Q ₁₀₂ and the output terminal 13, and the voltage between the detection transistor Q 111 forming the detection circuit connected to the transistor Q ₁₀₈
The voltage between the base of Q ₁₁₄ and the ground is equal, and the voltage between the base of the detection transistor Q ₁₁₃ constituting the detection circuit connected to transistor Q ₁₀₆ and the output terminal 14 is equal, and the voltage between the base of the detection transistor Q 113 and the output terminal 14 connected to transistor Q ₁₀₄ is equal. The voltages between the base of the detection transistor Q ₁₁₂ constituting the circuit and ground become equal. At this time, the collector current I _C11 flowing through the detection transistor Q ₁₁₁ is determined as follows.

V _BE2 = KT/ql _o {I _C11 (1+1)/h _FE11 )/I _S11 } +I _C11 (1+1/h _FE11 ) R ₁ ...(6) where, K: Boltzmann's constant, T: absolute temperature,
q: Electron charge, h _FE11 : DC current amplification factor of transistor Q ₁₁₁ , I _S11 : Reverse saturation current of transistor Q ₁₁₁ , V _BE2 : Base-emitter voltage of transistor Q ₁₀₂ .

Calculating I _C11 from equation (6), I _C11 = V _BE2 −KT/ql _o {I _C11 (1+1/h _FE11 )/I _S1
1 }/(1+1/h _FE11 )R ₁
...(7) Similarly, the collector current I _C14 flowing through the detection transistor Q ₁₁₄ is I _C14 = V _BE8 −KT/ql _o {I _C14 (1+1/h _FE14 )/I _S1
4 }/(1+1/h _FE14 )R ₈
...(7') However, h _FE14 : DC current amplification factor of transistor Q ₁₁₄ , I _S14 : Reverse saturation current of transistor Q ₁₁₄ ,
V _BE8 : Base-emitter voltage of transistor _Q108 .

Here, the collector current I _C2 flowing through transistor Q ₁₀₂ and the collector current flowing through transistor Q ₁₀₈
If it is equal to I _C8 , then V _BE2 = V _BE8 , and if the V _BE , h _FE and emitter area of transistors Q ₁₁₁ and Q ₁₁₄ are equal, and if R ₁₀ = R ₁₂ , then equation (7), (7′ ) formula, I _C11 = I _C14 .

Therefore, the input voltage of the differential comparator circuit, that is, the base potential V _B17 of transistors Q ₁₁₇ and Q ₁₁₈ ,
V _B18 is the forward voltage of diodes D ₁ and D ₂ which is V _D1 ,
Since V _D2 , V _B18 = V _CC −I _C14 ×R ₁₁ −V _D2 …(8) V _B17 = V _CC −I _C11 ×R ₁₀ …(9).

Here, since I _C11 = I _C14 and R ₁₀ = R ₁₁ , (8),
From equation (9), due to the difference in forward voltage V _D2 of diode D ₂ , V _B18 < V _B17 , transistor Q ₁₁₈ is in the on state, transistor Q ₁₁₇ is in the off state, and the resistance
Since no voltage drop occurs in R ₁₆ , transistors Q ₁₂₁ and Q ₁₂₂ forming the control circuit do not operate, and the output circuit also maintains normal operation.

Conversely, when the output transistors Q ₁₀₆ and Q ₁₀₄ are in the operating state, the detection transistors Q ₁₁₂ and Q ₁₁₃ perform the same operation as described above.

Next, consider the case where either the output terminal 13 or the output terminal 14 is grounded as shown in FIGS. 4 and 5.

First, as shown in Fig. 4, when the output terminal 13 is grounded, the collector current I _C2 of the transistor Q ₁₀₂
I _C2 = V _CC / rSCQ ₁₀₂ ...(9) However, rSCQ ₁₀₂ is the saturation resistance of transistor Q ₁₀₂ .

A current flows.

Here, when the output terminal 13 is grounded, the voltage V ₁₃ generated at the output terminal 13 is as follows: V ₁₃ = _{R S × I 2 ...} ( 10) A voltage is generated. Therefore, collector current I _C8 also flows through transistor Q ₁₀₈ , and its current value is I _C2 =
From I ₂ + I _C8 , I _C8 = I _C2 − I ₂ .

Therefore, since I _C8 < I _C2 , the transistor
From the formula of V _BE , V _BE ≒KT/ql _o I _C (1+1/h _FE )/ _IS , V _BE2 > V _BE8 .

Therefore, the collector current I _C11 of the transistor Q ₁₁₁ for detecting V _BE of the transistor Q ₁₀₂ is I _C11 = V _BE2 −KT/ql _o {I _C11 (1+1/h _FE11 )/I _S1
1 }/R ₁
...(10) becomes.

In addition, the collector current I _C14 of the transistor Q ₁₁₄ for detecting V _BE of the transistor Q ₁₀₈ is I _C14 = V _BE8 −KT/ql _o {I _C14 (1+1/h _FE14 )/I _S1
4 }/R ₈
...(11) becomes.

Here, if R ₁ = R ₈ and I _S11 = I _S14 , then V _BE2
>V _BE8 , so the relationship I _C11 > I _C14 holds true.

Next, the base potentials V _B18 and V _B17 of the transistors Q ₁₁₈ and Q ₁₁₇ in the comparator circuit are calculated from equations (8) and (9) as follows: V _B18 = V _CC −I _C14 ×R ₁₁ −V _D2 ……(8 ) V _B17 = V _CC − I _C11 × R ₁₀ ...(9) Since R ₁₁ = R ₁₀ , I _C11 > I _C14 , V _D2 < (I _C11 − I _C14 ) × R ₁₁ ...(12) In the state where V _BQ117 < _BQ118 , the transistor Q ₁₁₈ is turned off and the transistor Q ₁₁₇ is turned on, and a voltage drop occurs across the resistor R ₁₆ , so that the transistors Q ₁₂₁ , which constitute the control circuit, By operating Q ₁₂₂ and absorbing the base drive current of transistors Q ₁₀₂ and Q ₁₀₈ , it is possible to cut off transistors Q ₁₀₂ and Q ₁₀₈ and protect transistors Q ₁₀₂ and Q ₁₀₈ from overcurrent destruction. .

The above explanation describes the operation of the protection circuit when the transistors Q ₁₀₂ and Q ₁₀₈ are in the on state and the output terminal 13 is grounded.
Even when Q ₁₀₆ , Q ₁₀₄ are on and the output terminal 14 is grounded, the transistors Q ₁₁₂ , Q ₁₁₃ ,
Q ₁₁₅ and Q ₁₁₆ perform the same operation as above, and the transistors Q ₁₁₉ and Q ₁₂₀ forming the control circuit turn on and absorb the base drive current of transistors Q ₁₀₄ and Q ₁₀₆ , so that the transistor Q ₁₀₄ , cut off Q ₁₀₆ to prevent its destruction.

Next, when the output terminal 14 is grounded as shown in FIG. 5 and the transistors Q ₁₀₂ and Q ₁₀₈ are on, the collector current I _C2 of the transistor Q ₁₀₂ is I _C2 = V _CC − V _{CE (SAT)2} /R _L ...(13) where R _L is the load impedance, and V _CE(SAT)2 is the collector-emitter saturation voltage of transistor _Q102 .

becomes.

Here, if I _C2 is the current flowing to the ground point and I _C8 is the collector current of transistor Q ₁₀₈ , then I _C2 = _{I 3 +} I _C8 ... (14), and I _C8 = I _C2 - I ₃ ... …(15) Therefore, I _C2 > I _C8 .

Therefore, as shown above, V _BE2 > V _BE8 , and I _C11
＞I _C14 .

Here, as mentioned above, since the relationship I _C2 > I _C8 holds, the input voltage of the differential comparator circuit is V _B17
<V _B18 and a difference occurs, so the transistors Q ₁₂₁ and Q ₁₂₂ forming the control circuit turn on, cutting off the output circuit and preventing destruction.

Also, when the transistors Q ₁₀₆ and Q ₁₀₄ are on and the output terminal 13 is grounded, the same operation as above is performed, and the transistors forming the control circuit
Q ₁₁₉ and Q ₁₂₀ turn on, cutting off the output circuit and preventing damage.

As described above, according to this embodiment, the transistor _Q102 and
The protection circuit operates when the collector currents of Q ₁₀₈ or transistors Q ₁₀₆ and Q ₁₀₄ become unbalanced, so there is no malfunction even if the transistor is grounded with a resistor of several ohms.

Also, the unbalance ratio of the output transistor is (6)
From the formula, it can be set as V _D2 /R ₁₁ (or V _D1 /R ₉ ).

〔Effect of the invention〕

As explained in detail above, the BTL of the present invention
The circuit has the above-mentioned configuration and has a protection circuit that shuts off the transistor to prevent overcurrent from flowing when the output terminal is grounded, so it has the effect that the transistor will not be destroyed like in the past. have

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic configuration of the BTL circuit of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, and Figs. 3, 4, and 5 are explanatory diagrams of its operation. , FIG. 6 is a circuit diagram showing an example of a conventional BTL circuit. 11, 12... Input terminal, 13, 14... Output terminal, 15... Power supply terminal, 16, 17... Drive circuit, 18... Load, 19-22... Detection circuit, 2
3, 24... Level shift circuit, 25, 26...
Comparison circuit, 27... Control circuit, 28-31... Constant current source, 32... Ground terminal, 101, 102, 2
01, 202... Input terminal of comparison circuit, D ₁ , D ₂
...Diode, R ₁ to R ₁₆ ... Resistor, Q ₁₁ to _{Q 14} ,
Q ₁₀₁ , Q ₁₀₂ , Q ₁₀₄ ~ _{Q 106} , Q ₁₀₈ ~ Q ₁₁₄ , Q ₁₁₉ ~
Q ₁₂₂ ……NPN transistor, Q ₁₀₃ , Q ₁₀₇ , Q ₁₁₅
~Q ₁₁₈ ...PNP transistor.

Claims (1)

[Claims] 1. A first push-pull circuit in which first and second transistors are connected in series and whose midpoint is configured as a first output terminal; A BTL circuit having a second push-pull circuit configured with a point as a second output terminal, and first and second drive circuits that drive the inputs of the first and second push-pull circuits in opposite phases, respectively, first, second, third and fourth transistors that detect base-emitter voltages of the first, second, third and fourth transistors and output first, second, third and fourth detection signals, respectively; a fourth base-emitter voltage detection circuit; a first comparison circuit that compares the first detection signal and the fourth detection signal; and a comparison circuit that compares the third detection signal and the second detection signal. and a control circuit that controls the first and second drive circuits by using the output of the first comparison circuit and the output of the second comparison circuit as inputs. BTL circuit.