JPH05152436A - Large scale integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] High-speed operation is possible while keeping overall power consumption low, and circuit reliability is not reduced. [Structure] First supply voltage V1 (for example, 5 [V]) and first
The first circuit section 11 which operates by the operation clock CK1 of
And a second voltage V2 having a lower potential than the first supply voltage
(For example, 3 [V]) and the second circuit section 12 which operates by the second operation clock CK2 having a frequency higher than that of the first operation clock CK1 are provided on one integrated circuit 10. The circuit section (12) which is required to be driven is realized by low voltage driving, while the circuit (11) which does not require high speed operation is driven at low frequency and high voltage in order to improve reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large scale integrated circuit, and more particularly to a custom IC using gate array technology or standard cell technology.

[0002]

2. Description of the Related Art Among LSI's, a digital circuit applied to a custom IC using a gate array technique or a standard cell technique generally has a power supply voltage set to 5 [V]. Therefore, on the premise of this power supply voltage of 5 [V], development has been progressing day by day in order to highly integrate and speed up the circuit.

By the way, in recent years, an LSI having lower power consumption has been demanded in consideration of use of a battery power source in which a portability is emphasized in a personal computer or the like. The power consumption W of an LSI is generally expressed by the following formula: W = k · F · V ² (1) (However, k: constant, F: operating frequency, V: operating voltage for design.)

It is represented by As is clear from the equation (1), lowering the operating voltage in design is most effective in reducing power consumption. Therefore, the power supply voltage is lower than 5 [V], for example, 3 which is suitable for a battery power supply.
When the LSI is designed by setting it to [V], it becomes possible to increase the operation speed while suppressing the power consumption low. This is because by shortening the channel width of MOS-FET,
This is because the distance of electrons moving in the channel becomes shorter and the switching speed of the transistor becomes faster.

[0005]

However, when an LSI is designed with a low power supply voltage, it naturally has a problem that it is vulnerable to noise and the reliability of the circuit becomes low.

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable high-speed operation while keeping the overall power consumption low, and to realize a highly reliable large-scale integration. To provide a circuit.

[0007]

That is, according to the present invention, there is provided a first circuit portion (or a memory) which operates by a first supply voltage V1 (for example, 5 [V]) and a first operation clock CK1. A second voltage V2 (for example, 3 [V]) having a lower potential than the first supply voltage and the first operation clock CK1
A second circuit section (or a memory) that operates according to a second operation clock CK2 having a higher frequency is provided on one integrated circuit, and a circuit section that requires high-speed operation is driven by a low voltage. On the other hand, for circuits that do not require high-speed operation, low-frequency, high-voltage drive is used to improve reliability, enabling high-speed operation while keeping overall power consumption low, and It does not reduce the reliability of the circuit.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a chip structure according to an embodiment of the present invention, and 10 is an LSI chip. In the LSI chip 10, a first circuit portion to which a first power supply voltage 5 [V] and a first operation clock not shown here are supplied
11 and a second power supply voltage 3 [V] and a second circuit unit 12 to which a second operation clock (not shown) is supplied. The first circuit section 11 and the second circuit section 12 are connected as necessary, and at that time, a circuit for converting and synchronizing the signal voltage between the two circuits is used as the first circuit section. 11,
It is arranged on at least one of the second circuit portions 12.

However, both the first circuit portion 11 and the second circuit portion 12 are designed by the standard cell technique or the gate array technique according to the voltage value supplied, and therefore the second circuit portion 11 is designed. Since the supply voltage on the side of the circuit unit 12 is lower than the supply voltage on the side of the first circuit unit 11, the second circuit unit 12 side can operate at higher speed in terms of withstand voltage design.

In the above-mentioned structure, the first circuit section
The frequency of the operation clock supplied to 11 is set low, and the frequency of the operation clock supplied to the second circuit section 12 is set high to operate both the first circuit section 11 and the second circuit section 12, and Send and receive signals to and from the outside. By doing so, the second circuit unit 12 having a low power supply voltage performs a high-speed operation process, and the first circuit unit 11 having a high power supply voltage executes a low-speed but highly reliable operation process. The power consumption of both the circuit unit 12 and the first circuit unit 11 can be suppressed to be low, and as a result, the power consumption of the entire LSI chip 10 can be suppressed to be low. Then, referring to FIG. 2 and FIG.
A modified example will be described.

FIG. 2 shows another configuration example of the present invention.
This illustrates a case where a memory 14 is arranged in place of the second circuit section 12 of FIG. In the figure, in the LSI chip 10, a circuit portion 13 to which a first power supply voltage 5 [V] and a first operation clock not shown here are supplied, a second power supply voltage 3 [V] and here A memory 14 (not shown) to which a second operation clock is supplied is provided, and these circuit units 13 are provided.
A signal voltage converter 15 is arranged between the memory 14 and the memory 14.

Therefore, both the circuit section 13 and the memory 14 are designed by the standard cell technique or the gate array technique according to the voltage value supplied,
Therefore, the supply voltage on the side of the memory 14 is lower than the supply voltage on the side of the circuit section 13, so that the memory 14 side can operate at a higher speed in view of the withstand voltage design.

In the above structure, the frequency of the operation clock supplied to the circuit unit 13 is set low and the frequency of the operation clock supplied to the memory 14 is set high to operate both the circuit unit 13 and the memory 14. , Control signals with the outside,
In addition to transmitting / receiving data, the signal / voltage converting unit 15 writes / reads data between the circuit unit 13 and the memory 14. By doing so, the memory 14 having a low power supply voltage performs a high-speed write / read process, and the circuit unit 13 having a high power supply voltage performs a low-speed but highly reliable operation process. It is possible to suppress the power consumption of both sides to a low level, and as a result, to reduce the power consumption of the entire LSI chip 10.

With such a structure, if the circuit section 13 is a CPU and the memory 14 is a cache memory, for example, a one-chip microprocessor having a high-speed cache memory can be realized.

Contrary to FIG. 2, the memory 14 side is supplied with a high power supply voltage and a low frequency operation clock, and the circuit section 13 side is supplied with a low power supply voltage and a high frequency operation clock. However, the description thereof will be omitted.

FIG. 3 shows another configuration example of the present invention.
This illustrates an example in which a first memory 16 and a second memory 17 are arranged in place of the first circuit section 11 and the second circuit section 12 in FIG. In the figure, in the LSI chip 10, a first power supply voltage 5 [V] and a first memory 16 to which a first operation clock (not shown) is supplied, and a second power supply voltage 3
[V] and a second memory 17 to which a second operation clock (not shown) is supplied are provided independently.

Both the first memory 16 and the second memory 17 are designed by the standard cell technique or the gate array technique according to the voltage value supplied, and therefore, the second memory 17 side Since the supply voltage is lower than the supply voltage on the first memory 16 side, the second memory 17 side can operate at a higher speed because of the withstand voltage design.

In the above structure, the first memory
The frequency of the operation clock supplied to 16 is set low and the frequency of the operation clock supplied to the second memory 17 is set high to operate both the circuit unit 13 and the memory 14, and write data to the outside independently. / Perform read. By doing so, the second memory 17 having a low power supply voltage can perform high-speed data write / read processing with the first memory having a high power supply voltage.
In the first memory 16 of the first memory 16
The power consumption of both the second memory 17 and the second memory 17 can be kept low, and as a result, the power consumption of the LSI chip 10 as a whole can be kept low.

[0020]

As described above in detail, according to the present invention, the first
Circuit portion (or memory) that operates according to the supply voltage V1 (for example, 5 [V]) and the first operation clock CK1
And a second voltage V2 having a lower potential than the first supply voltage
(For example, 3 [V]) and the second circuit portion (or memory) that operates by the second operation clock CK2 having a higher frequency than the first operation clock CK1 are provided on one integrated circuit. While low-voltage drive realizes circuit parts that require high-speed operation, low-frequency, high-voltage drive is used to improve reliability for circuits that do not require high-speed operation, resulting in overall power consumption. It is possible to provide a large-scale integrated circuit that enables high-speed operation while keeping the value low and does not reduce the reliability of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a chip configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a chip configuration according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a chip configuration according to another embodiment of the present invention.

[Explanation of symbols]

10 ... LSI chip, 11 ... First circuit section, 12 ... Second circuit section, 13 ... Circuit section, 14 ... Memory, 15 ... Signal voltage conversion section, 16
... first memory, 17 ... second memory.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location G06F 15/78 510 P 7530-5L G11C 11/413 H01L 27/04 F 8427-4M 7323-5L G11C 11/34 335 A

Claims (2)

[Claims] 1. A first circuit portion which operates by a first supply voltage V1 and a first operation clock CK1, a second voltage V2 and a first voltage which are lower in potential than the first supply voltage.
And a second circuit section that operates with a second operation clock CK2 having a frequency higher than that of the operation clock CK1 of FIG. 2. A signal voltage conversion unit is provided between the first circuit unit and the second circuit unit.
Large scale integrated circuit described.