JPH05143211A - Input interface circuit - Google Patents

Abstract

PURPOSE:To make an input signal into a multilevel signal by plural threshold voltage levels without increasing the cost nor the packing area. CONSTITUTION:A Schmitt trigger element 11 makes an input signal into a pulse based on the threshold voltage level set in a rising mode and the threshold voltage level set in a falling mode and different from the former voltage level. An input I/F circuit 1 contains the element 11, a 3-state buffer 12, and a clock generating circuit 13. Thus, the input signal is inputted to the element 11 via a coupling resistor 14 and an input line 15. At the same time, the output of the buffer 12 is connected to the line 15. The element 11 decides the input signal by the threshold voltage level set in the rising mode in an OFF state and in the falling mode in an ON state respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input interface circuit for converting an input signal into a multi-valued signal by a plurality of threshold values in equipment including a digital signal processing circuit.

[0002]

2. Description of the Related Art Recently, in an input interface circuit in a device including a digital signal processing circuit, in order to improve the reliability of the input signal, a plurality of comparators having different threshold voltage values are connected in parallel to each other to input the input signal. There is a method in which the data is ternarized and judged by a processing circuit in the subsequent stage.

[0003]

However, in such a conventional method, since it is necessary to use a plurality of analog elements such as comparators having different threshold voltage values in order to convert the input signal into the ternary value, the cost is high. In addition, there is a problem that the mounting area becomes large.

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an input interface circuit capable of converting an input signal into a multi-valued signal by a plurality of threshold voltage values without increasing cost and mounting area. To aim.

[0005]

In order to achieve the above object, according to the present invention, in an input interface circuit that multivalues an input signal, a threshold voltage value at the time of rising of a pulse waveform when the input signal is pulsed and , The threshold voltage value at the time of falling of the pulse waveform is different, and the binarizing means for binarizing the input signal via the input line by the both threshold voltage values and the input line connected to the binarizing means. The three-state output means for making the output to the threshold voltage value at the rise of the binarization means or more, the threshold voltage value at the fall of the binarization means, or high impedance, and the binarization means input the input signal. Before, the output from the three-state output means to the input line is equal to or higher than the threshold voltage value at the time of rising or lower than the threshold voltage value at the time of falling. From which a control means for controlling to a high impedance, characterized in that equipped with a.

[0006]

According to the present invention, by the control of the control means, the three-state output means outputs the output to the input line above the threshold voltage value at the rising time or before the binarizing means inputs the input signal. By setting the threshold voltage value or less, the output of the binarizing means is turned on (on),
Alternatively, it can be set to the down state (off).

Subsequently, the input line becomes a high impedance state from both of the subsequent states, and 2
Since the input signal is input to the binarizing means, the binarizing means compares the input signals with the threshold voltage value at the falling time in the rising state, while the binarizing means makes the threshold voltage value at the rising time in the falling state. Compare the input signals with.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an input interface circuit (hereinafter referred to as an input I / F circuit) according to the present invention will be described below with reference to the drawings. Here, the input I / F circuit is connected to a digital filter circuit which is an example of a digital signal processing circuit for description.

FIG. 1 is a block diagram showing the configuration of an embodiment of the input I / F circuit 1 and the connection with the digital filter circuit 2.

The input I / F circuit 1 is provided with a Schmitt trigger element 11 as a binarization means, a three-state buffer 12 as a three-state output means, and a clock generation circuit 13 as a control means, and is externally supplied. Input signal is coupled to resistor 14 and input line 15
The input line 15 is connected to the output line 16 of the three-state buffer 12, and the output line 16 of the three-state buffer 12 is connected.

A digital filter circuit 2 is connected to the output of the Schmitt trigger element 11, and a Schmitt control signal (inverted FBCK0) and a sample are supplied from the clock generation circuit 13 to the digital filter circuit 2 and the three-state buffer 12, respectively. Clock (inverted DFNCK0, SRCK
0) is sent.

FIG. 2 shows the configuration of the clock generation circuit 13.

This clock generation circuit has a CP (not shown).
A reset signal (inverted RESET) and an original clock signal (DNFCLK) are input from a processor such as U, and based on these signals, a sample clock (inverted DFNCK0) is input to each of the four digital filter circuits and input I / F circuits. ~
3, SRCK0 to 3) and the Schmitt control signal (FBCK0 to 3 inverted) can be sent respectively, so that the NOT gate 1
31, shift register 132, NOT gate 133a-
d, NAND gates 134a to h, NOR gate 135
It is configured by connecting a to d as shown in the figure.

Since only the input I / F circuit 1 and the digital filter circuit 2 are shown in the present embodiment, only the Schmitt control signal (inverted FBCK0) and the sample clock (inverted DFNCK0, SRCK0) are used. Explain.

FIG. 3 shows the configuration of the digital filter circuit 2.

The digital filter circuit 2 has an input I
A 4-bit shift register 21 for inputting the output (IPA0) of the / F circuit 1 by the sample clock (SRCK0), a NAND gate 22 and a NOR gate 23 for processing the outputs (QA to D) of the shift register 21, an AND gate 24a, and A judgment circuit 24 which is composed of a NOR gate 24b and receives the outputs of the NAND gate 22 and the NOR gate 23 to judge ON / OFF of an input signal as will be described later.
It has a D flip-flop (hereinafter referred to as D-FF) 25, which is input by NCK0) and whose output Q is the output (INDA0) of this digital filter circuit 2. Also, DF
The F25 is connected so as to send the inverted output Qn to the determination circuit 24 and send the inverted output Qn to the three-state buffer 12 as a threshold selection signal (inverted FBDA0).

In this embodiment, the analog output of the photocoupler 3 is used as the input signal of the input I / F circuit 1.

Next, the input I / F circuit 1 shown in FIGS.
The circuit operation of the digital filter circuit 3 is shown in FIG.
This will be described with reference to FIG.

FIG. 4 shows the clock generation circuit 1 shown in FIG.
3, digital filter circuit 2 shown in FIG. 1 or FIG.
Input / output signals and internal signals in the input I / F circuit 1 are shown by a timing chart.

In the clock generation circuit 13 shown in FIG. 2, the outputs (QA to D) are output from the shift register 132 on the basis of the reset signal (RESET) and the original clock signal (DNCLK) input from the outside, and the Schmitt control is performed. Signal (inverted FBCK0) and sample clock (inverted DFNCK0, SR
CK0) is output.

In the digital filter circuit 2 shown in FIG. 3, the shift register 21 latches the output (IPA0) of the input I / F circuit 1 when the sample clock (SRCK0) from the clock generation circuit 13 rises. .. Also, depending on the rise of the sample clock (DFNCK0 inversion), D-FF25
Outputs the result determined as described later.

The input I / F shown in FIG. 1 or FIG.
In the circuit 1, the three-state output means 12 receives the threshold selection signal (inverted FBDA0) from the digital filter circuit 2, and the Schmitt control signal (inverted FBCK).
The output (PA0-R) is changed to Vc = 0 by "LOW" of 0).
Discharge to [V] or charge to Vc = 5 [V], and change the Schmitt control signal (inverted FBCK
Set to high impedance state by "HIGH" of 0).
The Schmitt trigger element 11 is an analog output from the photocoupler 3 when the output (PA0-R) of the three-state output means 12 is in a high impedance state, that is, when the Schmitt control signal (inversion FBCK0) is "HIGH". Input signal (PA0) and its analog input signal (PA0)
Is binarized by comparing the threshold voltage values Vth- and Vth +, and the binarized data (IPA0) is output.

FIG. 5 is a timing chart showing each signal when the Schmitt trigger element 11 of the input I / F circuit 1 shown in FIG. 1 binarizes the input signal at the threshold voltage value Vth + at the time of rising. ..

First, immediately before the Schmitt trigger element 11 takes in the input signal, the Schmitt control signal (inversion FBCK0) becomes “LOW” for a certain period of time, and the three-state buffer 12 turns on and functions as a buffer. Then, "0" of the threshold selection signal (FBDA0 inverted) is output.

The threshold selection signal (inverted FBDA0) is set to "0 (=
0 [V]) ”is the threshold voltage value Vth− at the fall of the Schmitt trigger element 11 (in this embodiment, for example, 1.5 [V]).
And ), The level of the input line 15 becomes lower than the threshold voltage value Vth- level, and the input (PA0-C) to the Schmitt trigger element 11 becomes the input signal (PA0). Turns off regardless of the voltage value.

When the Schmitt control signal (inversion FBCK0) becomes "HIGH", the output of the three-state buffer 12 becomes a high impedance state.
The input signal (PA0) is input to the Schmitt trigger element 11 as the input signal (PA0-C) via the resistor 14 and the input line 15.

At this time, since the Schmitt trigger element 11 has been in the off state until now, the comparator level at this time becomes the threshold voltage value Vth + at the time of the pulse rising from the off state to the on state, and this threshold voltage value. The input signal (PA0-C) is binarized by comparing Vth + with the input signal.

On the other hand, when the input signal is compared with the threshold voltage value Vth- when the Schmitt trigger element 11 is falling, the Schmitt trigger element 11 receives the input signal as in the case where the threshold voltage value Vth + is rising. Immediately before taking in, the Schmitt control signal (FBCK0 inverted) becomes “LOW” for a certain period of time, the three-state buffer 12 turns on, and the threshold selection signal (FBDA0 inverted) “1 (= 5
[V]) ”is output. This output“ 1 (= 5 [V]) ”is the threshold voltage value V when the Schmitt trigger element 11 rises.
Since it is preset to a value higher than th + (in this embodiment, 3.5 [V], for example), the level of the input line 15 becomes equal to or higher than the threshold voltage value Vth +, and the Schmitt trigger element 11 receives the input signal. Turns on regardless of the voltage value.

When the Schmitt control signal (inverted FBCK0) becomes "HIGH", the output of the three-state buffer 12 is in a high impedance state, so that the input signal (PA0- C) is input to the Schmitt trigger element 11.

Since the Schmitt trigger element 11 has been in the ON state until now, the threshold voltage value Vth at the time of the pulse falling of the comparator level from the ON state to the OFF state.
-, This threshold voltage value Vth- and the input signal (P
It will be binarized by comparing with A0-C).

The binarized data is input to the digital filter circuit 2, and in the digital filter circuit 2, the shift register 21 inputs the binarized data by the sample clock (SRCK0) as shown in FIG. Then, the decision circuit 24 decides on / off of the input signal based on the binarized data as described later.

FIGS. 6 (a) and 6 (b) each show a method of judging binarized data which is input data in the judgment circuit 24 of the digital filter circuit 2 according to the present invention and the prior art.

In the digital filter circuit 2, the shift register 21 temporarily stores the binarized data from the Schmitt trigger element 11 as shown in FIG.
The decision circuit 24 decides on / off of the input signal according to the following rules.

If the current state is off (threshold voltage value Vth +) and A2k are all 1 then on else then the current state is maintained if the current state is on (threshold voltage value Vth-) and A1k are all 0 then off else then the current state is maintained, however, n = 1, 2 depends on whether the current state is on or off, and corresponds to threshold voltage values Vth- and Vth + which are comparison levels. Therefore, when the current state is off, n = 1, and when the current state is on, n = 2.

During the on / off judgment of this input signal, the Schmitt trigger element 11 is currently on (threshold voltage value Vth-) and the output of the shift register 21 (QA to B).
Are all "1", and the current state is off (threshold voltage value Vth +), the output of the shift register 21 (QA ~
When all of B) become "0", the threshold voltage values Vth- and Vth + of the Schmitt trigger element 11 are switched.

That is, as shown in FIG. 3, when the Schmitt trigger element 11 is currently ON (threshold voltage value Vth-) and binarizing the input signal (PA0-C), the output of the shift register 21 is output. When all of (QA to B) become "1", the output of the NAND gate 22 becomes "0" and A
The output of the ND gate 24a also becomes "0", and the output of the NOR gate 24b becomes "1". Then, the D-FF 25 takes its output "1" into the input D by the sample clock (DFNCK0 inverted), the output Q changes to "1", while the inverted output Qn, that is, the threshold selection signal (FBDA0 inverted) is "0". Is input to the three-state buffer 12. The three-state buffer 12 outputs the threshold selection signal (inverted FBDA0) of "0" when the Schmitt control signal (inverted FBCK) becomes "LOW" to switch the Schmitt trigger element 11 to the off state. The Schmitt trigger element 11 is caused to binarize the input signal (PA0-C) with the threshold voltage value Vth +.

On the other hand, when the Schmitt trigger element 11 is currently off (threshold voltage value Vth +), the input signal (PA0-C) is 2
When digitizing, the output of the shift register 21 (QA
~ B) are all "0", the NOR gate 23
Becomes "1" and the output of the NOR gate 24b becomes "0". Then, the D-FF 25 takes "0" to the input D by the sample clock (DFNCK0 inverted), the output Q becomes "0", while the inverted output Qn, that is, the threshold selection signal (FBDA0) becomes "1". Input to the three-state buffer 12. Three-state buffer 1
In 2, the threshold selection signal (inverted FBDA0) when the Schmitt control signal (inverted FBCK) becomes “LOW”
"1" is output to switch the Schmitt trigger element 11 to the ON state, and the Schmitt trigger element 11 is made to binarize the input signal (PA0-C) with the threshold voltage value Vth-.

In other cases, that is, the shift register 2
If the outputs of 1 (QA to B) are not all "1" or "0", and if the threshold selection signal (inverted FBDA0) is "1", the outputs of the shift register 21 (QA to B) are all "0", When the threshold selection signal (inverted FBDA0) is "0" and the outputs (QA to B) of the shift register 21 are all "1", the output Q and the inverted output Qn of the D-FF 25 do not change and the Schmitt trigger element 11 does not change. Performs binarization of the input signal (PA0) with the current threshold voltage values Vth- and Vth +.

Therefore, in the prior art, when the input signal is binarized by two threshold values, two comparators are connected in parallel and two shifts are performed as shown in FIG. 6 (b). Whereas registers were needed,
In the present embodiment, as shown in FIG. 7A, different threshold voltage values Vth−,
Vth + is automatically switched and binarized by two threshold values, and only one shift register for storing the binarized result by the digital filter is required.

Therefore, according to the present embodiment, the cost is reduced as compared with the prior art, and the input I / F circuit and the digital filter circuit can be composed of only digital elements.
Compared with the analog element mixed type, the number of gates and
Mounting area etc. becomes smaller.

FIG. 7 is a timing chart showing each signal at the time of judgment in the digital filter circuit 2 when the input signal maintains the state of “HIGH (ON at 5 [V])”.

First, the threshold selection signal (inverted FBDA0) is "1 (= 5 [V])", the three-state buffer 12 is in the ON state, and its output (PA0-R) becomes Vc = 5 [V]. While being charged, the Schmitt trigger element 11 is currently on (threshold voltage value Vth-) and the input signal (PA0-C) is being binarized, and the "HIGH" input signal (PA0) is input. In this case, the input signal (PA0-C) remains "HIGH", and the Schmitt trigger element 11 receives the input signal (PA0-C).
0-R) is currently turned on (threshold voltage value Vth-) and binarized to output "1".

In the digital filter circuit 2, the binarization result is input and the output (QA ~
Until all of B) become "1", the D-FF 25 maintains the current state and outputs "0" from the output Q (see the above determination rule).

By the way, this input signal (PA0) is "HIGH".
Since the state of (5 [V]) is maintained, the Schmitt trigger element 11 continues to output "1", and immediately all the outputs (QA to B) of the shift register 21 become "1". The output of the judgment circuit 24 changes from "0" to "1",
The output Q of the D-FF 25 also changes from "0" to "1" and the input signal (PA0) is determined to be "1", while the inverted output Q
While n changes from "1" to "0" and the inverted output Qn "0" is input to the determination circuit 24, the inverted output Qn "0" is input to the three-state buffer 12 as the threshold selection signal (inverted FBDA0). ..

Then, this time, three-state buffer 1
When 2 is on, the threshold select signal (inverted FBDA0) “0” is output to its output (PA0-R), and the Schmitt trigger element 11 is turned off by this threshold select signal (inverted FBDA0) “0”. Switch to the input signal (PA0-
C) is binarized by the threshold voltage value Vth +.

At this time, the input signal (PA0) is "HIGH (5
[V]) ”is maintained, so three-state 12
When the output (PA0-R) is in the high impedance state, the output (IPA0) of the Schmitt trigger element 11 is in the ON state, that is, "1", and this result is sent to the digital filter circuit 2.

The digital filter circuit 2 inputs the binarized result and outputs the shift register 21 (QA to B).
Until all become "0", "1" for maintaining the current state is output from the output Q of the D-FF 25 (see the above determination rule). That is, the digital filter circuit 2 outputs the D-FF as the output (INDA0) of the digital filter circuit 2 while the input signal (PA0) maintains the "HIGH (5 [V])" state.
The output Q of 25 outputs "1" to determine that the input signal (PA0) is "1".

[0048]

As described above, according to the present invention, the threshold voltage value when the pulse waveform rises when the input signal is pulsed and the threshold voltage value when the pulse waveform falls and both thresholds are different. Binarizing means for binarizing the input signal via the input line according to the voltage value is provided, and before the binarizing means inputs the input signal, the output of the binarizing means is activated (on), or Since the input line is set to the high impedance state from both of the states set to the falling (OFF) state and the input signal is input to the binarizing means via the input line, the binarizing means is set to the rising state. In some cases, the input signals can be compared with the threshold voltage value at the falling time, while in the falling state, the input signals can be compared with the threshold voltage value at the rising time.

Therefore, according to the present invention, when the input signal is binarized by two threshold values, one binarizing means is required as compared with the prior art which requires two comparators. Therefore, the cost is reduced and the mounting area is reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration and the like of an embodiment of an input I / F circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a clock generation circuit.

FIG. 3 is a circuit diagram showing a configuration of a digital filter circuit.

FIG. 4 is a timing chart showing input / output signals and internal signals in a clock generation circuit, a digital filter circuit, and an input I / F circuit.

FIG. 5 is a timing chart showing each signal when a Schmitt trigger element of the input I / F circuit binarizes an input signal with a threshold voltage value Vth + at the time of rising.

6 (a) and 6 (b) are explanatory views showing a method for determining binarized data in a digital filter circuit according to the present invention and the related art.

FIG. 7 is a timing chart showing each signal at the time of determination in the digital filter circuit when the input signal maintains the “HIGH” state.

[Explanation of symbols]

1 Input Interface Circuit (Input I / F Circuit) 2 Digital Filter Circuit 3 Photocoupler 11 Schmitt Trigger Element (Binarizing Means) 12 Three-State Buffer (Three-State Output Means) 13 Clock Generation Circuit (Control Means) 14 Resistor 15 Inputs line

Claims (1)

[Claims] 1. In an input interface circuit for converting an input signal into a multi-valued signal, the threshold voltage value at the rising edge of the pulse waveform when the input signal is pulsed is different from the threshold voltage value at the falling edge of the pulse waveform. A binarizing means for binarizing an input signal via an input line according to both threshold voltage values, and an output to this input line, which is connected to the input line, and a threshold at the time of rising of the binarizing means. More than voltage value,
Before the input signal is input to the three-state output means for setting the threshold voltage value at the time of falling or lower, or high impedance, the output from the three-state output means to the input line rises. An input interface circuit comprising: control means for controlling the impedance to a high impedance from a threshold voltage value at time or more or a threshold voltage value at fall or less.