JPH05136565A - Thick-film multilayer ceramic board - Google Patents
Thick-film multilayer ceramic boardInfo
- Publication number
- JPH05136565A JPH05136565A JP3300751A JP30075191A JPH05136565A JP H05136565 A JPH05136565 A JP H05136565A JP 3300751 A JP3300751 A JP 3300751A JP 30075191 A JP30075191 A JP 30075191A JP H05136565 A JPH05136565 A JP H05136565A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder
- conductor layer
- multilayer ceramic
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 138
- 239000004020 conductor Substances 0.000 claims description 71
- 239000011247 coating layer Substances 0.000 claims description 29
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000002241 glass-ceramic Substances 0.000 abstract description 15
- 238000007650 screen-printing Methods 0.000 abstract description 12
- 230000008646 thermal stress Effects 0.000 abstract description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 10
- 229910052709 silver Inorganic materials 0.000 description 10
- 239000004332 silver Substances 0.000 description 10
- 238000010304 firing Methods 0.000 description 9
- 230000035882 stress Effects 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000008642 heat stress Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、厚膜多層セラミックス
基板、特にその表面に設けられた半田接合用導体層部の
構造を改良した厚膜多層セラミックス基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film multilayer ceramic substrate, and more particularly to a thick film multilayer ceramic substrate having an improved structure of a solder bonding conductor layer provided on the surface thereof.
【0002】[0002]
【従来の技術】厚膜多層セラミックス基板は、アルミナ
等の焼結セラミックス基体上に厚膜導体層および厚膜誘
電体層を、順次各ペーストを印刷、焼成することによっ
て形成される。厚膜多層セラミックス基板は、その製造
が簡便であること、および低い焼成温度を使用できるの
で銀、金、銅等の低抵抗導体が使用できること等の利点
がある反面、誘電体層のガラスセラミックスが脆弱であ
るため強度が十分でないという問題が従来より指摘され
ていた。特に、図2に示すように、基板表面の誘電体層
21上に設けた半田接合用導体層22を介して半田接合23に
より機能部品24を搭載した場合には、半田と導体層およ
び誘電体層の間の熱膨脹係数の違いによって応力が発生
し、冷熱衝撃等熱ストレス負荷時に誘電体層にクラック
等が発生して内部導体25との間で電気絶縁性の不良を招
く等の問題があった。半田の代わりにエポキシ等の有機
導電性接着剤によって機能部品を接合することも行われ
ているが、有機導電性接着剤には、接着強度が充分でな
い、コストが高い等の欠点がある。このため、機能部品
の搭載された厚膜多層セラミックス基板は熱ストレス耐
性の必要性の低い用途に限定されているのが現状であ
る。2. Description of the Related Art A thick film multilayer ceramic substrate is formed by sequentially printing and firing pastes of a thick film conductor layer and a thick film dielectric layer on a sintered ceramic substrate such as alumina. The thick film multilayer ceramic substrate has the advantages that it is easy to manufacture and that a low firing temperature can be used, so that a low resistance conductor such as silver, gold, or copper can be used. It has been pointed out that the strength is not sufficient because it is fragile. In particular, as shown in FIG. 2, the dielectric layer on the substrate surface
When the functional component 24 is mounted by the solder joint 23 through the solder joint conductor layer 22 provided on the 21, the stress is generated due to the difference in the thermal expansion coefficient between the solder and the conductor layer and the dielectric layer, and the cold heat is generated. There has been a problem that cracks or the like are generated in the dielectric layer when a thermal stress such as impact is applied, resulting in poor electrical insulation with the internal conductor 25. Although functional components are also joined with an organic conductive adhesive such as epoxy instead of solder, the organic conductive adhesive has drawbacks such as insufficient adhesive strength and high cost. For this reason, the thick film multilayer ceramic substrate on which the functional component is mounted is currently limited to applications in which thermal stress resistance is low.
【0003】[0003]
【発明が解決しようとする課題】以上説明したように、
従来の厚膜多層セラミックス基板においては、半田接合
部位とその下部に存在する内層導体間の電気絶縁の信頼
性が特に熱ストレス負荷時に著しく劣化するという問題
がある。したがって、本発明の目的は、多層構造表面に
機能部品が半田接合により搭載される厚膜多層セラミッ
クス基板であって熱ストレス負荷下にあっても下部の内
層導体との間に不必要な導通が発生しないより信頼性の
高い厚膜多層セラミックス基板を提供することにある。As described above,
In the conventional thick film multilayer ceramic substrate, there is a problem that the reliability of electrical insulation between the solder joint portion and the inner layer conductor existing below the solder joint portion is significantly deteriorated especially when a thermal stress is applied. Therefore, an object of the present invention is a thick-film multilayer ceramic substrate in which functional components are mounted on the surface of a multilayer structure by soldering, and unnecessary conduction with the lower inner-layer conductor is achieved even under a thermal stress load. Another object of the present invention is to provide a thick-film multilayer ceramic substrate that is more reliable and does not occur.
【0004】[0004]
【課題を解決するための手段およびその作用】前記目的
は、表面誘電体層上に導体層が設けられ該導体層上に形
成した半田層を介して該導体層と機能部品とが電気接続
される厚膜多層セラミックス基板において、前記導体層
の周縁に沿って該導体層を覆う半田に濡れない材料から
なる被覆層を設け該被覆層によって囲まれた領域内に前
記半田層を形成することによって達成される。前記被覆
層は、前記導体層の周縁から少なくとも20μmの幅で
該導体層の周縁部を被覆していることが好まい。また、
前記被覆層に覆われる導体層は、少なくとも5μmの厚
さを有していることが好ましい。[Means for Solving the Problems and Its Action] The object is to provide a conductor layer on a surface dielectric layer, and electrically connect the conductor layer and a functional component through a solder layer formed on the conductor layer. In the thick-film multilayer ceramic substrate, a coating layer made of a material that does not wet the solder is provided to cover the conductor layer along the periphery of the conductor layer, and the solder layer is formed in a region surrounded by the coating layer. To be achieved. It is preferable that the coating layer covers the peripheral portion of the conductor layer with a width of at least 20 μm from the peripheral edge of the conductor layer. Also,
The conductor layer covered by the coating layer preferably has a thickness of at least 5 μm.
【0005】本発明の厚膜多層セラミックス基板の基体
から最も遠い厚膜誘電体層すなわち表面誘電体層の表面
には半田接合用の導体層が設けられている。本発明にお
いて、この表面誘電体層上の導体層を構成する材料とし
ては、銀、銅またはこれらを主成分とする軟質の合金が
好ましい。この他、金、パラジウム、および白金等をも
使用するこができる。また、導体層は、本発明の被覆層
に覆われる周縁部内側において5μm以上の厚さを有し
ていることが好ましい。A conductor layer for solder bonding is provided on the surface of the thick film dielectric layer, that is, the surface dielectric layer, farthest from the substrate of the thick film multilayer ceramic substrate of the present invention. In the present invention, the material forming the conductor layer on the surface dielectric layer is preferably silver, copper or a soft alloy containing these as the main components. In addition, gold, palladium, platinum and the like can be used. In addition, the conductor layer preferably has a thickness of 5 μm or more inside the peripheral edge portion covered with the coating layer of the present invention.
【0006】この導体層の表面には、導体層の周縁に沿
って周縁から所定の幅で導体層を覆う被覆層が設けられ
ている。この被覆層はガラスセラミックス等の半田に濡
れない材料からなる層である。被覆層を構成する材料と
しては、ガラスセラミックスの他に、樹脂および金属酸
化物等が挙げられる。被覆層は導体層の周縁に沿って該
周縁から少なくとも20μm、より好ましくは50μm
の幅で導体層を覆うことが好ましい。この被覆層と導体
層の重なり部分の幅は、導体材料、半田材料、および使
用条件等を考慮して選択する。On the surface of the conductor layer, a coating layer is provided along the periphery of the conductor layer so as to cover the conductor layer with a predetermined width from the periphery. This coating layer is a layer made of a material that does not get wet with solder, such as glass ceramics. Examples of the material forming the coating layer include resins and metal oxides in addition to glass ceramics. The coating layer is at least 20 μm, more preferably 50 μm from the periphery along the periphery of the conductor layer.
It is preferable to cover the conductor layer with a width of. The width of the overlapping portion of the coating layer and the conductor layer is selected in consideration of the conductor material, the solder material, the usage conditions and the like.
【0007】導体層表面の被覆層によって囲まれた領域
内すなわち導体層の中央部には半田層が形成されてい
る。本発明は、導体層上の半田層の形状が被覆層の存在
によって管理され、導体層表面の被覆層によって囲まれ
た領域内でのみ機能部品との半田接合をなすものであ
る。半田層を構成する材料としては、錫、鉛、銀、ビス
マス、インジウム等の合金が挙げられる。A solder layer is formed in a region surrounded by the coating layer on the surface of the conductor layer, that is, in the central portion of the conductor layer. According to the present invention, the shape of the solder layer on the conductor layer is controlled by the presence of the coating layer, and the solder connection with the functional component is made only in the area surrounded by the coating layer on the surface of the conductor layer. Examples of the material forming the solder layer include alloys such as tin, lead, silver, bismuth and indium.
【0008】以上説明したように、本発明の厚膜多層セ
ラミックス基板は、厚膜ガラスセラミックス等により形
成された多層回路基板において、表面の導体層の周縁部
にガラスセラミックス等の被覆層を設け、半田層端部の
下に軟質金属等の導体層が、好ましくは所定の厚さで、
存在するようにして半田層と表面誘電体層との接点が存
在しないようにしたことを特徴とする。本発明の作用は
次のように説明される。As described above, the thick-film multilayer ceramic substrate of the present invention is a multilayer circuit substrate formed of thick-film glass ceramic or the like, in which a coating layer of glass ceramic or the like is provided on the peripheral portion of the conductor layer on the surface, A conductor layer such as a soft metal under the solder layer end portion, preferably with a predetermined thickness,
The present invention is characterized in that the contact between the solder layer and the surface dielectric layer does not exist so as to exist. The operation of the present invention will be explained as follows.
【0009】ガラスセラミックス誘電体層の熱膨脹係数
は一般に5〜10 ppm/℃の範囲にあり、これに対して
半田層、導体層は各々20〜30 ppm/℃、15〜20
ppm/℃である。この金属−セラミックス間の熱膨脹係
数の差により、半田層には温度変化によって応力が発生
し、特に半田層端部には剪断応力が集中する。このた
め、急激な温度変化が繰り返されるような状況では、半
田層端部に接する誘電体層が剪断応力により破壊され亀
裂が生じて、内部導体と半田接合用導体層との間で絶縁
不良等の故障を起こす。The coefficient of thermal expansion of the glass-ceramic dielectric layer is generally in the range of 5 to 10 ppm / ° C., whereas the solder layer and the conductor layer are respectively 20 to 30 ppm / ° C. and 15 to 20 ppm.
ppm / ° C. Due to the difference in the coefficient of thermal expansion between the metal and the ceramic, stress is generated in the solder layer due to the temperature change, and shear stress is concentrated especially on the end portion of the solder layer. Therefore, in a situation where rapid temperature changes are repeated, the dielectric layer in contact with the solder layer end is broken by shear stress and cracks occur, resulting in poor insulation between the internal conductor and the solder bonding conductor layer. Cause a failure.
【0010】半田接合用導体層の周縁をガラスセラミッ
クス等で被覆し、半田層の形状を半田接合用導体層の中
央部に限定することにより、この応力集中の位置を、該
導体層の周縁すなわち外端から内側に移動することが可
能となる。そして半田端部下の導体層が応力を吸収する
ので、過酷な熱ストレスに耐えることができるようにな
るのである。この場合、導体層を構成する成分を、銀、
銅等の軟質の金属を主体としたものとすれば、導体層の
応力吸収力が大きくなるので、より一層過酷な熱ストレ
スにも耐える厚膜多層セラミックス基板となる。本発明
の厚膜多層セラミックス基板の半田層上には、コンデン
サ、抵抗、トランジスタ、リードワイヤ等の機能部品を
取付けることができる。機能部品が搭載された本発明の
厚膜多層セラミックス基板は、より高信頼性の必要とさ
れる各種電気回路等に使用することができる。By covering the periphery of the solder-bonding conductor layer with glass ceramics or the like and limiting the shape of the solder layer to the central portion of the solder-bonding conductor layer, the position of this stress concentration can be set at the periphery of the conductor layer. It is possible to move inward from the outer end. Since the conductor layer under the solder end absorbs the stress, it becomes possible to endure severe thermal stress. In this case, the constituents of the conductor layer are silver,
If a soft metal such as copper is mainly used, the stress absorption capacity of the conductor layer is increased, so that the thick film multilayer ceramic substrate can withstand even more severe thermal stress. Functional components such as capacitors, resistors, transistors and lead wires can be mounted on the solder layer of the thick film multilayer ceramic substrate of the present invention. The thick film multilayer ceramic substrate of the present invention on which functional components are mounted can be used for various electric circuits and the like that require higher reliability.
【0011】[0011]
【実施例】以下本発明を実施例および比較例を挙げて本
発明を説明する。初めに、本実施例および比較例におい
て使用した各種厚膜材料の組成を表1に、また本実施例
および比較例において使用した各種機能部品の内容を表
2に示す。EXAMPLES The present invention will be described below with reference to examples and comparative examples. First, Table 1 shows the compositions of various thick film materials used in the examples and comparative examples, and Table 2 shows the contents of various functional parts used in the examples and comparative examples.
【0012】[0012]
【表1】 [Table 1]
【0013】[0013]
【表2】 試料1〜8[Table 2] Samples 1-8
【0014】96%アルミナの基体上に、白金/銀の厚
膜導体層1層およびガラスセラミックスAの厚膜誘電体
層2層を、それぞれ順次スクリーン印刷、焼成により積
層形成した。そして、その最上層にある厚膜誘電体層す
なわち表面誘電体層上に、表3に示す種々の材料を用い
て、スクリーン印刷、焼成法にて厚さ12μmの導体層
を形成した。次に、63Sn/37Pd半田ペーストを
用いてスクリーン印刷にて厚さ200μmの半田層を形
成し、表3に示す機能部品を取付けた。それから、常法
に従いピーク温度230℃にてリフロー処理を施して、
比較例の試料1、3、5および7を作成した。A platinum / silver thick film conductor layer 1 layer and a glass ceramic A thick film dielectric layer 2 layer were sequentially laminated on a 96% alumina substrate by screen printing and firing. Then, a conductor layer having a thickness of 12 μm was formed on the thick film dielectric layer on the uppermost layer, that is, the surface dielectric layer, by using various materials shown in Table 3 by screen printing and firing. Next, a solder layer having a thickness of 200 μm was formed by screen printing using 63Sn / 37Pd solder paste, and the functional parts shown in Table 3 were attached. Then, according to a conventional method, reflow treatment is performed at a peak temperature of 230 ° C.,
Comparative samples 1, 3, 5 and 7 were prepared.
【0015】次に、本発明の試料2、4、6および8を
作成した。図1は試料2の断面模式図である。まず、試
料1と同様にして厚膜導体層および厚膜誘電体層を順次
積層し,表面誘電体層11上に厚さ12μmの導体層12を
形成した。その導体層の周縁にガラスセラミックスCペ
ーストを用いてスクリーン印刷、焼成法にて厚さ10μ
mの被覆層13を形成した。この被覆層は導体層を周縁12
1 から200μmの幅で覆うとともに、表面誘電体層上
をも覆うように形成した。それから、被覆層によって囲
まれた領域内に、63Sn/37Pd半田ペーストを用
いてスクリーン印刷にて厚さ200μmの半田層14を形
成し、その上に表3に示す機能部品15を取付けた。その
後、常法に従いピーク温度230℃のリフロー処理を施
して、試料2、4、6および8を作成した。Next, samples 2, 4, 6 and 8 of the present invention were prepared. FIG. 1 is a schematic sectional view of Sample 2. First, in the same manner as in Sample 1, a thick film conductor layer and a thick film dielectric layer were sequentially laminated to form a conductor layer 12 having a thickness of 12 μm on the surface dielectric layer 11. The thickness of the conductor layer is 10 μm by screen printing and firing method using glass ceramics C paste on the periphery of the conductor layer.
m coating layer 13 was formed. This covering layer surrounds the conductor layer 12
It was formed so as to cover the surface dielectric layer with a width of 1 to 200 μm. Then, in the area surrounded by the coating layer, a solder layer 14 having a thickness of 200 μm was formed by screen printing using 63Sn / 37Pd solder paste, and the functional component 15 shown in Table 3 was attached thereon. Then, reflow treatment with a peak temperature of 230 ° C. was performed according to a conventional method to prepare samples 2, 4, 6 and 8.
【0016】試料1〜8について、次のようにして耐熱
ストレス負荷試験を行った。各試料を10個用意し、−
55℃に30分間保持した後125℃に30分間保持す
る熱処理を1サイクルとして、これを50サイクル行な
い、絶縁不良が発生した試料の個数を調べた。同様の熱
処理を100サイクル繰り返した場合に発生した絶縁不
良の数も調べた。これらの試験結果を表3に示す。表3
の結果から、導体層の周縁に被覆層を形成して半田層の
形状を管理することにより、絶縁不良の発生割合が低減
できることがわかる。The samples 1 to 8 were subjected to a thermal stress load test as follows. Prepare 10 samples for each,
The heat treatment of holding at 55 ° C. for 30 minutes and then at 125 ° C. for 30 minutes was set as one cycle, and this cycle was performed for 50 cycles to examine the number of samples in which insulation failure occurred. The number of insulation defects that occurred when the same heat treatment was repeated 100 cycles was also examined. The results of these tests are shown in Table 3. Table 3
From the results, it can be seen that the rate of occurrence of insulation failure can be reduced by forming the coating layer on the periphery of the conductor layer and controlling the shape of the solder layer.
【0017】[0017]
【表3】 試料11〜18[Table 3] Samples 11-18
【0018】96%アルミナの基体上に、白金/銀の厚
膜導体層1層およびガラスセラミックスBの厚膜誘電体
層2層を順次積層形成した。そして、その最上層にある
表面誘電体層上に、白金/銀ペーストを用いてスクリー
ン印刷、焼成法にて厚さ12μmの導体層を形成した。
次に、63Sn/37Pd半田ペーストを用いてスクリ
ーン印刷にて表4に示す通り200μmまたは300μ
mの厚さの半田層を形成し、表4に示す機能部品を取付
けた。それから常法に従いピーク温度230℃のリフロ
ー処理を施して、試料11〜13を作成した。A platinum / silver thick film conductor layer and a glass ceramic B thick film dielectric layer were sequentially laminated on a 96% alumina substrate. Then, a conductor layer having a thickness of 12 μm was formed on the uppermost surface dielectric layer by using a platinum / silver paste by screen printing and a firing method.
Next, using 63Sn / 37Pd solder paste, screen printing was performed to obtain 200 μm or 300 μm as shown in Table 4.
A solder layer having a thickness of m was formed and the functional parts shown in Table 4 were attached. Then, according to a conventional method, a reflow treatment with a peak temperature of 230 ° C. was performed to prepare samples 11 to 13.
【0019】次に、試料11〜13と同様にして基体上
に厚膜導体層と厚膜誘電体層を積層し表面誘電体層上に
導体層を形成した。その導体層の周縁にガラスセラミッ
クスCペーストを用いてスクリーン印刷、焼成すること
によって、厚さ10μmの被覆層を形成した。この被覆
層は、導体層を周縁から表4に示す通り100μmまた
は200μmの幅で覆うように形成した。また、表面誘
電体層上をも覆うように形成した。それから、被覆層内
側に63Sn/37Pd半田ペーストを用いてスクリー
ン印刷して、表4に示す通り200μmまたは300μ
mの厚さの半田層を形成し、その上に表4に示す通りの
機能部品を取付けた。それから常法に従いピーク温度2
30℃のリフロー処理を施して試料14〜18を作成し
た。試料11〜18について、先に述べたものと同様の
耐熱ストレス負荷試験を行ない、各試料10個のうちの
絶縁不良の発生個数を測定した。Then, in the same manner as in Samples 11 to 13, a thick film conductor layer and a thick film dielectric layer were laminated on the substrate to form a conductor layer on the surface dielectric layer. A coating layer having a thickness of 10 μm was formed on the periphery of the conductor layer by screen-printing and firing the glass ceramics C paste. This coating layer was formed so as to cover the conductor layer with a width of 100 μm or 200 μm from the periphery as shown in Table 4. Further, it was formed so as to also cover the surface dielectric layer. Then, 63Sn / 37Pd solder paste was screen-printed on the inside of the coating layer to obtain 200 μm or 300 μm as shown in Table 4.
A solder layer having a thickness of m was formed, and functional parts as shown in Table 4 were attached thereon. Then, according to the usual method, peak temperature 2
Reflow treatment was performed at 30 ° C. to prepare Samples 14 to 18. The samples 11 to 18 were subjected to the same thermal stress load test as described above, and the number of occurrences of insulation failure out of 10 samples was measured.
【0020】[0020]
【表4】 試料21〜28[Table 4] Samples 21-28
【0021】誘電体層の材料をガラスセラミックスAに
変更した以外は試料11〜18と同様にして、試料21
〜28を作成し、耐熱ストレス負荷試験を行った。結果
を表5に示す。Sample 21 was prepared in the same manner as samples 11 to 18 except that the material of the dielectric layer was changed to glass ceramics A.
28 were prepared and a heat stress stress test was conducted. The results are shown in Table 5.
【0022】[0022]
【表5】 試料31〜38[Table 5] Samples 31-38
【0023】表層導体層の材料を銀に、誘電体層の材料
をガラスセラミックスAに、それぞれ変更した以外は試
料11〜18と同様にして試料31〜38を作成し、耐
熱ストレス負荷試験を行った。結果を表6に示す。Samples 31 to 38 were prepared in the same manner as samples 11 to 18 except that the material of the surface conductor layer was changed to silver and the material of the dielectric layer was changed to glass ceramics A, and a heat stress load test was conducted. It was The results are shown in Table 6.
【0024】[0024]
【表6】 [Table 6]
【0025】表3〜6の結果から、誘電体層の材料、導
体層の材料、実装する機能部品の種類、被覆層の幅を変
えても、半田層の形状を管理することにより、絶縁不良
の発生を低減できることがわかる。なお、試料1〜38
の製造方法の説明において記載した半田層の厚さとは、
機能部品を取付ける前の膜厚すなわちスクリーン印刷し
た際における膜厚をいう。 試料41〜48From the results of Tables 3 to 6, even if the material of the dielectric layer, the material of the conductor layer, the type of the functional component to be mounted, and the width of the coating layer are changed, the shape of the solder layer is controlled to prevent insulation failure. It can be seen that the occurrence of Samples 1 to 38
With the thickness of the solder layer described in the description of the manufacturing method of
The film thickness before mounting the functional component, that is, the film thickness after screen printing. Samples 41-48
【0026】96%アルミナ基体上に、ガラスセラミッ
クスAの厚膜誘電体層を2層順次積層形成した。そし
て、その最上層にある厚膜誘電体層(表面誘電体層)上
に、表7に示す通り、銀、パラジウム/銀、および銅ペ
ーストを用いて、スクリーン印刷、焼成法にて表7に示
す通りの厚さの2×2mmサイズの厚膜導体層を形成し
た。その導体層の周縁にガラスセラミックスC、Dおよ
び樹脂Aを用いてスクリーン印刷、焼成(樹脂Aについ
ては硬化)することによって、厚さ10μmの被覆層を
形成した。この被覆層は、導体層をその周縁から表7に
示す通り100μmまたは200μmの幅で覆うように
形成した。また、表面誘電体層上を導体層の周囲400
μmの幅で覆うようにした。それから、被覆層内側に6
3Sn/37Pd半田(2mmφボール)を用いてピー
ク温度230℃のリフロー処理を施して半球状の半田層
を形成し、その上に0.8mmφ銅ワイヤーを取付け
て、試料41〜48を作成した。試料41〜48につい
て、先に述べたものと同様の耐熱ストレス負荷試験を行
なった。結果を表7に示す。表7の結果から、誘電体層
の材料、導体層の膜厚を変えても、半田層の形状を管理
することにより、絶縁不良の発生を低減できることがわ
かる。Two thick film dielectric layers of glass ceramics A were sequentially laminated on a 96% alumina substrate. Then, as shown in Table 7, silver, palladium / silver, and copper paste were used on the thick film dielectric layer (surface dielectric layer), which is the uppermost layer, by screen printing and firing to obtain Table 7. A thick film conductor layer of 2 × 2 mm size having the thickness shown was formed. A coating layer having a thickness of 10 μm was formed on the peripheral edge of the conductor layer by screen printing and firing (curing for resin A) using glass ceramics C and D and resin A. This coating layer was formed so as to cover the conductor layer with a width of 100 μm or 200 μm from the periphery as shown in Table 7. In addition, the surface of the dielectric layer is surrounded by 400
It was made to cover with a width of μm. Then, 6 inside the coating layer
Samples 41 to 48 were prepared by using 3Sn / 37Pd solder (2 mmφ ball) to perform a reflow treatment at a peak temperature of 230 ° C. to form a hemispherical solder layer, on which a 0.8 mmφ copper wire was attached. The samples 41 to 48 were subjected to the same heat stress stress load test as described above. The results are shown in Table 7. From the results in Table 7, it can be seen that the occurrence of insulation failure can be reduced by controlling the shape of the solder layer even if the material of the dielectric layer and the film thickness of the conductor layer are changed.
【0027】[0027]
【表7】 [Table 7]
【0028】[0028]
【発明の効果】以上説明したように、本発明にかかる厚
膜多層セラミックス基板は、表面誘電体層上の導体層の
周縁に沿って被覆層が設けられ、該被覆層によって囲ま
れた領域内に半田層が形成されているので、半田層と表
面誘電体層との接点が存在せず、その結果、熱ストレス
負荷下にあっても誘電体層が破壊されない信頼性の高い
厚膜多層セラミックス基板である。As described above, in the thick film multilayer ceramic substrate according to the present invention, the coating layer is provided along the periphery of the conductor layer on the surface dielectric layer, and within the area surrounded by the coating layer. Since the solder layer is formed on the surface, there is no contact between the solder layer and the surface dielectric layer, and as a result, the dielectric layer is not destroyed even under thermal stress load. It is a substrate.
【図1】本発明の一実施例の厚膜多層セラミックス基板
の断面模式図である。FIG. 1 is a schematic sectional view of a thick film multilayer ceramic substrate according to an embodiment of the present invention.
【図2】従来の厚膜多層セラミックス基板の断面模式図
である。FIG. 2 is a schematic sectional view of a conventional thick film multilayer ceramic substrate.
11…表面誘電体層、12…導体層、121 …導体層周縁、13
…被覆層、14…半田層、15…機能部品。11 ... Surface dielectric layer, 12 ... Conductor layer, 121 ... Conductor layer periphery, 13
… Covering layer, 14… Solder layer, 15… Functional parts.
Claims (2)
体層上に形成した半田層を介して該導体層と機能部品と
が電気接続される厚膜多層セラミックス基板において、 前記導体層の周縁に沿って該導体層を覆う半田に濡れな
い材料からなる被覆層を設け該被覆層によって囲まれた
領域内に前記半田層を形成したことを特徴とする厚膜多
層セラミックス基板。1. A thick film multilayer ceramic substrate in which a conductor layer is provided on a surface dielectric layer and the conductor layer and the functional component are electrically connected via a solder layer formed on the conductor layer, wherein the conductor layer A thick film multi-layer ceramics substrate, characterized in that a coating layer made of a material that does not wet the solder is provided to cover the conductor layer along the periphery of the solder layer, and the solder layer is formed in a region surrounded by the coating layer.
くとも20μmの幅で該導体層を被覆していることを特
徴とする請求項1記載の厚膜多層セラミックス基板。2. The thick-film multilayer ceramic substrate according to claim 1, wherein the coating layer covers the conductor layer with a width of at least 20 μm from the peripheral edge of the conductor layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3300751A JPH05136565A (en) | 1991-11-15 | 1991-11-15 | Thick-film multilayer ceramic board |
| TW82100089A TW233290B (en) | 1991-11-15 | 1993-01-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3300751A JPH05136565A (en) | 1991-11-15 | 1991-11-15 | Thick-film multilayer ceramic board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05136565A true JPH05136565A (en) | 1993-06-01 |
Family
ID=17888660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3300751A Pending JPH05136565A (en) | 1991-11-15 | 1991-11-15 | Thick-film multilayer ceramic board |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH05136565A (en) |
| TW (1) | TW233290B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001097579A1 (en) * | 2000-06-15 | 2001-12-20 | Murata Manufacturing Co.,Ltd. | Method of mounting electronic part |
| JPWO2017199712A1 (en) * | 2016-05-16 | 2019-02-14 | 株式会社村田製作所 | Ceramic electronic components |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115943128A (en) * | 2020-10-13 | 2023-04-07 | 日本电气硝子株式会社 | Glass for covering semiconductor element and material for covering semiconductor using same |
-
1991
- 1991-11-15 JP JP3300751A patent/JPH05136565A/en active Pending
-
1993
- 1993-01-08 TW TW82100089A patent/TW233290B/zh active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001097579A1 (en) * | 2000-06-15 | 2001-12-20 | Murata Manufacturing Co.,Ltd. | Method of mounting electronic part |
| US6598779B2 (en) | 2000-06-15 | 2003-07-29 | Murata Manufacturing Co., Ltd. | Electronic component mounting method |
| JPWO2017199712A1 (en) * | 2016-05-16 | 2019-02-14 | 株式会社村田製作所 | Ceramic electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| TW233290B (en) | 1994-11-01 |
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