JPH05136312A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the signal transmission speed of a semiconductor device and reduce electrical noise. [Structure] A semiconductor chip 1 having a terminal electrode on an upper surface,
Fingers 11 are attached to the ends bonded to the semiconductor chip 1.
The film wiring board 7 and the metal film wiring 6 of the film wiring board 7 adhered to the semiconductor chip 1 are alloy-bonded to the tips of the inner leads 4 of the lead frame, and the film wiring board 7 is provided. The fingers 11 and the terminal electrodes of the semiconductor chip 1 are alloy-bonded and resin-sealed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a technique effective when applied to a package having a semiconductor chip having a large scale integrated circuit mounted thereon.

[0002]

2. Description of the Related Art Conventionally, in order to protect a semiconductor chip and facilitate mounting on a printed wiring board of an electronic device, the semiconductor chip is mounted on a lead frame having a die pad in the center of each section, There is known a method in which electrodes near the periphery of a semiconductor chip and inner leads of a lead frame are connected with a bonding wire made of gold, resin is sealed, and finally outer leads are processed and formed. According to this conventional method, a space for insulation between the inner lead end portion and the die pad and an extra space considering the mounting position deviation between the semiconductor chip and the die pad are required. There was a limit to the size of the semiconductor chip to be mounted inside. In order to avoid this drawback, a plurality of inner leads extended on the circuit formation surface of the semiconductor chip are bonded with an adhesive with a semiconductor chip and an insulating film interposed, and the inner lead and the semiconductor chip are bonded by a bonding wire. In a semiconductor device electrically connected and sealed with a mold resin, a semiconductor device has been proposed in which a shared inner lead (bus bar inner lead) is provided in the vicinity of a longitudinal centerline of a circuit formation surface of a semiconductor chip ( (See JP-A-61-241959 and JP-A-3-12781). Further, in order to further improve the conventional technique of mounting such a large-sized semiconductor chip, as shown in a perspective view of FIG. 40, an inner lead bonded to the semiconductor chip with an insulating film interposed is used as an insulating film. A semiconductor device in which the shape is processed so that the gap between the semiconductor chip on the outer lead side and the inner lead is larger than the gap between the insulator and the insulator and the area of the insulating film is smaller It is disclosed in Kaihei 2-246125. In the figure, a is a semiconductor chip, b is a resin-sealed package, c is a resin-sealed portion, d is an insulating film, e is a common inner lead, f is an inner lead, g is a bonding wire, and h is an outer lead. is there.

[0003]

In recent years, semiconductor chips,
Especially in the case of semiconductor memory chips, the scale of the memory capacity is increasing at a rate of 4 times in 3 years, and the size of the semiconductor memory chips is increasing at a rate of 1.5 times in 3 years even if the element is miniaturized. I'm doing it. It is becoming more and more difficult to mount a semiconductor chip in a standardized package size against the backdrop of the demand for miniaturization of such elements and larger semiconductor chips. .. Further, since the power supply voltage of the semiconductor device has been lowered for the purpose of ensuring reliability and battery driving, it is difficult to supply a stable power supply voltage to all the circuit formation surfaces of the semiconductor chip. In the case of a semiconductor memory device, when the driving voltage is lowered, the signal transmission speed becomes slower, and a weak memory signal is apt to be erroneously recognized due to electrical noise. Therefore, there is a demand for a semiconductor memory device that avoids the deterioration of these characteristics. Also, due to the diversification of semiconductor devices, especially the word configurations, along with the diversification of electronic devices, the manufacture of packages that can easily configure semiconductor memory devices of various word configurations with the same base semiconductor memory chip. There is a demand for methods. At the same time, as a result of the spread of miniaturized, thinned, and lightweight electronic devices, there is a strong demand for a semiconductor device in which the package has a small space difference from a semiconductor chip and the package is thin. On the other hand, with the increase in size of semiconductor memory devices, the manufacturing cost of semiconductor memory chips increases in proportion to the memory capacity, and the degree of loss for semiconductor manufacturers due to defective semiconductor memory devices is increasing.

Based on these trends, the following various problems can be found when the above-mentioned conventional technique is examined. That is, (1) TSOP (Thin S having a package thickness of 1 mm
mall Outline Package) and even thinner Pape
r In the thin package, when the molding resin is encapsulated in the molding die, the unevenness of the inner leads complicates the flow path of the molding resin. As a result, unfilled resin and voids are likely to occur, and stable moldability cannot be obtained. (2) Since the electrode and the signal inner lead are connected by the bonding wire across the shared inner lead, the bonding wire becomes long, and as a result, a lateral force acts to deform the bonding wire during resin sealing. It's easy to do. (3) Since the inner leads bonded to the insulating film that is in a softened state at high temperature are wire-bonded, ultrasonic vibration is not efficiently applied, and stable bonding cannot be obtained. (4) In order to achieve low impedance, it is necessary to connect with a short bonding wire length, and the inner lead is extended to the center of the semiconductor chip. As a result, there is no room for changing the inner lead position, and the degree of freedom in designing the electrode layout is reduced. (5) Since the power supply voltage potential and the ground potential are supplied from the common inner lead, a stable potential can be applied near the center line in the longitudinal direction of the semiconductor chip, but around the semiconductor chip, especially on the long side. A stable potential, especially a stable ground potential, cannot be applied in the vicinity of since the distance is long, and the signal transmission speed becomes slow and electrical noise easily occurs in these parts. (6) When bonding the insulating film to the lead frame,
Alternatively, the workability when adhering the insulating film to the semiconductor chip is poor, and the productivity is reduced particularly when it is necessary to adhere with high positional accuracy. Also, the quality and reliability are deteriorated due to the damage.

An object of the present invention is to solve various problems as described above and to provide a semiconductor device as described below. (1) A semiconductor device capable of preventing the formation of molding defects. (2) A semiconductor device capable of improving productivity. (3) A semiconductor device that does not lead to deterioration in quality and reliability. (4) A semiconductor device having a high degree of freedom in designing an electrode layout. (5) In order to maximize the electrical characteristics of the semiconductor chip, fluctuations in the power supply voltage potential and the ground potential and a decrease in signal transmission speed and generation of electrical noise due to its impedance, or A semiconductor device capable of improving signal transmission speed and reducing electric noise by eliminating a decrease in signal transmission speed and generation of electrical noise due to a parasitic capacitance between a circuit formation surface and an inner lead.

[0006]

The semiconductor device of the present invention comprises:
The following is a brief description of an outline of a typical one that has solved the problems described above.
The main structure consists of a semiconductor chip having a terminal electrode group on the upper surface, a film-like wiring board bonded to the upper surface of the semiconductor chip, and a lead frame having an inner lead group reaching the circuit formation surface of the semiconductor chip. There is. The details of the film-like wiring board are such that an insulator formed so as to avoid the terminal electrode group on the upper surface of the semiconductor chip, the metal film electrode group provided on at least one surface of the insulating plate, and the metal film electrode group are connected to each other. As described above, the wiring pattern is provided on at least one surface of the insulating plate, and the finger electrode group is provided so as to reach the terminal electrode group of the semiconductor chip from the metal film electrode group. Then, while alloy-bonding the metal film electrode group of the film-shaped wiring board adhered to the semiconductor chip and the tip of the inner lead group of the lead frame,
It is a semiconductor device in which a finger electrode group of a film wiring board and a terminal electrode group of a semiconductor chip are alloy-bonded and then resin-sealed.

[0007]

According to the present invention, the position where the metal film electrode group of the film-shaped wiring board and the tips of the inner lead groups of the lead frame are alloy-bonded by the means as described above is determined by using the film-shaped wiring board. It becomes possible to set it at an arbitrary position, and the tip of the inner lead group will not be brought close to the terminal electrode group. Therefore, the length of the inner lead group applied to the semiconductor chip can be set short, and the unevenness or the step formed by the inner lead group is flattened, so that the turbulence of the resin flow at the time of resin injection can be made small and easy. It is possible to equalize the resin flow speeds in the resin flow paths of the respective parts in the cross section of the resin-sealed package. Alloy bonding of the metal film electrode group of the film wiring board and the tips of the inner lead groups of the lead frame can be performed at once for all electrode groups, and the finger electrode group of the film wiring board and the terminal electrode group of the semiconductor chip can be connected. Alloy joining can also be performed at once for all electrode groups. Using the temperature and pressure required for alloy joining of the finger electrode group of the film-like wiring board and the terminal electrode group of the semiconductor chip, the alloy joining and the alloy joining are simultaneously performed through the adhesive on the back surface of the film-like wiring board. The film-shaped wiring board and the semiconductor chip can be bonded together. The inner lead group of the lead frame and the metal film electrode group of the film-like wiring board are firmly joined by alloy joining, and the film-like wiring board and the semiconductor chip are joined together through the finger electrode group. A strong adhesive force, that is, a large pressure is not required at the time of bonding the wiring board and the semiconductor chip, and the pressure applied to the upper surface of the semiconductor chip is further reduced by the base film of the film wiring board serving as a cushion. .. A wiring pattern is formed on at least one surface of the film-like wiring board that electrically adheres the tip of the inner lead group and the terminal electrode group on the upper surface of the semiconductor chip, and the area of the insulating board is improved by improving the integration degree of this wiring. Since it can be made small, the amount of moisture absorption by the insulator can be reduced. A power supply voltage plane or a ground plane can be arranged by a wiring pattern formed on at least one surface of the film-like wiring board, and a power supply voltage terminal electrode or an arbitrary position is connected through the wiring pattern drawn from the power supply voltage plane or the ground plane. Since it can be connected to the ground terminal electrode, it can supply the power supply voltage potential and the ground potential evenly to every corner of the semiconductor chip, and can reduce the impedance of the power supply voltage system and the ground system transmission line. On the other hand, in the signal line transmission line. Also, since the width of the pattern can be wide and the length can be short, the impedance can be reduced. Since the area of the film-shaped wiring board can be reduced as described above, the area where the wiring pattern and the circuit forming surface of the semiconductor chip face each other is also reduced. As a result, the parasitic capacitance using the insulator as a dielectric can be reduced. Since the plane on which the inner lead group is formed and the plane of the film-like wiring board are different planes in the semiconductor package, the degree of freedom in routing the inner lead group and the degree of freedom in designing the wiring pattern are large. As a result, the degree of freedom in semiconductor circuit design including the circuit design of the semiconductor chip can be increased.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. Regarding the reference numerals given to the embodiments, those having the same function are denoted by the same reference numerals in all the drawings, and the description of the same reference numerals is omitted. FIG. 1 shows a first embodiment of the present invention.
Through 8 will be described. 1 is a partially cutaway perspective view of the resin-sealed semiconductor device of the first embodiment, FIG. 2 is a top view, and FIG. 3 is a sectional view taken along line AA of FIG. In this embodiment, for example, the semiconductor chip 1 has a DRAM (Dynamic Random Acc
ESS Memory semiconductor memory chips are packaged in resin-encapsulated package 2 with SOJ (Small Outline J-bend Package)
The semiconductor chip 1 is sealed in the resin-sealed package 2. 16 semiconductor chips 1 of DRAM
In the example of the Mbit memory, a rectangular flat plate having a thickness of about 0.4 mm is formed, and the width of the resin-sealed package 2 is 400 mil (0.4 inch, about 10 mm).
It has a substantially rectangular parallelepiped shape with a thickness of about 2.5 mm.

In the case of a resin-encapsulated semiconductor device of DRAM, two outer leads 3 are not present in the central portion of the two long sides of the resin-encapsulated package 2. , 24 J-shaped outer leads 3. on the other hand,
In the case of a resin-encapsulated semiconductor device of SRAM (Static Random Access Memory), all the outer leads 3 are required. For example, in the case of a 4 Mbit memory, the total number of J-type outer leads 3 is 32. The terminal numbers of the outer leads 3 are numbered based on the standard, and the signals applied to the outer leads 3 are also determined based on the standard defined for the 16 Mbit DRAM. Figure 1
The left end of the long side on the front side is the 1st terminal, the right end is the 14th terminal, the right end of the long side on the other side is the 15th terminal, and the left end is the 28th terminal. The power supply voltage (Vdd) terminal, the 15th terminal and the 28th terminal are ground (Vss) terminals, and the other terminals are a control terminal, a data input / output terminal and an address signal terminal.

The inner lead 4 engaged with the outer lead 3 is, on the upper part of the semiconductor chip 1, made of, for example, a polyimide resin, and has a low stress property and an insulating property.
It is arranged on the surface of a film wiring board 7 in which a pattern of metal film wiring 6 made of, for example, copper or a copper-based alloy is formed on the surface of a base film 5 of 00 μm. A rectangular opening 8 is formed in the vicinity of the center line in the longitudinal direction of the film wiring board 7, and a finger 11 which is a part of the metal film wiring 6 projects inward from the end face of the opening 8 of the film wiring board 7. It is set up. The size of the film wiring board 7 can be provided up to approximately the same size as the resin-sealed package 2, but here it is approximately the same size as the semiconductor chip 1. The fingers 11 are electrically joined to the protruding electrodes 9 formed on predetermined pad electrodes (not shown) arranged in rows near the center of the semiconductor chip 1 in the longitudinal direction. The protruding electrode 9 is made of, for example, gold and has a thickness of about 50 μm.
It has a height of m. The opening portion 8 is formed so as to surround the periphery of the protruding electrode 9 and has a size of the finger 11.
Any size is acceptable as long as it can be touched by a tool for joining with.
On the other hand, a polyimide resin film 10 having a thickness of about 10 μm is formed on the main surface of the semiconductor chip 1 except for the periphery of the protruding electrode 9, and the polyimide resin film 10 and the back surface of the film wiring board 7 are made of a film. It is adhered by an adhesive layer (not shown) provided on the back surface of the wiring board 7. As the adhesive layer, for example, a polyimide amide resin is used. In the signal transmission path in such a package structure, the signal input from the outer leads 3, 3− is transmitted to the inner leads 4, 4− engaged with the outer leads 3, and the film wiring is performed from the inner leads 4, 4−. It is transmitted to the fingers 11 and 11− through the metal film wirings 6 and 6− of the plate 7, is transmitted from the fingers 11 and 11− to the protruding electrodes 9 and 9−, and is input to the outer leads 3 and 3−. The signal is transmitted to the semiconductor chip 1.

In such a package structure, the inner lead 4 and the semiconductor chip 1 are not on the same plane, and the space margin between the semiconductor chip 1 and the resin-sealed package 2 is because the inner lead 4 is not provided therebetween. , The size of the two members of the semiconductor chip 1 and the resin-sealed package 2 is determined. Therefore, the semiconductor chip 1 that can be mounted in the limited size of the resin-sealed package 2 has the resin-sealed portion 2 that seals the periphery of the semiconductor chip 1.
It is decided by the thickness of the side portion of a.
a can be molded, and the size of the resin-encapsulated package 2 can be infinitely close to the extent that quality and reliability are ensured by the thickness of the side portion of the resin-encapsulated portion 2a. Furthermore, the inner leads 4, 4− are provided in the space above the semiconductor chip 1,
As long as the inner leads 4, 4− do not contact each other within the size of the resin-sealed package 2, that is, within the size of the film wiring board 7, the semiconductor chip 1
It can be freely routed without being restricted by the shape of.
Further, the metal film wirings 6 and 6-on the film wiring board 7 can also be freely routed as long as the metal film wirings 6 and 6-do not short-circuit with each other. Therefore, the degree of freedom in semiconductor circuit design is significantly increased.

Next, a method of assembling the film wiring board, the lead frame and the semiconductor device will be described. FIG. 4A is a top view of the film wiring board 7 used in the first embodiment, and FIG.
6 is a partial cross-sectional perspective view taken along line BB of FIG. 4A, FIG. 5 is a top view of the lead frame 3a used in the first embodiment, and FIG.
Is a top view of a state in which the film wiring board 7, the lead frame 3a and the semiconductor chip 1 used in the first embodiment are assembled, FIG. 7 is an explanatory view showing the assembling method, and FIG. 8 is a flowchart showing the assembling order. .. In the film wiring board 7, for example, a copper metal film is formed on the surface of the base film 5 of the film carrier tape, and the base film 5 and the copper metal film are formed at a predetermined position and a predetermined shape by a chemical etching method. A metal film wiring 6 including a base film 5 and fingers 11 which are processed into a shape to form a film wiring board 7.
The main part is formed by forming. Then, a photosensitive solder resist film 12 is formed so as to cover the base film 5 and the metal film wiring 6, and the solder resist film 12 on the metal film wiring 6 at a position corresponding to the tip portion of the inner lead 4 is opened. A part of the underlying metal film wiring 6 is exposed in a frame shape. That is, the exposed metal film wiring 6 becomes the pattern electrode 13 for electrically connecting to the inner lead 4. On the surfaces of the fingers 11 and the pattern electrodes 13 exposed from the solder resist film 12, for example, a tin plating film is formed. By cutting the base film 5 so that only a necessary portion is taken out from the film carrier tape thus obtained, the film wiring film 7 shown in FIG. 4A is obtained.

The tip portions of the inner leads 4 of the lead frame 3a used in the present invention, which are hatched in FIG. 5, are plated with gold, for example. As mentioned earlier,
The cut film wiring board 7 and the lead frame 3a are bonded by gold-tin alloy bonding the pattern electrode 13 on the film wiring board 7 and the tips of the inner leads 4 to each other.
It is integrated. This gold-tin alloy bonding is performed on all the inner leads 4 at once in the state of the lead frame. Then, in the state of the integrated lead frame, the fingers 11 protruding from the opening 8 of the film wiring board 7 and the protruding electrodes 9 formed on the semiconductor chip 1 are similarly integrated by gold-tin alloy bonding. To be done. The bonding between the fingers 11 and the protruding electrodes 9 may be gang bonding in which all the protruding electrodes 9 are bonded simultaneously, or single point bonding in which each of the protruding electrodes 9 is bonded one by one. Is also good. Then, the back surface of the film wiring board 7 and the semiconductor chip 1 can be bonded to each other through the adhesive layer described above in the same apparatus and in the same operation as the bonding of the fingers 11 and the protruding electrodes 9. This is because both the bonding temperature for gold-tin alloying and the bonding temperature for the adhesive layer are 4
This is because the temperature is almost the same around 00 ° C, and moreover, pressure is required at the same time as heating to obtain bonding and adhesion.

As described above, the film carrier tape having high production efficiency is used for manufacturing the film wiring board 7, and the inner lead 4 of the lead frame 3a and the film wiring board 7 are joined at once. The film wiring board 7 and the protruding electrodes 9 of the semiconductor chip 1 are also joined at one time, and the film wiring board 7 and the semiconductor chip 1 can be joined and the film wiring board 7 and the semiconductor chip 1 can be bonded at the same time. Therefore, the productivity is extremely high. Further, the possibility that the circuit forming surface on the semiconductor chip 1 is damaged by mechanical pressure occurs only when the film wiring board 7 and the semiconductor chip 1 are bonded, but the base film 5 of the film wiring board 7 serves as a cushion. Moreover, since the film wiring board 7 is fixed to the inner leads 4 by alloy bonding, a strong adhesive force (pressurization) is not required and the semiconductor chip 1 is not damaged.

In the film wiring board 7, a pattern electrode joined to the inner leads (Vdd) 4 and 4 engaged with the outer leads (Vdd terminals) 3 of the first and 14th terminals of the outer leads 3 and 3. (Vdd) 1
3, 13 are located at both ends of the pattern electrode row on one side,
The pattern electrodes (Vdd) 13, 13 are connected by a pattern of a power supply voltage plane 14 formed of a metal wiring film 6 integrally formed. The power supply voltage plane 14 is formed on the long-side peripheral portion of the film wiring board 7 so as to surround the pattern electrode rows except the pattern electrodes (Vdd) 13 at both ends. At the same time, the pattern electrode (Vdd) 1
From 3 and 13, the lead pattern (Vdd) 15 composed of the metal wiring 6 is stretched in the opening direction of the film wiring board 7, and the lead pattern 15 projecting in the opening 8 as it is is the finger (Vdd) supplying the power supply voltage. ) 11 is formed, the lead pattern (Vdd) 15 is branched before the opening 8 in order to reduce the impedance of the lead pattern (Vdd) 15 that reduces the signal transmission speed. Further, a plurality of lead patterns (Vdd) 15 are drawn not only from the pattern electrodes (Vdd) 13 at both ends but also from the power supply voltage plane 14 from any desired position and branched through between the pattern electrodes 13. Meanwhile, the finger (Vdd) 11 is formed at an arbitrary position. The larger the area of the power supply voltage plane 14, the better, and the thicker and shorter the lead pattern (Vdd) 15, the better.

Similarly, the pattern electrodes (Vs) joined to the inner leads (Vss) 4 and 4 engaged with the outer leads (Vss terminals) 3 of the 15th and 28th terminals.
s) 13 and 13 are connected by a ground plane 16, and a plurality of lead patterns (Vss) are drawn out not only from the pattern electrodes (Vss) 13 and 13 but also from any position of the ground plane 16 and at the tip thereof. Has a finger (Vss) 11. Like the power supply voltage plane 14, the larger the area of the ground plane 16, the better, and the thicker and shorter the lead pattern (Vss) 15 is, the better. As a result, it is possible to stably supply the power supply voltage potential and the ground potential evenly to every corner of the semiconductor chip 1, and to reduce the impedance of the power supply voltage system and the ground system of the semiconductor chip 1 so that a plurality of impedances are provided. The power supply voltage (Vdd) protruding electrode and the ground (Vss) protruding electrode can be formed at arbitrary positions on the semiconductor chip 1. At the same time, between the power supply voltage (Vdd) protruding electrode and the inner lead (Vdd) 4 formed in this way, and between the ground (Vss) protruding electrode and the inner lead (Vd).
ss) 4 are connected by a power supply voltage plane 14 and a ground plane 16, respectively, so that electrical noise, particularly power supply noise in the signal transmission path of the resin-sealed package 2 can be absorbed and the impedance can be lowered. So
The operation speed of the semiconductor chip 1 can be increased and the deviation of the data input / output speed can be suppressed.

On the other hand, the inner leads 4, 4-engaged with the outer leads 3, 3-other than the outer leads 3, 14, 15, 15 and 28 are the pattern electrodes 13 of the film wiring board 7, It is joined to 13-. The tip positions of these inner leads 4, 4− are the pattern electrodes 13,
Although it is determined by the position of 13-, the pattern electrodes 13 do not need to form a row, and therefore it is not necessary to align the tip positions and shapes of the inner leads 4, 4-.
Also, from the pattern electrodes 13 and 13 to the film wiring board 7
Lead patterns 15 and 15 that are extended in the opening direction of the
Is connected to a predetermined protruding electrode 9, but since these lead patterns 15 can be freely routed on the film wiring board 7, the position of the protruding electrode 9 can be easily changed. The lead patterns 15 and 15-- are semiconductor chips 1
Lead pattern 1 so that the operating speed of
It is preferable that the width of the lead pattern 15 is as wide as possible, and the length of the lead pattern 15, especially the length of the lead pattern 15 having the same width as the thin finger 11 is as short as possible.

Next, the resin moldability of the resin-sealed package will be described. As described above, the lead frame 3a, the film wiring board 7, and the semiconductor chip 1 are integrated into a member in the lead frame state. The member in the lead frame state is set in a mold and a resin sealing material is injected. The injection direction is from the lead frame 3a surface at the center of the short side of the resin sealing package 2 to the long side direction. .. As can be seen from FIGS. 3 and 6, the resin flow path in the mold is divided into a total of four flow paths including the upper surface portion, the lower surface portion, and the side surface portions (two locations) of the semiconductor chip 1. Since the length applied to the upper surface of the chip is short, the turbulence of the resin flow due to the unevenness of the wall surface of the channel is small, and the resin flow velocity in the four channels can be defined by the cross-sectional areas of the four channels. Then, it is necessary to equalize the resin flow velocity in each flow path in order to prevent resin unfilling and voids, but it is easy to set the dimensions of the package and each member that configure the resin flow path. Since the cross-sectional areas of the resin flow paths can be made equal and, as a result, the resin flow rates can be made equal, it is possible to prevent unfilling of resin and voids. In addition, TSOP with a thickness of 1 mm and even thinner Paper Thin Packa
Even in the case of ge, similarly, the turbulence of the resin flow due to the unevenness of the resin flow path is small, so that the resin flow velocities in the four flow paths can be easily equalized, and resin unfilling and voids can be prevented. It can be prevented.

FIG. 9 is a top view showing a state in which the film wiring board 7, the lead frame 3a and the semiconductor chip 1 according to the first modification of the first embodiment are assembled. In FIG. 9, the size of the film wiring board 7 is set to be substantially the same as the size of the resin-sealed package 2, for example, and the pattern electrodes (Vdd) joined to the outer leads (Vdd) 3 and 3 of the 1st and 14th terminals. 13 and 13 are formed, and power supply voltage planes 14 and 14 that are separated from the respective pattern electrodes (Vdd) 13 and 13 are formed. Similarly, regarding the pattern electrodes (Vss) 13 and 13 joined to the outer leads (Vss) 3 and 3 of the 15th and 28th terminals,
The ground planes 16 and 16 which are separated from each other are formed. Thus, the power supply voltage plane 14 and the ground plane 16
Are formed independently of each other with respect to the pattern electrode 13,
An example is shown in which a plurality of lead patterns (Vdd) 15, 15-, and lead patterns (Vss) 15, 15- are formed from the power supply voltage plane 14 and the ground plane 16. The figure also shows that the inner leads 4 can be freely arranged on the film wiring board 7.

FIGS. 10 and 11 show the second embodiment of the first embodiment.
9A and 9B are plan views of a lead frame of a third modified example.
FIG. 10 shows two dummy inner leads 17 having no potential applied to the lead frame 3a in the vicinity of the center line in the long side direction of the resin-sealed package 2 at an interval that does not hinder the joining of the protruding electrode 9 and the finger 11. 11 is an example in which dummy inner leads 18 having no potential are arranged on both sides of the short side of the resin-sealed package 2 in the lead frame 3a. By bonding and fixing the upper surface of the film wiring board 7 with the dummy inner leads 17 or the dummy inner leads 18 in this manner, the inner leads 4, 4− and the dummy inner leads 17, so as to surround the opening 8 of the film wiring board 7, 17
Alternatively, 18, 18 are firmly fixed to the film wiring board 7. Inner lead 4 and dummy inner lead 1
Since 7 or 18 is formed on the lead frame 3a, the inner lead 4 and the dummy inner lead 1 are formed.
7 or 18 forms the same plane, and the film wiring board 7 bonded to the dummy inner leads 17 or 18 has a plane without twist. As a result, the flatness formed by the fingers 11 of the film wiring board 7 is formed to be a stable and uniform flat surface. Therefore, by disposing the dummy inner leads 17 or 18, the mechanical strength of the resin-sealed package 2 can be increased, and the protrusion electrodes 9 and the fingers 11 can be joined stably.

FIG. 12 is a flow chart showing another assembling order of the first embodiment, showing that the processing order of lead bonding and electrode bonding can be replaced with that described in the first embodiment. Here is an example. This assembling method is exactly the same as that of the first embodiment except that the conventional inner lead bonder can also be used.

A second embodiment of the present invention is shown in FIG. 13 and FIG.
It will be explained based on 4. FIG. 13 is a sectional view of the resin-sealed semiconductor device of the second embodiment, and FIG. 14 is a top view of the film wiring board 7, the lead frame 3a and the semiconductor chip 1 of the second embodiment assembled. In this embodiment, the fingers 11 protruding from the end face of the opening 8 of the film wiring board 7 are joined to the protruding electrodes 9 of the semiconductor chip 1 and the film wiring board 7 and the polyimide resin film 10 on the semiconductor chip 1 are bonded together. After performing the above step, a potting resin 20 made of an epoxy resin having the same elastic modulus as the resin of the transfer mold forming the resin sealing portion 2a of the package and having a low stress is injected into the inner recess of the opening 8. By doing so, the fingers 11 and the protruding electrodes 9 in the openings 8 are covered with the potting resin 20. By covering the opening 8 with the potting resin 20, the potting resin 20 functions as a buffer for shrinkage stress even when exposed to an environmental test such as a temperature cycle, and the gap between the semiconductor chip 1 and the resin sealing portion 2a is increased. Due to the relative thermal deformation caused by the difference in the coefficient of thermal expansion, the fingers 11 and the protruding electrodes 9
Repeated deformation occurring in the joint and its joint can be avoided, and disconnection due to metal fatigue is eliminated. Further, since the opening 8 is filled with the potting resin 20 and the unevenness of the surface of the film wiring board 7 is eliminated, the disturbance of the flow of the resin molding the resin sealing portion 2a is eliminated, and the resin unfilling and voids are prevented. There is also an effect that can be done.

A third embodiment of the present invention is shown in FIG. 15 and FIG.
An explanation will be given based on 6. FIG. 15 is a top view of the lead frame 3a used in the third embodiment, and FIG. 16 is a sectional view of the resin-sealed semiconductor device in the third embodiment. Inner leads 4, 4 of the resin-sealed semiconductor device of this embodiment
Of the surface of the semiconductor chip 1 facing the circuit formation surface,
Half-etching is performed between the long-side end surface of the resin-encapsulated package 2 shown in FIG. 15 and the side surface of the semiconductor chip 1 to the tips of the inner leads 4, 4 to reduce the thickness of the outer leads 3, 3. It is formed as thin as about 1/2 of the thickness. And these inner leads 4, 4-
Tip of the film and the pattern electrodes 13 and 13 of the film wiring board 7
And are alloy-bonded. As a result, the distance from the upper surface of the inner leads 4, 4-to the bottom surface of the semiconductor chip 1 becomes smaller, and the film wiring board 7 and the inner leads 4, which induce the turbulence of the resin flow when the resin is injected,
Since the concavities and convexities formed by 4-are small, the resin flowing speeds in the resin flow paths can be easily made equal, and it is possible to prevent unfilling and voids of the resin. This effect becomes more effective as the thickness of the resin-sealed package 2 becomes thinner. Particularly, the TSOP having a package thickness of 1 mm and a thinner Pa than this.
It is effective for par Thin Package.

A fourth embodiment of the present invention is shown in FIGS.
It will be explained based on 9. 17 is a top view of the lead frame 3a used in the fourth embodiment, FIG. 18 is a cross-sectional view of the resin-sealed semiconductor device of the fourth embodiment, and FIG. 19 is an inner lead showing the main part of the lead frame 3a. It is a perspective view of the front-end | tip part of FIG. In this embodiment, the inner lead 4 is thinly etched by half-etching from the tip of the inner lead 4 to the outer peripheral portion of the semiconductor chip 1,
This is an example in which the protrusion 25 is formed on the thin inner lead 4 by thermocompressing and flattening the gold ball portion of gold wire bonding.

A fifth embodiment of the present invention is shown in FIGS.
It will be explained based on 4. 20 is a top view of the lead frame 3a used in the fifth embodiment, FIG. 21 is a sectional view of the resin-sealed semiconductor device of the fifth embodiment, and FIG. 22 is an inner lead showing a main part of the lead frame 3a. 4 is a perspective view showing the tip end portion of FIG. 4, FIG. 23 is a top view showing a state where the film wiring board 7, the lead frame 3a and the semiconductor chip 1 of the fifth embodiment are assembled, and FIG. 24 is an explanatory view showing the assembling method. .. In this embodiment, the semiconductor chip 1 and the lead frame 3a
Film wiring board 7 installed between inner leads 4 of
An insulating film having a dielectric property and a hygroscopic property, for example, a polyimide resin is used for the base film 5, and the size of the base film 5 is smaller than that of the semiconductor chip 1. As already explained, the film wiring board 7 is
Power supply voltage plane 14, ground plane 16, pattern electrode 13, lead pattern 1 formed of metal film wiring 6 on the surface
5, the opening 8 and the finger 11 are configured. By making the size of the base film 5 smaller than the size of the semiconductor chip 1 within the range of this configuration, the volume of the base film 5 becomes smaller and the amount of moisture absorbed by the base film 5 can be reduced. ..

On the other hand, in the case of surface mount type packages such as SOJ and TSOP, the aforesaid moisture absorption is vaporized and expanded by the rapid heating applied by the reflow device applied during the surface mounting on the printed wiring board, and the resin sealing portion of the package. A crack may occur in 2a, which may deteriorate the moisture resistance and the bondability of the protruding electrode portion. Therefore, since the moisture absorption amount can be reduced by the fifth embodiment, it is possible to prevent the crack of the package in the surface mounting using the solder reflow method. Further, as a result of reducing the size of the film wiring board 7, the length of the lead pattern 15 on the film wiring board 7 is also shortened, so that the area of the lead pattern 15 is also reduced and the lead pattern 15 and the circuit formation surface on the semiconductor chip 1 are also reduced. The parasitic capacitance of the base film 5 formed of the above as a dielectric is also reduced, and the signal transmission speed of the semiconductor chip 1 can be improved.

On the other hand, the inner leads 4 and 4− of the lead frame 3a are excluding the end portions of the inner leads 4 and 4− to the middle portion between the end face on the long side of the resin-sealed package 2 and the side face of the semiconductor chip 1. Is half-etched to a thickness of about 1/2 of the thickness of the inner leads 4, 4− and the outer leads 3, 3−. ,
25- are formed. The protrusions 25, 25-function as joint terminals with the pattern electrodes 13, 13- on the film wiring board 7. Furthermore, since such an inner lead shape forms a space between the inner lead 4 and the circuit formation surface on the semiconductor chip 1,
The parasitic capacitance using the resin sealing portion 2a formed of the inner lead 4 and the circuit forming surface of the semiconductor chip 1 as a dielectric also becomes small, which is also effective in improving the signal transmission speed of the semiconductor chip 1. In this embodiment, a polyimide resin film is used as the base film 5, but a fluorine-based resin having a lower dielectric constant than this can be used, and the parasitic capacitance can be further reduced.

A sixth embodiment of the present invention will be described with reference to FIGS. 25 and 26. FIG. 25 is a cross-sectional view of the resin-sealed semiconductor device of the sixth embodiment, and FIG. 26 is a top view of the film wiring board 7, lead frame 3a and semiconductor chip 1 of the sixth embodiment assembled. In this embodiment, the lead frame 3a described in the fifth embodiment is provided with the semiconductor chip 1 and the film wiring board 7 described in the first embodiment.
By bonding a rectangular fluororesin film 26 having the same thickness as the space between the inner lead 4 and the film wiring board 7 generated by the half etching of the package structure in which the inner lead 4 and the semiconductor are bonded together, This has the effect of reducing the parasitic capacitance induced from the circuit forming surface of the chip 1.

The seventh embodiment of the present invention is shown in FIGS.
It will be explained based on 9. FIG. 27 is a top view of the lead frame 3a used in the seventh embodiment, FIG. 28 is a sectional view of the resin-sealed semiconductor device of the seventh embodiment, and FIG. 29 is an inner lead showing a main part of the lead frame 3a. It is a perspective view of the front-end | tip part of FIG. The inner lead 4 of the lead frame 3a of the present embodiment is the semiconductor chip 1 from the tip of the inner lead 4.
By the first half-etching, the area up to the outer side is thinned to about 2/3 of the thickness of the lead frame.
The portion of the half-etched portion except the tip portion of the inner lead 4 is thinned to about 1/3 of the thickness of the lead frame by the second half-etching. As a result, the protrusion 25 is formed at the tip of the inner lead,
The thickness is about 2/3 of the thickness of the lead frame,
The thickness from the upper surface of the inner lead 4 to the bottom surface of the semiconductor chip 1 can be reduced. By doing this, TS
It is effective in preventing resin non-filling and voids in thin packages such as OP and Paper Thin Pockage.

The eighth embodiment of the present invention is shown in FIGS.
It will be explained based on 1. FIG. 30 is a sectional view of the resin-sealed semiconductor device of the eighth embodiment, and FIG. 31 is a top view showing a state in which the film wiring board 7, the lead frame 3a and the semiconductor chip 1 of the eighth embodiment are assembled. In this embodiment, an insulating rod-shaped member 19 formed integrally with the base film 5 of the film wiring board 7 is formed at the center line portion of the opening 8 of the film wiring board 7 in the long side direction, and the surface of the film wiring board 7 is formed. The tips of the fingers 11 that are engaged with the lead pattern 15 formed in the above are extended to the ends of the insulating rod-shaped member 19. The base film 5 below the finger 11 is removed between the opening 8 and the insulating rod-shaped member 19, and the finger 11 and the semiconductor chip 1 are connected to the protruding electrode 9 at this portion.
It is electrically connected via. Like this one finger
By adhering the tip portion of 1 to the insulating rod-shaped member 19,
Since the fingers 11 are fixed to the base film 5, the fingers 11 can maintain a high positional accuracy without being deformed even when an external force is applied to the fingers 11, so that the fingers 11 and the projections when the projection electrodes 9 are joined are The positioning accuracy with the electrode 9 is improved, and the reliability and workability of joining can be improved.

A ninth embodiment of the present invention is shown in FIGS. 32 and 3.
It will be explained based on 3. 32 is a cross-sectional view of the resin-sealed semiconductor device of the ninth embodiment, and FIG. 33 is a top view of the film wiring board 7, lead frame 3a and semiconductor chip 1 of the ninth embodiment assembled. In this embodiment, the metal film wiring 6 is formed on both surfaces of the film wiring board 7. The metal film wiring 6 formed on the surface of the film wiring board 7 opposite to the bonding surface (front surface) with the inner leads 4 is composed of a power supply voltage plane 14 and a ground plane 16 formed so as to surround the power supply voltage plane 14. The ground plane 16 covers most of the back surface of the film wiring board 7. Further, the base film 5 of the film wiring board 7 has holes for forming the through holes 27. The metal film wiring 6 formed on the joint surface of the film wiring board 7 with the inner lead 4 is integrally formed with the finger 11 for joining the pattern electrode 13 for joining with the inner lead 4 and the protruding electrode 9. Lead pattern 15
And the lead pattern 15 formed integrally with the through hole 27 and the finger 11. In addition,
Photosensitive solder resist films 12 are formed on both surfaces of the film wiring board 7 except for the pattern electrodes 13.

The supply path of the power supply voltage (Vdd) will be described below. The outer lead (Vd) of the first terminal
d) The power supply voltage (Vdd) conducted to the inner leads (Vdd) 4 and 4 engaged with the outer leads (Vdd) 3 of terminals 3 and 14 is the pattern electrode (Vdd) 13 and 1.
One of the patterns following the pattern electrode (Vdd) 13 and 13 via the direct lead pattern (Vd)
d) 15 is supplied to the fingers (Vdd) 11 and 11, the other is supplied to the power supply voltage plane 14 on the back surface through the through hole 27, and further through the through hole 27 formed at an arbitrary position. Then, it is supplied to a large number of other lead patterns (Vdd) 15 on the surface and subsequent fingers (Vdd) 11. Ground (Vs
s) The same applies to the potential conduction path. As a result, the power supply voltage plane 14 and the ground plane 16 can secure an area capable of achieving a sufficiently low impedance even for the film wiring board 7 having a small area, and the power supply voltage potential and the potential can be set at arbitrary positions of the semiconductor chip 1. Since the ground potential can be supplied, electrical noise, especially power source noise, in the signal transmission path is absorbed, and as a result, the signal transmission speed of the semiconductor chip 1 is increased, the deviation of the data input / output speed is suppressed, and the memory malfunction is prevented. it can.

Furthermore, since the lead pattern 15 can be arranged short and efficiently on the film wiring board 7 having a small area,
The parasitic capacitance induced from the lead pattern 15 and the circuit forming surface of the semiconductor chip 1 can be reduced. In addition, parasitic capacitance induced from the lead pattern 15 inside the film wiring board 7 and the circuit forming surface of the semiconductor chip 1 and the inner lead 4 and the circuit forming surface of the semiconductor chip 1, and the parasitic capacitance generated from the lead pattern 15 and the inner lead 4. The generated electric field or magnetic field is reduced or blocked by the ground plane 16 formed on the main portion of the back surface of the film wiring board 7. Further, on the outside of the film wiring board 7, the parasitic capacitance induced by the inner leads 4 and the circuit forming surface of the semiconductor chip 1 also has a resin sealing material corresponding to the thickness of the base film 5. Will be reduced. Film wiring board 7
Since the area of the base film 5 is small, the amount of moisture absorbed can be reduced, so that the generation of cracks in the package can be prevented. Further, the power supply voltage plane 14 and the ground plane 16 on the back surface of the film wiring board 7 are the resin sealing portion 2
It has the effect of blocking the light that passes through a and has a thickness of 1 mm
It is effective for thin packages such as OP and Paper Thin Package.

A tenth embodiment of the present invention will be described with reference to FIGS. 34 and 35. 34 is a top view of the lead frame 3a used in the tenth embodiment, and FIG. 35 is a partially cutaway perspective view of the resin-sealed semiconductor device of the tenth embodiment. In this embodiment, two dummy rod-shaped inner leads are provided on the lead frame 3a in the vicinity of the center line in the long side direction of the resin-sealed package 2 at a distance that does not hinder the joining of the protruding electrode 9 and the finger 11. 21 is provided,
No. 1 terminal on both ends of the rod-shaped inner leads 21, 21
The trapezoidal inner leads 22 and 22 are provided in accordance with the lead-out shapes of the inner leads 4, 4, 4 and 4 of the No. 15 terminal, the No. 15 terminal and the No. 28 terminal. Square outer leads 23, 23 shown by hatching are provided. In the resin-encapsulated semiconductor device of the present embodiment, the rectangular outer leads 23, 23 are bent above the resin-encapsulated package 2, and further inward at the short side ridge lines on the upper surface of the resin-encapsulated package 2, It is processed into the inverted L-shaped outer leads 24, 24. By doing so, the inner leads 4, 4−, the rod-shaped inner leads 21, 21 and the trapezoidal inner leads 22, 22 cover the entire upper surface of the circuit forming surface which is the heat source of the semiconductor chip 1, and the semiconductor chip The heat generated in 1 is uniformly radiated through the outer leads 3, 3− and the inverted L-shaped outer leads 24, 24 into the atmosphere or the mounted substrate over the entire surface of the semiconductor chip 1. Especially the inverted L-shaped outer lead 2
Since 4 and 24 increase the heat radiation effect to the atmosphere, the larger the size of the inverted L-shaped outer leads 24 and 24 is, the higher the effect is. The heat dissipation effect is further improved by extending the character-shaped outer leads 24, 24. As a result, the heat dissipation effect of the resin-sealed package 2 is improved, the data retention characteristics of the semiconductor chip 1, especially the semiconductor memory chip (DRAM) under high temperature are improved, and at the same time, the signal transmission speed under high temperature can be improved. it can. The rod-shaped inner lead 21 and the trapezoidal inner lead 22 function as a skeleton of the resin-sealed package 2 and also have an effect of increasing mechanical strength. If the inner leads 4 have a gap, the rectangular outer leads 23, 23 may be formed in the resin-sealed package 2
Needless to say, the bent shape may be an inverted L-shape or a J-bend shape.

An eleventh embodiment of the present invention will be described with reference to FIGS. 36 and 37. FIG. 36 is a sectional view of the resin-sealed semiconductor device of the eleventh embodiment, and FIG. 37 is a top view of the film wiring board 7, lead frame 3a and semiconductor chip 1 of the eleventh embodiment assembled together. In this embodiment, the protruding electrodes 9 formed on the semiconductor chip 1 are formed on the peripheral portion of the semiconductor chip 1. Therefore, the fingers 11 formed on the film wiring board 7 are provided so as to project from the outer peripheral edge of the film wiring board 7. Further, the opening 8 formed in the vicinity of the center line in the long side direction of the film wiring board 7 reduces the size of the dielectric and hygroscopic base film 5 as described in Example 6 to reduce the package size. It is provided to prevent the occurrence of cracks. Further, since the pattern electrodes 13 and 13-can be formed in the vicinity of the outer peripheral edge of the film wiring board, the lengths of the inner leads 4 and 4- and the lead patterns 15 and 15-can be shortened, and the inner leads 4 and 4- can be shortened. ─ and lead pattern 1
It is possible to reduce the facing area between 5, 15 and the circuit forming surface of the semiconductor chip 1. As a result, it is possible to reduce the impedance and parasitic capacitance in the inner leads 4, 4-and the lead patterns 15, 15-, and improve the signal transmission speed of the semiconductor chip 1. The assembling method of this embodiment is performed according to the flowchart of the assembling order of FIG. 12 shown in the first embodiment.

A twelfth embodiment of the present invention will be described with reference to FIGS. 38 and 39. FIG. 38 is a sectional view of the resin-sealed semiconductor device of the twelfth embodiment, and FIG. 39 is a top view showing a state in which the film wiring board 7, lead frame 3a and semiconductor chip 1 of the twelfth embodiment are assembled. In the present embodiment, the film wiring board 7 in which the metal film wirings 6 are formed on both surfaces and the front and back metal film wirings 6 are electrically connected by the through holes 27.
By using, the semiconductor device can be configured even if the protruding electrode 9 is formed in the vicinity of the center of the semiconductor chip 1 and in the peripheral portion. As described above, in the example of the present invention, by adopting either of the assembling order shown in FIG. 8 or FIG. 12, even in the semiconductor chip 1 in which the electrodes are arranged in the vicinity of the center line in the long side direction of the semiconductor chip 1, It can also be applied to the semiconductor chip 1 in which electrodes are arranged on the peripheral portion of the semiconductor chip 1.

[0037]

The effects obtained by the present invention will be briefly described as follows. (1) It is possible to improve moldability and prevent the occurrence of molding defects such as unfilled resin and voids. (2) The productivity related to joining can be improved. (3) It is possible to prevent damages and scratches on the circuit forming surface of the semiconductor chip, and improve the quality and reliability of the semiconductor device. (4) It is possible to prevent cracks in the package that occur during reflow. (5) It is possible to improve the signal transmission speed and reduce electrical noise. (6) The heat dissipation can be improved. (7) The reliability of the electrical connection can be ensured. (8) The degree of freedom in designing a semiconductor chip can be increased.

[Brief description of drawings]

FIG. 1 is a partially cutaway perspective view of a resin-sealed semiconductor device according to a first embodiment.

FIG. 2 is a top view of the resin-sealed semiconductor device according to the first embodiment.

3 is a sectional view taken along line AA of FIG.

FIG. 4 is a film wiring board used in the first embodiment, in which A is a top view and B is a partial cross-sectional perspective view taken along line BB.

FIG. 5 is a top view of the lead frame used in the first embodiment.

FIG. 6 is a top view of the film wiring board, the lead frame and the semiconductor chip of the first embodiment in an assembled state.

FIG. 7 is an explanatory view showing the assembling method of the first embodiment.

FIG. 8 is a flowchart showing an assembling sequence of the first embodiment.

FIG. 9 is a top view showing a state in which a film wiring board, a lead frame and a semiconductor chip according to a first modification of the first embodiment are assembled.

FIG. 10 is a plan view of a lead frame of a second modified example of the first embodiment.

FIG. 11 is a plan view of a lead frame of a third modified example of the first embodiment.

FIG. 12 is a flowchart showing another assembling order of the first embodiment.

FIG. 13 is a sectional view of a resin-sealed semiconductor device of a second embodiment.

FIG. 14 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the second embodiment are assembled.

FIG. 15 is a top view of the lead frame used in the third embodiment.

FIG. 16 is a sectional view of a resin-sealed semiconductor device of a third embodiment.

FIG. 17 is a top view of the lead frame used in the fourth embodiment.

FIG. 18 is a cross-sectional view of a resin-sealed semiconductor device according to a fourth embodiment.

FIG. 19 is a perspective view of a tip portion of an inner lead showing a main portion of a lead frame of a fourth embodiment.

FIG. 20 is a top view of the lead frame used in the fifth embodiment.

FIG. 21 is a cross-sectional view of a resin-sealed semiconductor device according to a fifth embodiment.

FIG. 22 is a perspective view of a tip portion of an inner lead showing a main portion of a lead frame of a fifth embodiment.

FIG. 23 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the fifth embodiment are assembled.

FIG. 24 is an explanatory view showing the assembling method of the fifth embodiment.

FIG. 25 is a sectional view of a resin-sealed semiconductor device of a sixth embodiment.

FIG. 26 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the sixth embodiment are assembled.

FIG. 27 is a top view of the lead frame used in the seventh embodiment.

FIG. 28 is a cross-sectional view of the resin-sealed semiconductor device of the seventh embodiment.

FIG. 29 is a perspective view of a tip portion of an inner lead showing a main portion of a lead frame of a seventh embodiment.

FIG. 30 is a cross-sectional view of the resin-sealed semiconductor device of the eighth embodiment.

FIG. 31 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the eighth embodiment are assembled.

FIG. 32 is a cross-sectional view of the resin-sealed semiconductor device of the ninth embodiment.

FIG. 33 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the ninth embodiment are assembled.

FIG. 34 is a top view of the lead frame used in the tenth embodiment.

FIG. 35 is a partially cutaway perspective view of the resin-sealed semiconductor device of the tenth embodiment.

FIG. 36 is a sectional view of the resin-sealed semiconductor device of the eleventh embodiment.

FIG. 37 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the eleventh embodiment are assembled.

FIG. 38 is a sectional view of the resin-sealed semiconductor device of the twelfth embodiment.

FIG. 39 is a top view showing a state where the film wiring board, the lead frame and the semiconductor chip of the twelfth embodiment are assembled.

FIG. 40 is a perspective view of a conventional example.

[Explanation of symbols]

 1 Semiconductor Chip 2 Resin Sealing Package 3 Outer Lead 4 Inner Lead 5 Base Film 6 Metal Film Wiring 7 Film Wiring Board 8 Opening 9 Projection Electrode 10 Polyimide Resin Film 11 Finger 12 Photosensitive Solder Resist Film 13 Pattern Electrode 14 Ground Plane 15 Lead pattern 16 Power supply voltage plane 17 Dummy inner lead 18 Dummy inner lead 19 Insulating rod-shaped member 20 Potting resin 21 Rod-shaped inner lead 22 Trapezoidal inner lead 23 Square outer lead 24 Reversed L-shaped outer lead 25 Protrusion 26 Fluorine resin film 27 Through hole

Claims (15)

[Claims] 1. A semiconductor chip having a terminal electrode group in the central portion, a lead frame having an inner lead group reaching the circuit formation surface of the semiconductor chip, and an opening provided in the central portion avoiding the terminal electrode group. A metal film electrode group is formed on at least one surface of the insulator, and a part of the metal film electrode group is connected or a wiring pattern extended from the metal film electrode group is formed. A film-shaped wiring board having a finger electrode group reaching up to, the metal film electrode group provided on the upper surface of the film-shaped wiring board and the tip of the inner lead group of the lead frame are alloy-bonded, and the semiconductor The film-shaped wiring board is adhered to the upper surface of the chip, the finger electrode group and the terminal electrode group are alloy-bonded, and resin-sealed. Conductor device. 2. The semiconductor device according to claim 1, wherein the wiring pattern is provided independently of each of the metal film electrode groups. 3. The semiconductor according to claim 1, wherein a dummy inner lead is provided over the entire surface of the semiconductor chip between the terminal electrode group and the tip of the inner lead group on the upper surface of the semiconductor chip. apparatus. 4. The semiconductor device according to claim 3, wherein the dummy inner lead is provided in a peripheral portion of the semiconductor chip. 5. The semiconductor device according to claim 1, wherein the opening is sealed by filling the opening with potting resin, and the terminal electrode group and the finger electrode group are covered and resin-sealed. 6. The semiconductor device according to claim 1, wherein a lower surface of a portion of the inner lead group that overlaps an upper portion of the semiconductor chip is removed. 7. The semiconductor device according to claim 1, wherein a lower surface of a portion of the inner lead group that overlaps with an upper portion of the semiconductor chip is removed, and a metal bump is provided at a tip end portion of the inner lead group. 8. The semiconductor device according to claim 1, wherein a lower surface of a portion of the inner lead group which overlaps with an upper portion of the semiconductor chip is removed while leaving a tip portion of the inner lead group. 9. The semiconductor device according to claim 8, wherein an insulating member is bonded to a lower surface of a portion of the inner lead group that overlaps with an upper portion of the semiconductor chip. 10. A semiconductor chip having a terminal electrode group in the central portion, a lead frame having an inner lead group reaching the circuit forming surface of the semiconductor chip, and a bridge-shaped member avoiding the terminal electrode group in the central portion. A wiring pattern in which a metal film electrode group is formed on at least one surface of an insulator having two openings on both sides of the bridge-shaped member, and a part of the metal film electrode group is connected or extended from the metal film electrode group. And a film-shaped wiring board having a finger electrode group reaching from the metal film electrode group to the bridge-shaped member, and the metal film electrode group and the lead frame provided on the upper surface of the wiring board. While alloy-bonding the tip of the inner lead group, bonding the film-shaped wiring board to the upper surface of the semiconductor chip, bonding the finger electrode group to the bridge-shaped member In addition, the semiconductor device is characterized by being alloy-bonded to the terminal electrode group and resin-sealed. 11. A semiconductor chip having a terminal electrode group in the central portion, a lead frame having an inner lead group reaching the circuit forming surface of the semiconductor chip, and an opening provided in the central portion avoiding the terminal electrode group. A metal film electrode group is formed on the upper surface of the insulator, a wiring pattern is formed on the lower surface of the insulator to connect with a part of the metal film electrode group by a through hole, and the metal film electrode group is extended from the metal film electrode group. A film-like wiring board having a wiring pattern and having finger electrode groups reaching the openings from the metal film electrode group, wherein the metal film electrode group and the lead frame provided on the upper surface of the film-like wiring board The tip of the inner lead group is alloy-bonded, and the film-like wiring board is adhered to the upper surface of the semiconductor chip, the finger electrode group and the terminal electrode group. A semiconductor device in which the above are alloy-bonded and resin-sealed. 12. A semiconductor chip having a terminal electrode group in the center, a lead frame having an inner lead group reaching the circuit formation surface of the semiconductor chip, and an opening provided in the center avoiding the terminal electrode group. A metal film electrode group is formed on at least one surface of the insulator, and a part of the metal film electrode group is connected or a wiring pattern extended from the metal film electrode group is formed. A film-shaped wiring board having a finger electrode group reaching to, a flat dummy lead frame provided so as to avoid the inner lead group and the opening is provided above the circuit forming surface of the semiconductor chip, The metal film electrode group provided on the upper surface of the film-like wiring board and the tips of the inner lead groups of the lead frame are alloyed and The film-shaped wiring board is adhered to the upper surface of the semiconductor chip, the finger electrode group and the terminal electrode group are alloy-bonded, resin-sealed, and a part of the dummy lead frame extended from the end of the resin sealing member is attached. A semiconductor device having. 13. A semiconductor chip having a terminal electrode group in a peripheral portion, a lead frame having an inner lead group reaching the circuit formation surface of the semiconductor chip, and a width not reaching the terminal electrode group in the peripheral portion. A metal film electrode group is formed on at least one surface of a set insulator, and a part of the metal film electrode group is connected or a wiring pattern extended from the metal film electrode group is formed. A film-shaped wiring board having a finger electrode group reaching from the periphery to a peripheral portion, and the metal film electrode group provided on the upper surface of the film-shaped wiring board and the tips of the inner lead groups of the lead frame are alloy-bonded to each other. Bonding the film-shaped wiring board to the upper surface of the semiconductor chip, alloy-bonding the finger electrode group and the terminal electrode group, and sealing with a resin. Characteristic semiconductor device. 14. A semiconductor chip having a terminal electrode group in the peripheral portion, a lead frame having an inner lead group reaching the circuit formation surface of the semiconductor chip, an opening provided in the central portion, and the terminal electrode group in the peripheral portion. A metal film electrode group is formed on at least one surface of an insulator set to have a width that does not reach the width, and a part of the metal film electrode group is connected or a wiring pattern extended from the metal film electrode group is formed. And a film-shaped wiring board having a finger electrode group reaching the peripheral portion from the metal film electrode group, and a metal film electrode group provided on the upper surface of the film-shaped wiring board and an inner lead group of the lead frame. While alloy-bonding the tip, the film-shaped wiring board is bonded to the upper surface of the semiconductor chip, and the finger electrode group and the terminal electrode group are alloy-bonded. , A semiconductor device which is resin-sealed. 15. A semiconductor chip having a first terminal electrode group at a central portion and a second terminal electrode group at a peripheral portion, a lead frame having an inner lead group reaching a circuit formation surface of the semiconductor chip, and a central portion. A metal film electrode group is formed on the upper surface of an insulator whose width is set so as not to reach the second terminal electrode group in the peripheral portion by providing an opening avoiding the first terminal electrode group of A wiring pattern is formed on the lower surface of the body to connect with a part of the metal film electrode group through a through hole, and a wiring pattern is extended from the metal film electrode group, and the metal film electrode group has an opening on the opening and A film-shaped wiring board having a finger electrode group reaching the peripheral portion, and combining the metal film electrode group provided on the upper surface of the film-shaped wiring board with the tips of the inner lead groups of the lead frame. With bonding, the semiconductor chip upper surface and bonding the film-like wiring board, the finger electrodes and the terminal electrodes and alloyed semiconductor device which is characterized in that resin-sealed.