JPH0513529A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In the stepper exposure of the patterning process of the aluminum layer, each identification code is formed in the semiconductor integrated circuit piece to improve the production efficiency in manufacturing. An aluminum layer 3 is provided around a chip region 2 provided on a semiconductor wafer, and when patterning the aluminum layer 3, a code pattern 6 is formed by patterning an individual identification code for each chip by stepper exposure. 4, 5 and optically read the information of the individual pieces at the time of the electrical characteristic test of the semiconductor integrated circuit on the chip, and the judgment result of the quality, grade information, etc. are stored in the memory cells provided on each chip. It is possible to record, and it is possible to select and assemble only the chips of the grade that meets the demand, and it is possible to eliminate the inventory of disused items.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for identifying a plurality of semiconductor integrated circuits on the same semiconductor substrate.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, as shown in FIG. 3, an electrical characteristic test of a semiconductor integrated circuit provided in a chip area 2 of a semiconductor wafer 1 is performed, and as a result, an inker or the like is placed on a defective chip. The mark is formed by the above method so that the non-marked good product A and the marked defective product B can be distinguished.

[0003]

In the conventional semiconductor integrated circuit described above, there is a great demand for grade classification products because all the good chips are assembled into products and grade selection is performed based on electrical characteristics. Shipped from grades, low demand grades were in stock. Therefore, there is a drawback in that even a product with a small demand is additionally manufactured, resulting in a high manufacturing cost and a low production efficiency.

[0004]

According to another aspect of the present invention, there is provided a semiconductor integrated circuit including a metal layer provided on an outer periphery of a semiconductor chip region and an identification pattern provided on a part of the metal layer to display individual identification information of the semiconductor chip. And a memory cell provided in at least a part of the semiconductor chip.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

1A and 1B are a plan view and a partially enlarged view of a semiconductor chip showing an embodiment of the present invention.

As shown in FIGS. 1 (a) and 1 (b), product information / individual information unique to each chip such as a lot number and an individual number is provided in a part of the aluminum layer 3 provided on the outer periphery of the chip area 2. There are provided code areas 4 and 5 having a code pattern 6 in which the above codes are coded and recorded.

FIG. 2 is a schematic diagram for explaining the code pattern forming method of the present invention.

As shown in FIG. 2, a blind 7 corresponding to the code pattern is arranged close to the reticle 8 during stepper exposure in the patterning process of the aluminum layer, and unique data is simultaneously exposed to the semiconductor wafer 1 through the reduction lens 9. Product information and individual recognition data are recorded on the outer periphery of each chip area 2. When a semiconductor integrated circuit on a semiconductor wafer is tested for electrical characteristics, the code pattern in the chip area is optically read, and the quality judgment result and grade selection information based on the electrical characteristics are recorded on the chip along with individual information for each semiconductor integrated circuit. Can be electronically recorded in the memory cell. Therefore, it is possible to eliminate mechanical damage without performing marking in the characteristic test. In addition, at the time of assembling, the individual information is optically read and collated with the data recorded on the recording medium, and only the required grade chips can be selected and assembled.

[0010]

As described above, according to the present invention, the electric characteristic test result can be individually recognized by forming the identification pattern by the stepper for each chip area of the semiconductor wafer, and the product assembling efficiency can be improved. It has the effect of improving the input and manufacturing costs.

[Brief description of drawings]

FIG. 1 is a plan view and a partially enlarged view of a semiconductor chip showing an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a code pattern forming method of the present invention.

FIG. 3 is a plan view of a semiconductor wafer for explaining an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 semiconductor wafer 2 chip area 3 aluminum layer 4,5 code area 6 code pattern 7 blind 8 reticle 9 reduction lens A good product B defective product

Claims (1)

Claim: What is claimed is: 1. A metal layer provided on an outer periphery of a semiconductor chip region, an identification pattern provided on a part of the metal layer to display individual identification information of the semiconductor chip, and at least the semiconductor. A semiconductor integrated circuit having a memory cell provided in a part of a chip.