JPH05127936A - Fault tolerant data processor - Google Patents

Abstract

PURPOSE:To provide a data processor which is composed of hardware less than a conventional fault tolerant data processor where hardware is multiplex- constituted, and which has equal fault tolerance. CONSTITUTION:Three processors 102-104 and two bus interface units 105 and 106 are included in a data processing unit. The two bus interface units 105 and 106 have interfaces which are correspondingly connected to two system buses 107 and 108, are directly connected to two of the processors 102-104 and are indirectly connected to one via a bus switch 109. One of the three processors 102-104 is used as that for comparison/reference with the other two processors. Thus, the data processor having fault tolerance, which has the constitution of less hardware, can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a fault tolerant data processing device provided with excellent fault tolerance performance (hereinafter referred to as fault tolerance) by multiplexing hardware.

[0002]

2. Description of the Related Art Conventionally, as a typical fault tolerant data processing device of this type, a pair and
There are spare type and triple majority type.
And FIG. 3 shows those configuration examples.

In FIG. 2, processor boards 201 and 202 have two processors 203,
It has 204 and 205, 206. That is, one logical CPU in the system is composed of four processors. These four processors operate in synchronization with the same clock, and in the normal state, they perform exactly the same operation. Each processor board 201,2
The outputs of the two processors in 02 are the comparison circuits 207, 2
Always checked by 08. This system has two system buses 209 and 210. The output signal 211 of the processor 203 is used as the output from the processor board 201 for both system buses, and the output from the processor board 202 is used as the output from the processor board 202. The output signal 212 of the processor 205 is used. These output signals 211 and 212 are output to the system bus 209 from the bus transceivers 213 and 215, respectively, and to the system bus 210 from the bus transceivers 214 and 216, respectively, and wired-ORed on the system buses. .. Now tentatively processor 203 or 20
If a failure occurs in any one of No. 4 and No. 4, the comparison circuit 207 naturally detects that the two input signals are different. This abnormal signal is transmitted to the bus transceivers 213 and 214 of the processor board 201, and the outputs of these bus transceivers are controlled so as not to be output to the system buses 209 and 210. Processor board 2 at the same time
01 is recognized as having a hardware failure and is automatically disconnected from the system. Even in this state, the output of the processor board 202 continues to supply the correct data to the two system buses 209 and 210, so that the system operation can be continued normally even when the processor board 201 has a failure. .

In FIG. 3, three processor boards 301, 302, 303 operate in synchronization with the same clock. Further, this system has three system buses 304, 305 and 306, and each system bus and processor board are connected in a one-to-one correspondence. When the data of the system bus is taken in by each processor board, the data of all three system buses is taken in by each processor board. If there are triple majority logic circuits 307, 308, 309 on each processor board 301, 302, 303 and the contents of the three input data are not the same, the contents of the two sets of matching input data are treated as correct. , Data is supplied to the processors (P) in the processor boards 301, 302, 303. This mechanism allows the system to continue correct operation even if erroneous data is output to one system bus due to hardware failure.

[0005]

In each of the above-mentioned prior arts, it is necessary to prepare the hardware redundantly in order to realize fault tolerance, which results in a complicated hardware configuration and a high cost. was there.

An object of the present invention is to provide a data processing device which can prevent a system down due to a single hardware failure with a reduced hardware configuration.

[0007]

In a fault tolerant data processing apparatus according to the present invention, the data processing unit has three processors of the same type which operate in synchronization with the same clock, and the first and third processors among the processors. Directly with the second processor, indirectly with the second processor via the bus switch, directly with the second and third processors, and indirectly with the first processor with the bus switch. And two bus interface units each having an interface corresponding to each other and to two system buses.
And third or second and third two input data from each processor are compared, and the comparison result is output to the data bus together with the input data from the first or second processor, or from the system bus. The comparison result input together with the data is transmitted to each other, and when the comparison result input from the partner bus interface unit does not match, the data input to itself is supplied to the two processors having the interface directly to itself. In addition, it also has a function of supplying to a processor having an interface indirectly with itself via a bus switch.

[0008]

Out of the three processors, the output data of the third processor is used as comparison reference data for comparing whether the output data of the first and second processors output to the two system buses match or do not match. A comparison signal that is used and indicates the comparison result is output to the system bus along with the output signals of the first and second processors, respectively. Therefore, the output signals of the first and second processors on the system bus are respectively accompanied by the information of coincidence and non-coincidence with the output of the third processor, and whether or not the output data of at least two processors coincide with each other. Will always be shown. Therefore, if the comparison signals on one of the system buses do not match, it is determined that the first or second processor connected to that system bus is abnormal,
The system bus data for which the comparison signals are the same is adopted as the correct data.

If the comparison signals on the two system buses do not match each other, it means that only the third processor is faulty or only the third processor is normal. It is conceivable that the probability that the first and second processors will fail simultaneously is extremely small. Therefore, it is determined that the third comparison reference processor is abnormal and that the data on the system bus is correct.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the fault tolerant data processing apparatus of the present invention.

This fault-tolerant data processing device comprises a processor board (data processing unit) 101,
It comprises a memory unit 110, an input / output processing unit 111, and two system buses 107 and 108.
The processor board 101 has three processors (P) 102, 103, 10 that operate in synchronization with the same clock.
4 and 2 bus interface units (BIU) 10
5, 106 are included, and the bus interface 105 is connected to the system bus 107 and the bus interface unit 106.
Are connected to the system bus 108, and the memory unit 110 and the input / output processing unit 111 are connected to both of the two system buses 107 and 108, respectively. In the processor board 101, the processor 102 is the direct bus interface unit 10
5, and is also connected to the bus interface unit 106 via the bus switch 109. Similarly, the processor 104 is directly connected to the bus interface unit 106, and the bus switch 1
It is also connected to the bus interface unit 105 via 09. And one processor 103 has an interface with both the bus interfaces 105 and 106. In other words, the bus interface units 105 and 106 are commonly connected to the processor 103, and the processor 102 and the processor 104 are connected together.
One of them is directly connected, and the other is indirectly connected via the bus switch 109. The operations of the bus interface units 105 and 106 are directly connected to each other.
The data from the processors 102 and 103 and the data from the processors 104 and 103 are compared with each other, and the comparison result is connected to the connected system buses 107 and 108, respectively.
And 104 at the same time as the data output.

Next, how the fault tolerance by this hardware configuration is realized will be described. Assuming that a fault has occurred in the processor 102, the processor 10 in the bus interface unit 105 is
A mismatch in the input data from 2 and 103 is detected. As a result, the output data mismatch signal to the system bus 107 is driven. On the other hand, bus interface unit 1
On the 06 side, data is supplied from the processors 104 and 103 that are operating normally, so that no data mismatch occurs, and normal data is supplied to the system bus 108 side. That is, the unit that receives data via the system buses 107 and 108 does not use the data on the system bus 107 side, but uses the data on the system bus 108 side as correct data, so that the system can continue normal operation. If a failure occurs in the comparison processor 103, the bus interface unit 10
A discrepancy occurs in both 5 and 106. In this case, it is very unlikely that two processors will fail at the same time.
System bus 107 and 10
When the disagreement signal is output to both 8 of the busses, it is considered that correct data is output to both buses, and the processing is continued.

Next, a bus interface unit 105 for receiving data from the system buses 107, 108,
The operation of 106 will be described. The bus interface units 105 and 106 correspond to the corresponding system buses 10 respectively.
It receives data and the comparison signal from 7, 108 and communicates the results to each other. From the system bus 107 or 108 to the bus interface unit 105 or 1
If the comparison signal attached to the data input to 06 matches, the data is regarded as correct and the data is supplied to the two processors 102, 103 or 104, 103 directly connected to the bus interface units 105, 106. In this case, if the comparison signals associated with the data received by the other bus interface unit do not match,
The data is erroneous, and it is determined that the data received by the own bus interface unit is correct, and the two processors 102 and 103 or 104 and 1 directly connected to it
03, and also supplies data to the processor 104 or 102 via the bus switch 109. As a result, correct data is supplied to the three processors 102, 103, 104 in the processor board. If the comparison signal associated with the data received by its own bus interface unit does not match and the comparison signal associated with the data received by the other bus interface unit also does not match, both data are regarded as correct and processing is continued.

[0015]

As described above, according to the present invention, of the three processors included in the data processing unit, the data of one processor having an interface with both of the two bus interface units can be used for the data of the other two processors. By using it as common comparison reference data for the data output from, there is an effect that an equivalent fault tolerance can be realized with less hardware configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a fault tolerant data processing device of the present invention.

FIG. 2 is a block diagram of a conventional fault-tolerant system according to a pair-and-spare technique.

FIG. 3 is a block diagram of a conventional triple-tolerant fault tolerant system.

[Explanation of symbols]

101 processor board 102, 103, 104 processor (P) 105, 106 bus interface unit (BI
U) 107, 108 system bus 109 bus switch 110 memory unit 111 input / output processing unit

Claims (1)

[Claims] 1. A data processing unit, a memory unit,
In a data processing device including an input / output processing unit and two system buses for performing data transfer between the units, the data processing unit includes three processors of the same type that operate in synchronization with the same clock. And directly with the first and third processors of the processors, indirectly with the second processor via a bus switch, and directly with the second and third processors,
And two bus interface units each having an interface indirectly with the first processor via the bus switch and having interfaces respectively corresponding to each other and to the system bus. The bus interface unit is the first bus interface unit. And third or second and third processors are compared, and the comparison result is output to the data bus together with the input data from the first or second processor, and the system is also provided. The comparison result input together with the data from the bus is transmitted to each other, and when the comparison result input from the partner bus interface unit does not match, the data input to itself is transferred to the two data directly interfaced to itself. It is supplied to the processor and automatically A fault tolerant data processing device characterized by being supplied to a processor having an interface indirectly with the body.