JPH05102411A - Electrostatic breakdown preremedy circuit of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent breakdown due to a steep surge pulse and to improve surge breakdown strength by providing a transistor type protecting circuit directly connected to a pad through a metallic wiring layer and by interposing a diode type protecting circuit and a series resistance between it and an inside circuit. CONSTITUTION:A transistor type protecting circuit 7 against a steep surge pulse is provided with a P-channel MOS-type transistor 3 and an N-channel MOS-type transistor 5 which connect a drain to a pad 1 through a metallic wiring layer 2. A diode type protecting circuit 13 against a surface pulse whose peak value is low and charge amount is large is interposed between the transistor type protecting circuit 7 and the inside circuit 10 and has first and second P-N junction diodes 11, 12 which connect an anode to a drain of P- channel MOS-type transistor 3 and an N-channel MOS-type transistor 5. A series resistance 14 is interposed between the diode type protecting circuit 13 and the inside circuit 10 and is connected to first and second P-N junction diodes 11, 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit technique for preventing electrostatic breakdown of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional example of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit. 41 in the figure
Is a pad formed as an electrode on the semiconductor chip as an electrode for electrically connecting a semiconductor chip as a main body of the semiconductor integrated circuit and a lead for external connection, and is used as a digital input terminal. It is something. 6
Reference numeral 0 is an internal circuit having MOS type transistors and the like formed on the same semiconductor chip. A diffusion layer resistor 42 is provided between the pad 41 and the internal circuit 60 in order to suppress a high-voltage pulse (hereinafter referred to as a surge pulse) that enters toward the internal circuit 60 through the pad 41 due to static electricity. A diode type protection circuit 45 is provided.

Diffusion layer resistor 42 doped with P-type impurities
Has one end connected to the pad 41 and the other end connected to the internal circuit 60 via the diode type protection circuit 45.
The diode type protection circuit 45 includes a first PN junction diode 43 formed between a P type diffusion layer and an N type region fixed to a power supply potential VDD of a semiconductor substrate forming a semiconductor chip, and an N type diode. A second layer formed between the diffusion layer and a P-type region of the semiconductor substrate which is fixed to the ground potential GND.
PN junction diode 44 of. 55 is a distributed PN junction formed between the diffusion layer resistor 42 and the N-type region of the semiconductor substrate fixed to the power supply potential VDD.

FIG. 4 is a circuit diagram showing another conventional example of an electrostatic breakdown countermeasure circuit when the pad 41 is also used as a digital input terminal. This is obtained by replacing the diode type protection circuit 45 in the case of FIG. 3 with a transistor type protection circuit 50. The transistor type protection circuit 50 is
A P-channel MOS transistor 46 having a gate fixed to the power supply potential VDD via the first resistor 47 and a source directly fixed to the power supply potential VDD, and a gate fixed to the ground potential GND via the second resistor 49. And an N-channel MOS transistor 48 whose source is fixed directly to the ground potential GND. Both MOS type transistors 4
The drains of the reference numerals 6 and 48 are connected to each other and further connected to the internal circuit 60. A diffusion layer resistor 42 is interposed in series between the transistor type protection circuit 50 and the pad 41 as in the case of FIG. 3, and similarly between the diffusion layer resistor 42 and the power supply potential VDD. Distributed PN junction 5
5 is formed.

The operation of the conventional circuit for preventing electrostatic breakdown of the semiconductor integrated circuit having the above configuration will be described with reference to FIGS. 3 and 4.

A digital signal supplied to the internal circuit 60 on the semiconductor chip is supplied through the pad 41. The surge pulse also enters the semiconductor chip through the same pad 41. The surge pulse that has entered through the pad 41 has its peak value attenuated by the action of the parasitic capacitance (not shown) between the pad 41 and the semiconductor substrate and the function of the diffusion layer resistor 42, and then the diode type protection circuit 45 or the transistor type transistor. It is transmitted to the protection circuit 50. The diode-type protection circuit 45 and the transistor-type protection circuit 50 both supply the surge pulse to the power supply potential VDD according to the polarity of the surge pulse.
Alternatively, the peak value of the surge pulse is further attenuated by letting it escape to the ground potential GND. Therefore,
Only the surge pulse that is greatly attenuated is applied to the gate of the MOS transistor of the internal circuit 60, for example, and the internal circuit 60 is protected from electrostatic breakdown. That is, the surge withstand voltage of the semiconductor integrated circuit is improved as compared with the case where the internal circuit 60 is directly connected to the pad 41.

FIG. 5 and FIG. 6 show the case where one pad 41 is connected to _n (n ≧ 2) internal circuits 60 _{1 to} 60 _n of the electrostatic breakdown countermeasure circuits of FIGS. 3 and 4, respectively ( FIG. 11 is a circuit diagram showing a conventional example applied to an analog reference potential input terminal).

In FIG. 5, the pad 41 used as an analog reference potential input terminal has internal circuits 60 _{1 to} 6 6.
Diffusion layer resistors 42 _{1 to} 42 _n and diode type protection circuits 45 _{1 to} 45 _n are interposed between 0 _n and 0 _n . Distributed PN junctions 55 _{1 to} 55 _n are formed between the diffusion layer resistors 42 _{1 to} 42 _n and the power supply potential VDD, respectively. Further, in FIG. 6, the pad 41 also used as the analog reference potential input terminal is the internal circuit 60.
_{1 to} 60 _n and distributed PN junctions 55 _{1 to} 55 _n , respectively.
The diffusion layer resistors 42 _{1 to} 42 _n and the transistor type protection circuits 50 ₁ to 50 _n are interposed.

In the electrostatic breakdown countermeasure circuits shown in FIGS. 5 and 6, n internal circuits 60 _{1 to} 60 _n on the semiconductor chip are provided.
The analog reference potentials applied to the
Supplied through 1. At this time, an input current having a direction corresponding to the polarity of the analog reference potential flows through the pad 41. Therefore, the pad 41 and the internal circuits 60 _{1 to} 6 6
If the common impedance with 0 _n is large, mutual interference may occur between the internal circuits 60 _{1 to} 60 _n . Therefore, as described above, each of the internal circuits 60 _{1 to} 60
provided individually diffusion layer resistance 42 ₁ through 42 _n and the diode type protection circuit 45 ₁ to 45 _n for each _n, or the diffusion layer resistance 42 ₁ through 42 _n and the transistor-type protection circuit 50 _1-5
0 _n was individually provided. Moreover, in order to suppress the voltage drop in each of the diffusion layer resistors 42 _{1 to} 42 _n ,
The resistance of each of the diffusion layer resistance 42 ₁ through 42 _n have been set low. Then, the surge pulse that has entered the semiconductor chip through the same pad 41 is transmitted to each diffusion layer resistor 42.
_{1 to} 42 _n and each of the diode type protection circuits 45 _{1 to} 45 _n or the transistor type protection circuits 50 ₁ to 50 _n act to attenuate the same as in the case of FIG. 3 or FIG.

[0010]

In any of the conventional electrostatic breakdown preventing circuits for semiconductor integrated circuits shown in FIGS. 3 to 6, the pad 41 and the diode-type or transistor-type protection circuit 45 (45 _{1 to} 45) are used. _n ), 50 (50 ₁ to 50 _n )
Diffusion layer resistance 42 (42 ₁ ~42 _n) is interposed with since a configuration to some extent attenuate the surge pulse by the diffusion layer resistance between the, particularly when steep surge pulse has penetrated through a pad 41 , The invading surge pulse is the protection circuit 45 (45 _{1 to} 45 _n ), 50 (50 ₁ to
50 _n ) before reaching the power supply potential VDD or the ground potential GND, the diffusion layer resistor 42 doped with a P-type impurity.
(42 ₁ ~42 _n) and distribution PN junction between the semiconductor substrate of N-type regions 55 (55 ₁ ~55 _n) is a problem of being destroyed by receiving a reverse voltage by the surge pulse. The distributed PN junction 55 (55 _{1 to} 55 _n ) leads to permanent destruction.

An object of the present invention is to further improve the surge withstand voltage of a semiconductor integrated circuit.

[0012]

In order to achieve the above object, the present invention provides a surge pulse which penetrates into an internal circuit on a semiconductor chip through a pad formed as an electrode on the semiconductor chip in the semiconductor integrated circuit. In the electrostatic breakdown prevention circuit provided between the pad and the internal circuit in order to suppress the noise, a transistor-type protection circuit directly connected to the pad is provided as a countermeasure against electrostatic breakdown against a steep surge pulse, and at the same time, As a measure against electrostatic breakdown against a surge pulse having a low high value but a large amount of electric charge, a configuration in which a diode type protection circuit and a series resistor are interposed between the transistor type protection circuit and an internal circuit is adopted.

More specifically, the invention of claim 1 is as follows.
The transistor type protection circuit 7, the diode type protection circuit 13 and the series resistor 14 as shown in FIG. 1 are adopted between the pad 1 and the internal circuit 10. That is, in the transistor-type protection circuit 7, the drain is connected to the pad 1 through the metal wiring layer 2, the gate is fixed to the power supply potential VDD via the first resistor 4, and the source is directly connected to the power supply potential VDD. A fixed P-channel MOS transistor 3, a drain thereof is connected to the drain of the P-channel MOS transistor 3, and a gate thereof is connected to the ground potential GN via the second resistor 6.
And an N-channel MOS transistor 5 whose source is fixed directly to the ground potential GND. The diode-type protection circuit 13 is interposed between the transistor-type protection circuit 7 and the internal circuit 10, and its anode is connected to the drains of the P-channel MOS type transistor 3 and the N-channel MOS type transistor 5, respectively, and The first PN junction diode 11 whose cathode is fixed to the power supply potential VDD, and the cathode is the first PN junction diode 11.
And a second PN junction diode 12 which is connected to the anode of the PN junction diode 11 and whose cathode is fixed to the ground potential GND. Further, the series resistor 14 is connected to the diode type protection circuit 13 and the internal circuit 1
0, one end of which is the anode of the first PN junction diode 11 and the second PN junction diode 12
Is commonly connected to the cathode of the
Is connected to.

According to a second aspect of the present invention, as shown in FIG. 2, a plurality of internal circuits 10 ₁ to 10 on the semiconductor chip are passed through one pad 1 formed as an electrode on the semiconductor chip in the semiconductor integrated circuit. An electrostatic breakdown countermeasure circuit provided between the pad 1 and the plurality of internal circuits 10 ₁ to 10 _n for suppressing a surge pulse that intrudes toward _n (n ≧ 2). Of the diode type protection circuit 13 and the series resistor 14 are individually provided (13 _{1 to} 13 _n , 14 _{1 to} 14 _n ) for each of the internal circuits 10 ₁ to 10 _n , and the pad 1 and each diode type protection circuit 13 _{1 are provided.} ~ 13
One transistor type protection circuit 7 having the above configuration between _n and
Is adopted in common.

[0015]

According to the first aspect of the present invention, the surge pulse that has entered through the pad 1 is applied to the transistor type protection circuit 7 through the metal wiring layer 2 while the peak value is not attenuated.

In the transistor type protection circuit 7, the P channel MOS type transistor 3 is formed on the N type region fixed to the power supply potential VDD in the semiconductor substrate forming the semiconductor chip, and is of the N channel MOS type. The transistor 5 is formed on the P-type region of the semiconductor substrate which is fixed to the ground potential. However, when a sharp positive surge pulse enters, the N-channel MOS transistor 5 is Drain and semiconductor substrate P
Before the PN junction with the type region receives the reverse voltage by the surge pulse and is destroyed, the surge pulse causes conduction between the drain and the source of the P-channel MOS type transistor 3, and the surge pulse has the power supply potential. Escaped to VDD. On the contrary, when a sharp negative surge pulse enters, the PN junction between the drain of the P-channel MOS transistor 3 and the N-type region of the semiconductor substrate receives a reverse voltage due to the surge pulse and is destroyed. Before being done
The surge pulse conducts between the drain and the source of the N-channel MOS transistor 5, and the surge pulse escapes to the ground potential GND. In other words, the steep surge pulse that has entered through the pad 1 is caused by turning on one of the P-channel MOS type transistor 3 and the N-channel MOS type transistor 5 that form the transistor type protection circuit 7, thereby turning on the transistor. The pattern protection circuit 7 is released to the power supply potential VDD or the ground potential GND without being destroyed. Therefore, the internal circuit 10 is protected from electrostatic breakdown.

When a surge pulse having a low peak value but a large amount of electric charge enters, the surge pulse is attenuated by the action of the diode type protection circuit 13 and the series resistor 14 as in the conventional case, and the internal circuit is reduced. 10 is protected from electrostatic damage.

By the way, one pad 1 is n (n ≧ 1).
When connected to the internal circuit 10 ₁ to 10 _n of 2), with the pad 1 and the transistor type protection circuit 7 and a diode type protection circuit 13 and the series resistor 14 between the internal circuits 10 ₁ to 10 _n In the case of adopting a configuration in which all of the internal circuits 10 ₁ to 10 _n are increased due to the progress of miniaturization of the semiconductor integrated circuit with the improvement of the semiconductor manufacturing technology, the transistor type protection circuit is correspondingly provided. 7. The numbers of the diode-type protection circuit 13 and the series resistance 14 increase, which causes a problem of increasing the chip cost.

However, according to the second aspect of the invention, since one transistor type protection circuit 7 is commonly used, the cost of the semiconductor chip can be reduced. Moreover, since the pad 1 and the transistor-type protection circuit 7 are directly connected by the metal wiring layer 2 having a low resistance value, the common impedance between the pad 1 and each of the internal circuits 10 ₁ to 10 _n is kept low. Be done. Therefore, the internal circuit 10 ₁ to
There is no risk of mutual interference during 10 _n .

[0020]

1 is a circuit diagram showing an embodiment of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit according to the invention of claim 1, in which a pad is used as a digital input terminal. Is.

A transistor type protection circuit 7, a diode type protection circuit 13 and a series resistor 14 are provided between the pad 1 and the internal circuit 10.

The transistor-type protection circuit 7 has a CMOS structure and has a P-channel MOS type transistor 3 and an N-channel MOS type transistor 5 whose drains are directly connected to the pad 1 through the metal wiring layer 2.
The P-channel MOS transistor 3 is formed on an N-type region fixed to the power supply potential VDD in a semiconductor substrate forming a semiconductor chip, and has a gate connected to a power supply via a first resistor 4. It is fixed to the potential VDD and the source is directly fixed to the power supply potential VDD. N channel MO
The S-type transistor 5 is formed on a P-type region of the semiconductor substrate which is fixed to the ground potential,
The gate is fixed to the ground potential GND via the second resistor 6, and the source is directly fixed to the ground potential GND.

The diode type protection circuit 13 is interposed between the transistor type protection circuit 7 and the internal circuit 10 and has first and second PN junction diodes 11 and 12. First
The PN junction diode 11 is formed between the P-type diffusion layer and the N-type region of the semiconductor substrate fixed to the power supply potential VDD, and the anode is a P-channel MO diode.
It is connected to the drains of the S-type transistor 3 and the N-channel MOS type transistor 5, and the cathode is fixed to the power supply potential VDD. The second PN junction diode 12 is formed between the N type diffusion layer and the P type region of the semiconductor substrate which is fixed to the ground potential GND, and the cathode is the first PN junction diode. 11 is connected to the anode and the cathode is at ground potential G
It is fixed to ND.

The series resistor 14 is a diode type protection circuit 1.
Of the first PN junction diode 11 and the second PN junction diode 12 formed of polysilicon so as to be interposed between the third PN junction diode 11 and the internal circuit 10.
Is commonly connected to the cathode of the
It is connected to the.

According to the insulation breakdown countermeasure circuit having the above configuration,
The surge pulse that has entered through the pad 1 is applied to the transistor type protection circuit 7 through the metal wiring layer 2 without the peak value being attenuated.

Nowadays, as semiconductor manufacturing technology is improved and the miniaturization of semiconductor integrated circuits is advanced, the impurity concentration of the source and drain regions of a MOS type transistor on a semiconductor chip is generally increased. Two MOS transistors 3 and 5 that form the protection circuit 7.
, The reverse breakdown voltage of the PN junction formed between the source and drain and the semiconductor substrate is lowered.

However, when a steep surge pulse of positive polarity enters through the pad 1, the N channel MO
Before the PN junction between the drain of the S-type transistor 5 and the P-type region of the semiconductor substrate receives the reverse voltage due to the surge pulse and is destroyed, the drain / source of the P-channel MOS type transistor 3 is caused by the surge pulse. The electrical connection is established between them and the surge pulse is released to the power supply potential VDD. On the contrary, when a sharp negative surge pulse enters, the PN junction between the drain of the P-channel MOS transistor 3 and the N-type region of the semiconductor substrate receives a reverse voltage due to the surge pulse and is destroyed. Before the surge, the surge pulse conducts between the drain and the source of the N-channel MOS transistor 5, and the surge pulse escapes to the ground potential GND. In other words, the steep surge pulse that has entered through the pad 1 is caused by turning on one of the P-channel MOS type transistor 3 and the N-channel MOS type transistor 5 that form the transistor type protection circuit 7, thereby turning on the transistor. The mold protection circuit 7 is released to the power supply potential VDD or the ground potential GND without being destroyed, and the internal circuit 10 is protected from electrostatic breakdown.

When a surge pulse having a low peak value but a large amount of electric charges enters, the surge pulse is actuated by the diode type protection circuit 13 and the series resistor 14 in the same manner as in the conventional power source potential VDD or the ground potential. It escapes to GND and is attenuated, and the internal circuit 10 is protected from electrostatic breakdown.

FIG. 2 is a circuit diagram showing an embodiment of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit according to the invention of claim 2, wherein a pad is used as an analog reference potential input terminal. It is a thing.

A pad 1 in the figure is for supplying an analog reference potential to _n (n ≧ 2) internal circuits 10 ₁ to 10 _n . Pad 1 and n internal circuits 10 ₁ to 1
One transistor type protection circuit 7 is interposed between 0 _n and 0 _n . This transistor type protection circuit 7 has a P channel MOS type transistor 3 and an N channel MOS type transistor 5 whose drains are directly connected to the pad 1 through the metal wiring layer 2 as in the case of FIG. The P-channel MOS type transistor 3 has its gate fixed to the power supply potential VDD through the first resistor 4 and its source directly fixed to the power supply potential VDD, and the N-channel MOS type transistor 5 has its gate fixed to the second power supply potential VDD. It is fixed to the ground potential GND through the resistor 6 and the source is directly fixed to the ground potential GND.

Between the transistor type protection circuit 7 and the n internal circuits 10 ₁ to 10 _n , there are provided diode type protection circuits 13 _{1 to} 13 _n and a series resistor 14 made of polysilicon.
_{1 to} 14 _n are individually provided. In each of the n diode-type protection circuits 13 _{1 to} 13 _n , the anode is connected to the drains of the P-channel MOS type transistor 3 and the N-channel MOS type transistor 5 and the cathodes thereof are the same as in the case of FIG. First PN junction diodes 11 _{1 to} 11 _n fixed to the power supply potential VDD, a cathode connected to the anodes of the _first PN junction diodes 11 _{1 to} 11 _n , and a cathode connected to the ground potential GN.
Second PN junction diodes 12 _{1 to} 12 fixed to D
_{with n} .

According to the dielectric breakdown countermeasure circuit for inputting the analog reference potential having the above-described configuration, as in the case of FIG. 1, a steep surge pulse and a surge pulse having a low peak value but a large amount of charge are generated. Both of them can be attenuated, and an electrostatic breakdown countermeasure circuit can be realized which is different from the conventional one and is not accompanied by a steep surge pulse. Moreover, since one transistor type protection circuit 7 is commonly used, the cost of the semiconductor chip can be reduced. Further, since the pad 1 and the transistor-type protection circuit 7 are directly connected by the metal wiring layer 2 having a low resistance value, the common impedance between the pad 1 and each of the internal circuits 10 ₁ to 10 _n is kept low. Be done. Therefore, there is no possibility that mutual interference will occur between the internal circuits 10 ₁ to 10 _n .

[0033]

As described above, according to the first aspect of the present invention, as a countermeasure against electrostatic damage against a steep surge pulse, a transistor type protection circuit directly connected to a pad through a metal wiring layer is provided, and at the same time, the peak value is Since a diode type protection circuit and a series resistance are interposed between the transistor type protection circuit and an internal circuit as a measure against electrostatic breakdown against a surge pulse having a low charge amount, however,
Unlike the prior art, it is possible to realize an electrostatic breakdown countermeasure circuit that does not cause breakdown due to a steep surge pulse, and it is possible to significantly improve the surge withstand voltage of a semiconductor integrated circuit as compared with the conventional one.

According to the second aspect of the present invention, when one pad is connected to a plurality of internal circuits, one transistor type protection circuit 7 directly connected to the pad through the metal wiring layer is common. Since it is adopted, the surge withstand voltage of the semiconductor integrated circuit can be improved while reducing the cost of the semiconductor chip. Moreover, since the common impedance between the pad and each internal circuit is suppressed to a low level, there is no possibility of mutual interference between the internal circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit according to the invention of claim 1, wherein a pad is used as a digital input terminal.

FIG. 2 is a circuit diagram showing an embodiment of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit according to the invention of claim 2, wherein a pad is used as an analog reference potential input terminal. ..

FIG. 3 is a circuit diagram showing a first conventional example of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit, showing an example in which a pad is used as a digital input terminal.

FIG. 4 is a circuit diagram showing a second conventional example of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit, showing an example in which a pad is used as a digital input terminal.

FIG. 5 is a circuit diagram showing a third conventional example of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit, showing an example in which a pad is used as an analog reference potential input terminal.

FIG. 6 is a circuit diagram showing a fourth conventional example of a circuit for preventing electrostatic breakdown of a semiconductor integrated circuit, showing an example in which a pad is used as an analog reference potential input terminal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pad 2 ... Metal wiring layer 3 ... P-channel MOS type transistor 4 ... First resistance 5 ... N-channel MOS type transistor 6 ... Second resistance 7 ... Transistor type protection circuit 10, 10 ₁ to 10 _n ... Internal circuit 11, 11 ₁ to 11 _n ... first PN junction diode 12, 12 ₁ to 12 _n ... second PN junction diode 13, 13 ₁ to 13 _n ... diode type protection circuit 14, 14 ₁ to 14 _n ... series resistance

Claims (2)

[Claims] 1. A semiconductor integrated circuit is provided between a pad formed as an electrode on a semiconductor chip and between the pad and the internal circuit in order to suppress a surge pulse entering toward an internal circuit on the semiconductor chip. And a drain connected to the pad through a metal wiring layer, a gate fixed to a power supply potential via a first resistor, and a source directly fixed to the power supply potential. The channel MOS transistor and the drain are the P channel M
A transistor type protection circuit having an N-channel MOS type transistor connected to the drain of the OS type transistor, having a gate fixed to the ground potential via a second resistor and a source directly fixed to the ground potential, A first interposed between the transistor type protection circuit and the internal circuit, the anode is connected to the drains of the P-channel MOS type transistor and the N-channel MOS type transistor, and the cathode is fixed to the power supply potential. A diode-type protection circuit having a PN junction diode and a second PN junction diode whose cathode is connected to the anode of the first PN junction diode and whose cathode is fixed to the ground potential; And the internal circuit, and one end of which is the first PN junction die. And a cathode of the second PN junction diode, and a series resistor having the other end connected to the internal circuit. circuit. 2. A pad and a plurality of internal portions of a semiconductor integrated circuit for suppressing a surge pulse entering through a pad formed as an electrode on a semiconductor chip toward a plurality of internal circuits on the semiconductor chip. A circuit for preventing electrostatic breakdown provided between the circuit and the circuit, wherein a drain is connected to the pad through a metal wiring layer, a gate is fixed to a power supply potential through a first resistor, and a source is directly supplied with a power supply. A P-channel MOS type transistor whose potential is fixed and a drain of the P-channel M-type transistor
One transistor type protection circuit having an N-channel MOS type transistor which is connected to the drain of the OS type transistor, whose gate is fixed to the ground potential via the second resistor and whose source is directly fixed to the ground potential. , Each of which is interposed between the transistor type protection circuit and each of the plurality of internal circuits, and whose anode is the P channel M.
A first PN junction diode connected to the drains of the OS-type transistor and the N-channel MOS type transistor and having a cathode fixed to the power supply potential; and a cathode connected to the anode of the first PN-junction diode And a plurality of diode-type protection circuits each having a second PN junction diode whose cathode is fixed to the ground potential, and interposed between each of the plurality of diode-type protection circuits and each of the plurality of internal circuits. And one end is the first P
A static electricity storage device for a semiconductor integrated circuit, comprising a plurality of series resistors commonly connected to an anode of an N-junction diode and a cathode of the second PN junction diode and having the other end connected to the internal circuit. Electric breakdown protection circuit.