JPH05102237A - Semiconductor device and method of forming electrode pad thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor device that can be thinned even if an electrode pad formed on a semiconductor element and an inner lead are connected using a bonding wire, and a method for forming the electrode pad with a small number of steps. provide. [Structure] An electrode pad 12 and an inner lead 13 formed at a position lower than an upper surface 11a of a semiconductor element 11 are connected by a bonding wire 14, and the semiconductor element 11, the inner lead 13 and a bonding wire 14 are packaged in a package 15. And integrally seal. Further, the recess formed so as to traverse the streets on the wafer is divided at the same time when the streets are cut, and the desired electrode pad 12 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an electrode pad formed on a semiconductor element and an inner lead are connected by a bonding wire, and these are integrally sealed in a package, and a method for forming the electrode pad. Is.

[0002]

2. Description of the Related Art With the miniaturization of electronic devices, semiconductor devices used for them tend to be smaller and thinner. FIG. 6 shows a sectional view of a semiconductor device having a structure in which a mold resin is used as a package for integrally encapsulating a semiconductor element. That is, in the semiconductor device 1, the electrode pad 12 is formed on the upper surface 11 a of the semiconductor element 11, and the electrode pad 12 and the inner lead 13 are connected by the bonding wire 14. Then, the semiconductor element 11, the inner leads 13, and the bonding wires 14 are integrally sealed with a package 15 made of a molding resin to form the semiconductor device 1.

A gold wire, for example, is used as the bonding wire 14. This bonding wire 1
4 is connected in a loop from the electrode pad 12 formed on the upper surface 11a of the semiconductor element 11. The height from the upper surface of the electrode pad 12 to the uppermost part of the loop of the bonding wire 14 is h, and this height h is hereinafter referred to as the loop height. The total thickness of the semiconductor device 1 having such a structure is the thickness of the package 15, that is, the semiconductor element 11.
It depends largely on the total thickness of the thickness d ₁ of the package 15 on the upper surface side, the thickness d ₂ of the semiconductor element 11 and the thickness d ₃ of the package 15 on the lower surface side of the semiconductor element 11. Therefore, the semiconductor device 1 as a whole is made thinner by forming these d ₁ , d ₂ and d ₃ thin.

[0004]

However, the semiconductor device described above has the following problems. That is, in the semiconductor device 1 shown in FIG. 6, since the bonding wire 14 is connected in a loop from the electrode pad 12 formed on the upper surface 11a of the semiconductor element 11, d _{1 of the} packages 15 that integrally seal these is used. Cannot be thinner than the height h of the loop. In addition, there is a limit to the reduction of the thickness of the semiconductor element 11 by d ₂ , so that it becomes impossible to reduce the thickness of the semiconductor device 1 as a whole. Therefore, the present invention provides a semiconductor device that can be thinned even if the electrode pad formed on the semiconductor element and the inner lead are connected using a bonding wire, and a method for forming the electrode pad with a small number of steps. To aim.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, in which an electrode pad formed on a semiconductor element and an inner lead are connected by a bonding wire. In a semiconductor device in which a bonding wire and an inner lead are integrally sealed in a package, the electrode pad is provided at a position lower than the upper surface of the semiconductor element. Further, a recess having a predetermined depth is formed in a state of crossing a street for partitioning a plurality of electric circuits on the upper surface of the semiconductor wafer, and an electrode layer is formed so as to cover the surface of the recess with an insulating layer interposed therebetween. A semiconductor device comprising electrically connecting an electrode layer and an electric circuit, cutting a semiconductor wafer along a street to divide it into chip-shaped semiconductor elements, and at the same time dividing an electrode layer, an insulating layer and a recess. This is a method of forming an electrode pad.

[0006]

Since the electrode pad is provided at a position lower than the upper surface of the semiconductor element, when the electrode pad and the inner lead are connected by a loop-shaped bonding wire, the uppermost bonding wire protruding from the upper surface of the semiconductor element is The position is low. Therefore, the semiconductor device can be thinned because the bonding wire is not exposed from the package even if the package on the upper surface side of the semiconductor element is thinned by the size of the lowermost position of the bonding wire. Further, since the streets on the upper surface of the semiconductor wafer are cut to be divided into chip-shaped semiconductor elements, at the same time, the recesses having a predetermined depth formed so as to cross the streets are divided, so that the upper surface is formed on the peripheral portion of each semiconductor element. Lower electrode pads will be formed.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a cross-sectional view illustrating a semiconductor device of the present invention, FIG. 2 is a perspective view illustrating a semiconductor element, and FIG. 3 is a cross-sectional view illustrating an electrode pad. As shown in FIG. 1, a semiconductor device 1 of the present invention includes an electrode pad 12 formed on a semiconductor element 11, a bonding wire 14 for connecting the electrode pad 12 and an inner lead 13 such as a lead frame, And a package 15 that integrally seals these.

The electrode pad 12 is provided at a position lower than the upper surface 11a of the semiconductor element 11 by a height H, and the electrode pad 12 and the inner lead 13 are connected via a bonding wire 14 having a loop height h. ing.
Therefore, the position of the uppermost portion of the bonding wire 14 is lowered by the size of this H. Therefore, if H is set to be larger than the loop height h, for example, the uppermost portion of the bonding wire 14 does not protrude from the upper surface 11a of the semiconductor element 11.

The package 15 is formed by using a molding resin by, for example, a transfer molding method. The thickness of the package 15 is the upper surface side d ₁ of the semiconductor element 11, the thickness d ₂ of the semiconductor element 11 and the lower surface side of the semiconductor element 11. It is the sum of d ₃ and.

As a concrete example, when the electrode pad 12 is formed at a position where the height H from the upper surface 11a of the semiconductor element 11 is 150 μm and the loop height h of the bonding wire 14 is 150 μm, the maximum bonding wire 14 is formed. The upper portion does not rise above the upper surface 11a of the semiconductor element 11. Therefore, the thickness d ₂ of the semiconductor element 11 is 300 μm.
When m, the minimum thickness of the entire package 15 is substantially equal to the thickness d ₂ of the semiconductor element 11. Note that H may be smaller than the loop height h, and in that case, the uppermost portion of the bonding wire 14 is the semiconductor element 1.
Since it projects from the upper surface 11a of the semiconductor element 11, the thickness d ₁ of the package 15 on the upper surface side of the semiconductor element 11 may be formed to a thickness such that the bonding wire 14 is not exposed.

Next, the semiconductor element of the semiconductor device of the present invention will be described with reference to FIG. As shown in FIG. 2, a large number of recessed recesses having a predetermined depth are formed in the peripheral portion of the semiconductor element 11, and electrode pads 12 are formed on the inner surfaces of each recess. Each electrode pad 1
2 and the inner leads 13 at the corresponding positions are connected by a bonding wire 14 using, for example, a gold wire.

As shown in FIG. 3, the electrode pad 12 is formed in such a manner that the inner surface of the recess formed in the semiconductor element 11 is covered with an electrode layer 12b made of aluminum or the like via an insulating layer 12a. The electrode layer 12b is electrically connected to the electrode layer 12b of an electric circuit (not shown) formed of a transistor or the like formed on the surface of the semiconductor element 11. As a result, the electrode pad 12 becomes the upper surface 11a of the semiconductor element 11.
Is electrically connected to the electric circuit at a position lower by a height H.

Next, a method of forming the electrode pad 12 will be described with reference to FIG.
It demonstrates in order of a process based on FIG. First, as a first step, as shown in FIG. 4A, a resist 2 is applied to the surface of a wafer 10 made of silicon or the like. Then, using the mask 3, for example, only a portion of the resist 2 corresponding to the recess for forming the electrode pad 12 is irradiated with ultraviolet rays.
It should be noted that a plurality of the recesses are formed in a state of crossing the streets for partitioning the plurality of electric circuits formed on the surface of the wafer 10. However, in FIG. 4 and FIG. I will explain using two.

Next, as a second step, as shown in FIG. 4B, the wafer 10 is etched with a chemical or the like by using the resist 2 developed and removed as a mask to form a recess having a depth H + α. To do. This α is the sum of the thicknesses of the insulating layer 12a and the electrode layer 12b, which will be described later, but is a small size with respect to the depth H of the depression. Then, an electric circuit (not shown) composed of transistors or the like is formed on the surface of the wafer 10 through a normal process.

Next, as a third step, as shown in FIG. 4C, an insulating layer 12a is formed by using, for example, the CVD method so as to cover the inner surface of the depression, and further, for example, sputtering is performed on the insulating layer 12a. Electrode layer 12 made of aluminum, etc.
b is formed. Simultaneously with the formation of the electrode layer 12b, the electric circuit formed on the surface of the wafer 10 in the above-described process is electrically connected to the electrode layer 12b.

Next, as a fourth step, as shown in FIG. 5A, a resist 2 is applied to the surface of the wafer 10 in a state of covering the electrode layer 12b formed in the above step. Then, the mask 3 is used to irradiate only the bottom of the recess of the resist 2, that is, the portion to be abraded by a dicing saw described later, with ultraviolet rays.

As a fifth step, as shown in FIG.
The resist 2 irradiated with ultraviolet rays in the previous step is removed, and the resist 2 is used as a mask to form the electrode layer 12b and the insulating layer 12a.
To remove. As a result, a portion of the electrode layer 12b and the insulating layer 12 where grooves are formed in the wafer 10 by a dicing saw described later is formed.
a is removed.

Finally, as a sixth step, as shown in FIG. 5C, the wafer 10 in a portion where the electrode layer 12b and the insulating layer 12a are removed in the previous step is smaller than this width and a dicing saw is used to make the wafer 10. Create a groove in. At this time, since the electrode layer 12b and the insulating layer 12a are removed so as to have a width larger than the width of the groove, burrs do not occur on the electrode layer 12b after the groove is cut. Thereafter, so-called back grinding is performed to grind the back surface of the wafer 10 if necessary.
Reduce the thickness of. Then, along this groove, the wafer 10
When a pressure is applied to the semiconductor chip 11, the insulating layer 12a, the electrode layer 12b, and the depression are divided into two at the same time, and the chip-shaped semiconductor element 11 is divided into the electrode pad 12. As a result, the electrode pads 12 that are lower than the upper surface 11a by the height H are formed on the peripheral edge of each of the divided semiconductor elements 11.

In the above description, the electrode pad 12 is formed by using the recessed concave portion, but the present invention is not limited to this, and the peripheral portion of the semiconductor element 11 has a step lower than the upper surface 11a thereof. The electrode pad 12 may be formed by providing a concave portion. As a method of forming this step or the above-mentioned depression,
Other than the method described above, it may be formed by using electric discharge machining. Further, when the molding resin on the upper side of the semiconductor element 11 is formed to be extremely thin, external light may pass through the molding resin, which may cause a malfunction in the electric circuit formed on the semiconductor element 11. Therefore, the semiconductor element 11
A malfunction of the electric circuit can be prevented by applying a light-shielding film using ink or the like on the surface of the mold resin above and preventing the entry of light. Further, in the above-described embodiment, the semiconductor device 1 using the mold resin as the package 15 has been described, but the present invention is not limited to this, and a similar effect can be obtained even if a ceramic package or the like is used. Be done.

[0020]

As described above, the semiconductor device and the method of forming the electrode pad thereof according to the present invention have the following effects. That is, by providing the electrode pad at a position lower than the upper surface of the semiconductor element, the uppermost part of the loop-shaped bonding wire connecting the electrode pad and the inner lead can be lowered, so that the package above the semiconductor element can be made thin. Can be formed. Therefore, even a semiconductor device in which the electrode pad and the inner lead are connected by using the bonding wire can be made thin. Further, the streets of the wafer are cut to be divided into chip-shaped semiconductor elements, and at the same time, the recesses provided so as to cross the streets are divided, and desired electrode pads are formed on the peripheral portions of the respective semiconductor elements. Therefore, the electrode pad can be efficiently formed with a small number of steps.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 2 is a perspective view illustrating a semiconductor element used in the semiconductor device of the present invention.

FIG. 3 is an enlarged sectional view illustrating an electrode pad of the present invention.

4A to 4C are cross-sectional views (No. 1) for explaining the manufacturing process of the electrode pad, where (a) is the first process, (b) is the second process, and (c).
Is the third step.

5A and 5B are cross-sectional views (No. 2) for explaining the manufacturing process of the electrode pad, where (a) is the fourth process, (b) is the fifth process, and (c).
Is the sixth step.

FIG. 6 is a cross-sectional view illustrating a conventional semiconductor device.

[Explanation of symbols]

 1 Semiconductor Device 11 Semiconductor Element 12 Electrode Pad 12a Insulating Layer 12b Electrode Layer 13 Inner Lead 14 Bonding Wire 15 Package

Claims (2)

[Claims] 1. An electrode pad formed on a semiconductor element,
In a semiconductor device comprising a bonding wire for connecting the electrode pad and the inner lead, and a package for integrally encapsulating the semiconductor element, the bonding wire and the inner lead, the electrode pad is an upper surface of the semiconductor element. A semiconductor device, which is provided at a lower position. 2. A step of forming a recess having a predetermined depth across a street for partitioning a plurality of electric circuits on the upper surface of a semiconductor wafer, and an electrode layer with an insulating layer interposed so as to cover the surface of the recess. Forming and electrically connecting the electrode layer and the electric circuit, and cutting the semiconductor wafer along the streets to divide it into chip-shaped semiconductor elements, and at the same time, the electrode layer and the insulating layer. A method of forming an electrode pad of a semiconductor device, comprising the step of dividing the concave portion.