JPH048031A - diversity receiver - Google Patents

Abstract

PURPOSE:To eliminate the need for a monitoring demodulation section or the like by generating and counting an error correcting signal at error correction, comparing them, controlling a signal switching device and outputting a data stored in the memory of a reception system with excellent line quality. CONSTITUTION:An error detecting and correcting circuit 10a generates an error correcting signal indicating the correction every time one bit of erroneous bits 23 is corrected and sends the signal to an error correcting signal comparator 12. The error correcting signal comparator 12 counts an error correcting signal outputted from the error detecting and correcting circuits 10a, 10b and compares the signals to decide which of reception systems is excellent in the line quality. The error correcting signal comparator 12 controls a signal switching device 13 based on the result of decision to switch the signal switching device 3 so that the data by one frame stored in a memory 11a is read. Thus, the reception path is selected to the reception system offering excellent line quality at every frame.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a diversity receiving device used in mobile communication systems and the like.

[Conventional technology]

FIG. 3 is a block diagram showing a guiversity receiving apparatus described in Japanese Patent Application Laid-Open No. 58-202642. In the figure, la and lb are antennas arranged spatially separated from each other, and 2a and 2b are connected to antenna 1a or 1b, respectively, and demodulate the signal received by antenna 1a (Ib). It is also a receiver that detects code errors in demodulated data and outputs error pulses.

3 is a signal switch that selects one of the receivers 2a and 2b and outputs the data demodulated by the receiver 2a (2b); 4 is a signal switch that selects one of the receivers 2a and 2b and outputs the data demodulated by the receiver 2a (2b); 4 selects one of the receivers 2a and 2b; In comparison, the receiver 2a (2b
) is a comparison circuit that controls the signal switch 3 to select the signal switch 3.

Further, FIG. 4 is a block diagram showing the configuration of the receivers 2a and 2b. In the figure, 5 is the antenna 1a (Ib)
6 is a main demodulator that demodulates the signal received by the receiver 5. 7 is a monitor demodulator whose demodulation performance is set slightly lower than that of the main demodulator 6, and 8 is a monitor demodulator that compares the data demodulated by the main demodulator 6 with the data demodulated by the monitor demodulator 7 to detect error pulses. This is an error rate determination unit that generates.

Next, the operation will be explained. The signal received by the antenna 1a is sent to the receiver 2a and received by the receiver 5 thereof.

The signal received by the receiving section 5 is sent to a main demodulating section 6 and a monitor demodulating section 7, each demodulated into data with slightly different demodulation performance, and sent to an error rate determining section 8. The error rate determination section 8 determines that the data demodulated by the main demodulation section 6, which has slightly better demodulation performance, is correct, and uses it and the monitor demodulation section 7.
The error rate is determined by comparing the demodulated data with the data demodulated in , and an error pulse is generated and sent to the comparison circuit 4 . In addition, the main demodulator 6
The demodulated data is input to the signal switch 3.

On the other hand, the receiving system of the receiver 2b also operates in the same manner as the receiving system of the receiver 2a, and sends error pulses to the comparator circuit 4 and data demodulated by the main demodulator 6 to the signal switch 3.

The comparison circuit 4 compares the error rates received from the error rate determining sections 8 of the receivers 2a and 2b, and determines the receiving system with the lowest error rate. The signal switching device 3 is controlled according to the determination of the comparison circuit 4, and if the error rate of the receiving system of the receiver 2a is low, the data from the main demodulator 6 of the receiver 2a is transferred to the receiver 2a.
If the error rate of the receiving system b is low, switching is made to select and output data from the main demodulator 6 of the receiver 2b.

[Problem to be solved by the invention]

Since the conventional Guibersich receiver is configured as described above, each receiving system requires a monitor demodulator 7 in addition to the main demodulator 6, which not only complicates the circuit configuration, but also makes it difficult to determine the error rate. determines that the data demodulated by the main demodulator 6 is correct, and if the data demodulated by the main demodulator 6 is also incorrect, the data demodulated by the monitor demodulator 7 is generated based on comparison with the data demodulated by the monitor demodulator 7. There is a problem in that the error pulses are no longer output, and the signal switch 3 is no longer able to properly switch the receiving system.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a diversity receiving device that always switches the receiving system correctly and has a simple circuit configuration.

[Means to solve the problem]

The diversity receiving device according to the present invention detects code errors in data demodulated by the receiver of each receiving system,
When a code error is detected, a plurality of error detection/correction circuits correct the error focus and generate an error correction signal, a plurality of memories store error-corrected data in each error detection/correction circuit, and each It is equipped with an error correction signal comparison circuit that counts and compares the error correction signals from the error detection/correction circuits, and controls switching of the signal switch based on the comparison results.

[For production]

The diversity receiving device in this invention has error detection and
The correction circuit detects a code error in the data demodulated by the receiver of each receiving system, corrects the error bit, generates an error correction signal at the time of error correction, and compares the error correction signal with the error correction signal. Count and compare each in the circuit, switch the signal switch based on the comparison result,
By outputting data stored in the memory of a receiving system with good line quality, a diversity receiving device with a simple circuit configuration and capable of always switching to the correct receiving system is realized.

C Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, la and Ib are antennas, and 3 is a signal switch, which are the same or equivalent parts as those in the conventional system, which are given the same reference numerals in FIG.

Further, 9a and 9b are receivers connected to the antennas la and lb, respectively, and the connected antenna 1
By simply demodulating the signal received at a(lb),
This receiver differs from conventional receivers 2a and 2b in that it does not have a monitor demodulator 7 or an error rate determiner 8 for generating error pulses.

10a and 10b are connected to the receivers 9a and 9b, respectively, to detect code errors in data demodulated by the connected receivers 9a and 9b, and when a code error is detected, correct the error bit. This is an error detection/correction circuit that performs error correction and sends out error correction signals.

11a and llb are the error detection/correction circuits 10a and 10.
This is a memory that is connected to each of the memory terminals 10a and 10b and stores one frame's worth of data that has been error-corrected by the connected error detection/correction circuits 10a and 10b. 12 receives error correction signals from each of the error detection/correction circuits 10a and 10b, counts them, and controls the switching of the signal switch 3 based on the comparison result of the counted values to ensure reception with good line quality. This is an error correction signal comparison circuit that outputs data stored in the system memory 1la (llb).

FIG. 2 is an explanatory diagram showing the frame structure of data received by this diversity receiving device.

In the figure, 20 is a frame pattern for frame synchronization of the data, and 21 is an information bit of the data. 22 is an error correction code added to detect a code error in this information bit 21 and correct the erroneous bit, and 23 is an error bit detected in the information bit 21 by this error correction code 22. It is.

Next, the operation will be explained. The signal received by antenna 1a is demodulated into data by receiver 9a and sent to error detection/correction circuit 10a. Error detection/correction circuit 10
In a, the error correction signal 2 in the data frame shown in FIG.
2 is used to detect a code error in the information bit 21.

When an error bit 23 is detected by this code error detection, the error detection/correction circuit 10a corrects the error bit 23 using the error correction signal 22, and corrects the error bit 23 for one frame with the code error corrected. Store the data in memory 11a. At this time, the error detection/correction circuit 10a detects the error bit 2.
Each time 1 bit of 3 is corrected, an error correction signal indicating that the correction has been made is generated and sent to the error correction signal comparison circuit 12.

On the other hand, the receiving system of the receiver 9b operates similarly to the receiving system of the receiver 9a, and when a code error is detected in the information bits 21, the error bit 23 is corrected and the error correction signal is converted into an error correction signal. The data for one frame with code errors corrected is sent to the correction signal comparison circuit 12, and the data for one frame with code errors corrected is sent to the memory llb.
Store in.

The error correction signal comparison circuit 12 counts the error correction signals output from the error detection/correction circuits 10a and 10b during one frame, and compares them to determine which receiving system has better line quality. Determine. Here, it is assumed that, for example, the data input to the error detection/correction circuit 10a includes the error bit 23, and the data input to the error detection/correction circuit 10b does not include the error bit 23.

In that case, the error detection/correction circuit 10a generates error correction signals equal to the number of bits correcting code errors, and performs error detection/correction.
Correction circuit 10b does not generate an error correction signal. Therefore,
The error correction signal comparison circuit 12 counts and compares the error correction signals for one frame, and determines that the line quality of the receiving system on the receiver 9a side is better than that of the receiving system on the receiver 9b side. do. The error correction signal comparison circuit 12 controls the signal switch 3 based on the determination result, and the memory 11a
The signal switch 3 is switched so that one frame's worth of data stored in is read out.

This makes it possible to switch the receiving path to a receiving system with good channel quality for each frame.

〔Effect of the invention〕

As described above, according to the present invention, code errors in data of each receiving system are detected and corrected, an error correction signal is generated at the time of error correction, the error correction signals are counted and compared, and the error correction signals are counted and compared. Since the configuration is configured to control the signal switcher and output the data stored in the memory of the receiving system with good line quality, the circuit configuration can be simplified by eliminating the need for a monitor demodulator, etc. Even in such a case, it is possible to always switch to the correct receiving system, and there is an effect that a diversity receiving apparatus can be obtained that can perform communication with fewer code errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a diversity receiving device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the frame structure of data received by this diversity receiving device,
FIG. 3 is a block diagram showing a conventional diversity receiver, and FIG. 4 is a block diagram showing the configuration of the receiver. la and lb are antennas, 3 is a signal switch, and 9a. 9b is a receiver, 10a and 10b are error detection/correction circuits,
11a and 11b are memories, and 12 is an error correction signal comparison circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A plurality of antennas arranged spatially separated from each other, a plurality of receivers connected to each of the antennas and demodulating signals received by the connected antennas, and a plurality of receivers connected to each of the receivers. and detects a code error in data demodulated by the connected receiver, and when a code error is detected, corrects the error bit, and
a plurality of error detection/correction circuits that send out error correction signals;
a plurality of memories that are connected to each of the error detection/correction circuits and store data error-corrected by the connected error detection/correction circuits; and one of the memories is selected and stored in the memory. A signal switch that outputs the data that has been detected and the error correction signals from each of the error detection and correction circuits are counted and compared, and the switching of the signal switch is controlled based on the comparison result. A diversity receiving device comprising a correction signal comparison circuit.