JPH047845A - Manufacture of semiconductor equipment - Google Patents

Abstract

PURPOSE:To form a mask pattern of via-holes at high alighnment accuracy in reduced size by making deadend holes in the semiconductor substrate from the one side of the substrate without going through the substrate, by filling the utmost deadends of these holes with easily removable substance to form a surface mask pattern, and after that by thinly drilling the substrate from the opposite side thereof to go through the viaholes. CONSTITUTION:One side of a sheet of GaAs semiconductor substrate 1 is etched to form deadend hole 5, and the utmost deadend is filled with photoresist 6, or the like. The metallize pattern 7a connected to source electrode 2a and the wiring pattern 7b connected to the drain electrode are formed to cover hole 5, and this substrate is thinly drilled from the back of the substrate. After removing photoresist 6 or the like, the back metallize 8 is carried out, and the back metallize is electrically conducted with the source electrode 2a. With this, a throughhole mask pattern for viaholes can be formed by usual contact aligner, or the like without necessitating the use of special equipment such as infrared ray aligner, thereby being able to form a microminiaturaized mask pattern for viaholes at good precision of alignment.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device that includes a via hole grounding method for reducing parasitic inductance that is effective in a high frequency band. It is related to.

[Conventional technology]

FIGS. 2 and 3 show a conventional semiconductor device having a via hole, as disclosed in, for example, Japanese Patent Application Laid-Open No. 59-94818.

Figure 2 shows the gate electrode, drain electrode, and
A via hole is opened from the surface of the substrate on which a source electrode is formed, and FIG. 5(a) is a plan view thereof, and FIG.

In the figure, 1 is a GaAs substrate, 2a is a source electrode, 2
b is a drain electrode, 3 is a gate electrode, 7a is a wiring connected to the source electrode 2a, 7b is a wiring connected to the drain electrode 2b, 7C is a wiring connected to the gate electrode 3, 8 is metallization on the back surface, and 9 is a via hole. be.

Next, a method of manufacturing this structure will be explained.

First, a gate electrode 3, a drain electrode 2b, and a source electrode 2a are formed on the main surface of the GaAs substrate 1, and then a resist pattern is formed to cover these electrodes and have openings between adjacent source electrodes 2a. do. Then, using the pattern as a mask, an opening is formed in the GaAs substrate 1 by etching. Next, gate electrode 3. The drain electrode 2b is metallized with Au or the like, and the wiring 7c,
7b is provided, and a wiring is also provided on the inner wall of the via hole 9, thereby connecting adjacent source electrodes 2a. Next, after thinning the substrate from the back surface to reach the via hole, a conductive metal 8 is provided on the back surface of the substrate, thereby grounding the source electrode 2a through a via hole 9 opened from the front surface of the substrate.

In addition, Fig. 3 shows another conventional example, which is based on a manufacturing method in which a via hole is opened from the back side of a high-output FET, and Fig. 3 (a) is a plan view thereof. (b)
is a sectional view taken along line BB' in FIG. 3(a).

In the figure, the same reference numerals as in FIG. 2 indicate the same parts, and the manufacturing method thereof will be explained below.

First, after forming the gate electrode 3, drain electrode 2b, and source electrode 2a on the main surface of the GaAs substrate 1, wirings 7c and 7b are connected to these electrodes.

7a is formed. Source electrode 2 formed on the surface of substrate 1
A is positioned from the back side using a device such as an infrared aligner, and a via hole 9 is opened using the formed mask pattern.Then, the back side of the substrate 1 and the inside of the via hole 9 are filled with Au.
The source electrode 2a is grounded through a via hole 9.

In this way, the semiconductor device having the via hole structure penetrating the substrate shown in FIGS. 2 and 3 has excellent operation because deterioration in device performance is reduced even in high frequency bands such as microwave bands. can have characteristics. This is 1
This is because, as is well known, grounding inductance is smaller and more uniform when the source electrode is grounded through a via hole than when the source electrode is grounded through a bonding wire.

[Problem to be solved by the invention]

As mentioned above, there are two conventional methods for manufacturing semiconductor devices having via holes, one of which is the third method.
As shown in the figure, a source electrode formed on the front surface of a semiconductor substrate is positioned from the back side using a device such as an infrared aligner, a via hole is opened as a mask pattern, and the inside of the hole is metalized with Au, etc. It is. This method of opening via holes from the back side requires a device such as an infrared aligner that can be aligned from the back side, and furthermore, when the patterns of source electrodes etc. are reduced in order to miniaturize semiconductor devices, the via holes are opened from the back side. Alignment becomes extremely difficult, and there is a problem in that the degree of alignment deteriorates as the pattern becomes finer.

On the other hand, as shown in Figure 2, the method of opening via holes from the surface of a semiconductor substrate involves a step of thinning the semiconductor substrate during the manufacturing process, exposing the bottom of the via hole. Sometimes, due to variations in the thickness of the semiconductor substrate itself or variations in the thinning technology, a protrusion is generated at the bottom of the via hole as shown in FIG. 2(C). The height H of this protrusion reaches from several pm to several tens of μm. Therefore, when mounting a semiconductor device on a heat sink or mounting it on a measurement jig stand to measure the characteristics of an element, the semiconductor device The device is tilted, making it difficult to fully demonstrate the device performance and make measurements. Furthermore, after opening the via hole 9 on the surface of the semiconductor substrate 1, a photolithography process is required to metalize the electrode portion and the inside of the hole with Au or the like, but the via hole 9 is a deep hole. Therefore, it has been difficult to apply photoresist uniformly, and it has also been difficult to reduce the size of the metallized pattern.

This invention was made in order to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a semiconductor device having via holes, which can cope with reduction in element size without using special equipment. shall be.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, a hole is formed from the surface of a semiconductor substrate without penetrating the substrate, and a material such as photoresist that is easily removed later is filled inside the hole to form a pattern on the surface. After forming the substrate, the substrate is thinned from the back side of the substrate, the hole is penetrated, and the inside of the hole is metalized.

[Function] In this invention, even if a via hole is opened in the semiconductor substrate from the surface, the inside of the hole is filled with photoresist, etc., so that steps that are disadvantageous to pattern formation on the surface are reduced, and it is possible to cope with pattern reduction. . Further, even when the semiconductor substrate is processed to be thin, the bottom of the via hole does not remain as a protrusion, so no protrusion is generated that would be disadvantageous for mounting a semiconductor device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIGS. 2 and 3 indicate the same parts, 5 is an etched hole, 4.
6 indicates a photoresist.

Next, the manufacturing method will be explained.

First, as shown in FIG. 1(a), an active layer is formed on the surface of a semi-insulating CaAS substrate 1 by ion implantation or epitaxial growth, and then a source electrode 2a, a drain electrode 2b, and a gate electrode 3 are provided.

Next, as shown in Fig. 1 (0)), a photoresist pattern 4 with holes opened at the positions where via holes are to be formed is formed, and using this as a mask, chlorine (CI□), silicon tetrachloride (
The GaAs substrate 1 is etched by reactive ion etching (RIE) using plasma such as SiC (14). The depth of this etching varies depending on the required device performance, but for example, here, the hole 5 is etched to a depth of 35 μm.

Next, as shown in FIG. 1(C), the inside of this hole 5 is filled with photoresist or the like 6.

Next, as shown in FIG. 1(d), a metallized pattern 7a made of Au or the like is connected to the source electrode 2a so as to cover the hole 5, and a wiring pattern 7b is connected to the drain electrode, although not shown in the figure. A wiring pattern connected to the gate electrode is formed.

Next, as shown in FIG. 1(e), the GaAs substrate 1 is processed to be 30 μm thinner than the back surface thereof.

Next, as shown in FIG. 1(f), after removing the photoresist 6 filled in the hole 5 with an organic solvent or the like, metallization 8 is performed on the back surface, and this is applied to the source electrodes 2a, l! : To conduct electrically.

As described above, in the present invention, since the via hole is formed from the surface of the semiconductor substrate, there is no need for special equipment such as an infrared aligner, and a normal contact aligner can be used instead.
An opening mask pattern of via holes can be formed using a projection aligner or a projection aligner, and a mask pattern of reduced via holes can be formed with high alignment accuracy.

In addition, since the via holes are opened from the surface of the semiconductor substrate and then filled with photoresist, etc.,
Subsequent surface pattern formation becomes easy. Furthermore, since the metallization inside the via hole is performed from the back side, the bottom of the via hole does not protrude.

In the above embodiment, the depth of the hole was set to 35 μm, and the semiconductor substrate was processed to be as thin as 30 μm, but the present invention is not limited to this value.

Furthermore, although this embodiment has been described with reference to GaAsFET, it is also applicable to MMIC and the like.

Furthermore, a semiconductor substrate other than GaAs, such as indium phosphide (InP), may be used as the substrate.

〔Effect of the invention〕

According to the present invention, an opening is formed from the surface of a semiconductor substrate into the substrate with a depth that does not penetrate through the substrate, and the opening is filled with a substance such as photoresist that is easily removed later. , form a wiring pattern on the surface of the opening by connecting it to the electrode on the surface of the substrate, process the substrate to be thinner than the back surface, penetrate the opening, and apply conductive material to cover the inner wall of the opening and the back surface of the substrate. Since the conductive metal on the back surface and the electrode on the surface of the substrate are connected via the conductive metal in the opening and the wiring pattern, the via hole can be adjusted using an ordinary contact aligner or projection aligner. This has the effect of forming an aperture mask pattern with high alignment accuracy and a reduced size.

In addition, since the via holes are opened from the surface of the semiconductor substrate and then filled with photoresist, etc.,
Subsequent surface pattern formation becomes easy. Furthermore, since the metallization inside the via hole is performed from the back side, the bottom of the via hole does not protrude, and the semiconductor device can be mounted with high precision, which has the effect of making it possible to fully demonstrate the device performance.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing the structure of a semiconductor device according to a conventional example, and FIG. 3 is a diagram showing the structure of a semiconductor device according to another conventional example. FIG. 1 is a GaAs substrate, 2a and 2b are source electrodes,
a drain electrode, 3 a gate electrode, 4 a photoresist,
Reference numeral 5 indicates an etched hole, 6 indicates a photoresist filled in the hole, 7a, 7b, and 7c interconnects connected to the source electrode, drain electrode, and gate electrode, respectively, 8 indicates metallization on the back surface, and 9 indicates a via hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A step of forming an opening from the surface of a semiconductor substrate into the substrate with a depth that does not penetrate the substrate, and a step of filling the opening with a material that is easily removed later, such as photoresist. , forming a wiring pattern on the surface of the opening by connecting it to an electrode on the surface of the substrate; processing the substrate to be thinner than the back surface and passing through the opening; and an inner wall of the opening and providing a conductive metal so as to cover the back surface of the substrate, and connecting the conductive metal on the back surface and the electrode on the surface of the substrate via the conductive metal in the opening and the wiring pattern. A method for manufacturing a featured semiconductor device.