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JPH0471297A - Multilayer board provided with built-in component - Google Patents

Multilayer board provided with built-in component

Info

Publication number
JPH0471297A
JPH0471297A JP2183237A JP18323790A JPH0471297A JP H0471297 A JPH0471297 A JP H0471297A JP 2183237 A JP2183237 A JP 2183237A JP 18323790 A JP18323790 A JP 18323790A JP H0471297 A JPH0471297 A JP H0471297A
Authority
JP
Japan
Prior art keywords
substrates
anisotropic conductive
component
conductive film
multilayer board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2183237A
Other languages
Japanese (ja)
Inventor
Kotaro Hayashi
浩太郎 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Chemi Con Corp
Original Assignee
Nippon Chemi Con Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Chemi Con Corp filed Critical Nippon Chemi Con Corp
Priority to JP2183237A priority Critical patent/JPH0471297A/en
Publication of JPH0471297A publication Critical patent/JPH0471297A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To obtain a multilayer board having the forms of various circuits by a method wherein an anisotropic conductive film is installed between first and second substrates along with an arbitrary circuit component and the electrical connection of the electrodes of the circuit component with wiring conductors, which are respectively formed on the first and second electrodes, is selectively performed through the anisotropic conductive film. CONSTITUTION:A multilayer board is constituted between first and second substrates 2A and 2B and an anisotropic conductive film 10 containing a conductive filler 14 is inserted between electrodes 61, 62, 63...6n of a base chip 6 and wiring electrodes 21, 22, 23...2n. Then, wiring conductors 20a and 20b are respectively formed on the substrates 2A and 2B and an anisotropic conductive bonding agent 12 is inserted between the conductors 20a and 20b to form a multilayer structure. In this case, the conductors 20a and 20b are in a state that they are insulated from each other via the film 10. There, when a pressure F is applied between the substrates 2A and 2B to compress the bonding agent 12, heat is applied and the compressed state of the agent 12 is fixed, connecting pieces are constituted of the filler 14 contained in this agent 12 and conductor circuits are formed between the substrates 2A and 2B. Thereby, the connection between the built-in component and the wiring conductors 20a and 20b can selectively be made possible.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

この発明は、IC1抵抗、コンデンサ等の各種の電子部
品を内蔵した部品内蔵多層基板に関する。
The present invention relates to a component-embedded multilayer board that incorporates various electronic components such as IC1 resistors and capacitors.

【従来の技術】[Conventional technology]

従来、多層基板を形成する多層化には、シート積層法、
多層印刷法、厚膜多層法等がある。シート積層法は、セ
ラミックで形成されたグリーンシートに導体を印刷配線
して積み重ねて多層化し、多層印刷法は、グリーンシー
トに導体を印刷し、その上に絶縁層を印刷し、再び印刷
配線を施し、スルーホールを通して眉間を連結し、これ
らの工程を繰り返して多層化するものである。また、厚
膜多層法は、アルミナ基板に厚膜導体を印刷配線し、そ
の上に結晶化ガラスを重ねて印刷し、その上に導体を印
刷配線して眉間をスルーホールで連結し、これらの工程
を繰り返すことにより多層化する方法である。
Conventionally, sheet lamination method,
There are multilayer printing methods, thick film multilayer methods, etc. The sheet lamination method prints conductors on green sheets made of ceramic and stacks them to create a multilayer structure.The multilayer printing method prints a conductor on a green sheet, prints an insulating layer on top of it, and prints the printed wiring again. The glabella is connected through a through hole, and these steps are repeated to create multiple layers. In addition, the thick film multilayer method prints and wires a thick film conductor on an alumina substrate, prints crystallized glass on top of it, prints and wires the conductor on top of that, and connects the eyebrows with a through hole. This is a method of creating multiple layers by repeating the process.

【発明が解決しようとする課題】[Problem to be solved by the invention]

ところで、これらの多層化技術は、グリーンシートやア
ルミナ基板に導体又は絶縁物を印刷し、それを繰り返す
ことによって多層化するものであり、印刷導体を用いた
ものである。このような印刷技術−を用いた多層化は、
その製造工程が複雑化するとともに、多層化のための印
刷設備を必要とし、設備が大掛かりとなる欠点がある。 また、このような多層化技術を以て多層基板が構成され
た場合、その多層基板に形成されている導体回路の一部
を変更し、或いは実装されている特定の素子と配線導体
とを選択することは不可能である。即ち、特定のニーズ
に対応した回路装置では、僅かの定数変更であったとし
ても、新たに回路設計を行う必要がある。 そこで、この発明は、極めて簡単に多層化を実現すると
ともに、内蔵部品と配線導体との接続を選択可能にした
部品内蔵多層基板の提供を目的とする。 1課題を解決するための手段】 即ち、この発明の部品内蔵多層基板は、導電フィラーを
含有する異方性導電膜が持つ選択的な導電特性を利用し
たものであって、対向して配置される第1及び第2の基
板(2A、2B)と、これら基板の何れか一方又は双方
に設置される回路部品(ペアチップ6、チップ部品71
.72)と、前記第1又は第2の基板に設置されて前記
回路部品の電極(61,62=・6n、711.712
.721.722)と接続すべき配線導体(4,21,
22・・・2n)と、前記第1の基板と前記第2の基板
間に挟み込まれて前記各基板間を接合するとともに、含
有している導電フィラー(14)を以て前記回路部品の
前記電極と前記配線導体との間又は前記配線導体間を選
択的に接続する異方性導電膜(10)とを備えてなるも
のである。
By the way, these multilayering techniques print conductors or insulators on green sheets or alumina substrates, and repeat this process to form multiple layers, and use printed conductors. Multilayering using such printing technology is
The manufacturing process is complicated, and printing equipment for multilayering is required, which has the drawback of requiring large-scale equipment. In addition, when a multilayer board is constructed using such multilayer technology, it is necessary to change a part of the conductor circuit formed on the multilayer board, or to select specific elements and wiring conductors mounted on the multilayer board. is impossible. That is, in a circuit device that meets specific needs, it is necessary to perform a new circuit design even if the constants are only slightly changed. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a component-embedded multilayer board that can extremely easily realize multilayering and also allows selection of connections between built-in components and wiring conductors. [Means for Solving 1 Problem] That is, the component-embedded multilayer substrate of the present invention utilizes the selective conductive property of an anisotropic conductive film containing a conductive filler, first and second substrates (2A, 2B), and circuit components (pair chip 6, chip component 71) installed on either or both of these substrates.
.. 72) and the electrodes (61, 62=・6n, 711.712) of the circuit component installed on the first or second substrate.
.. 721, 722) and the wiring conductor (4, 21,
22...2n), which is sandwiched between the first substrate and the second substrate to bond the respective substrates, and is connected to the electrode of the circuit component using a conductive filler (14) contained therein. It is provided with an anisotropic conductive film (10) selectively connecting between the wiring conductors or between the wiring conductors.

【作   用】[For production]

導電フィラーを含有する異方性導電膜は、加圧すること
により、加圧された箇所の導電フィラー間が選択的に導
通し、局所的な導体回路を構成することができる。 したがって、この発明では、対向して配置される第1及
び第2の基板の間に挟み込まれて各基板間を接合する異
方性導電膜を設置したので、その異方性導電膜に含まれ
ている導電フィラーを以て回路部品の電極と配線導体と
を選択的に接続することができる。
When an anisotropic conductive film containing a conductive filler is pressurized, electrical conduction is selectively established between the conductive fillers at the pressurized portions, thereby forming a local conductor circuit. Therefore, in this invention, since an anisotropic conductive film is provided which is sandwiched between the first and second substrates disposed facing each other and connects each substrate, the anisotropic conductive film contains The electrodes of the circuit component and the wiring conductor can be selectively connected using the conductive filler.

【実 施 例】【Example】

以下、この発明を図面に示した実施例を参照して詳細に
説明する。 第1図は、この発明の部品内蔵多層基板(以下「多層基
板」という)の一実施例を示す。 この多層基板には、セラミックのグリーンシート等の可
撓性を持つ第1及び第2の基板2A、2Bが設置され、
各基板2A、2Bは、対向して配置されている。基板2
Aには、配線導体4が印刷等の方法によって形成され、
その上に内蔵すべき回路部品として半導体回路装置であ
るペアチップ6が設置され、このペアチップ6を取り囲
む部分には、絶縁層8が印刷等の方法によって形成され
ている。 ペアチップ6は、多数のトランジスタ、抵抗等が内蔵さ
れたICであって、その上面部には、第2図に示すよう
に、内蔵回路との電気的な接続を行うための複数の電極
61.62.63・・・6nが形成されている。 基板2Bの対向面側には、ペアチップ6の各電極61.
62.63・・・6nに対応する複数の配線導体21.
22.23・・・2nが設置され、これらの配線導体2
1.22.23・・・2nは導体印刷等の方法によって
形成されている。 そして、基板2A、2Bの対向面間には、異方性導電膜
10が挟み込まれ、この異方性導電膜10は異方性導電
接着剤12で形成されている。この異方性導電接着剤1
2には、異方性導電性を付与するための導電フィラー1
4が含有されている。 以上の構成によれば、基板2A、2B間に異方性導電膜
10を挟み込んで一つの多層基板を構成しており、ペア
チップ6の各電極61.62.63・・・6nと配線導
体21.22.23・・・2nとの間に導電フィラー1
4を含む異方性導電膜10が挟み込まれている。 ところで、第3図の(A)に示すように、基板2A、2
Bに配線導体20a、20bを形成し、その間に異方性
導電接着剤12を挟み込んで多層化構造を形成する。こ
の場合、基板2A、2B間に挟まれた異方性導電接着剤
12は、定常状態ではその内部に含有する各導電フィラ
ー14は互いに離間した状態にあるので、配線導体20
a、20bは異方性導電膜10を介して互いに絶縁状態
となる。 そこで、第3図の(A)に示すように、基板2A、2B
間に圧力Fを加えて異方性導電接着剤12を圧縮し、熱
を加えてその圧縮状態を固定すると、この異方性導電接
着剤12に含まれている導電フィラー14は、第3図の
(A)に示す絶縁状態から第3図の(B)に示すように
、接続手を構成して互いに導通し合い、基板2A、2B
間に導体回路を形成することになる。 したがって、このような異方性導電接着剤12で形成さ
れた異方性導電膜10を挟み込まれた第1図に示す多層
基板では、対応箇所を加圧し、熱を加えてその圧縮状態
を固定することにより、ペアチップ6の各電極61.6
2.63・・・6nと配線導体21.22.23・・・
2nとの間に異方性導電膜10の導電フィラー14を以
て導体回路が形成され、その導体回路を介して電気的に
接続されることになる。 このような異方性導trioによる導体回路は、従来の
印刷や半田付けによる接続に比較してその作業が簡単で
あり、加圧箇所の選択によって接続箇所を任意に設定で
きる等の利点がある。 次に、第4図及び第5図は、この発明の部品内蔵多層基
板の他の実施例を示す。 前記実施例では内蔵すべき回路部品として比較的大型の
ペアチップ6を用いた場合について説明したが、第4図
及び第5図に示す実施例では、内蔵部品としてチップ電
解コンデンサやチップ抵抗等のチップ部品71.72を
用いたものである。 第5図に示すように、基板2A、2Bの対向面側に選択
的に配線導体201.202.203.204.205
.206が形成され、配線導体201.2020間には
第1のチップ部品71が設置されてその電極711.7
12が接続され、また、配線導体205.206の間に
は第2のチップ部品72が設置されてその電極721.
722が接続されている。この実施例では、各チップ部
品71.72が互いに重ならないように配置されて、多
層基板の厚さ調整が回られている。 そして、各基板2A、2Bの間には、異方性導電膜10
が異方性導電接着剤12によって形成され、基板2A、
2Bの圧接により異方性導電膜10に含まれている導電
フィラー14によって導体回路が形成されている。即ち
、この実施例では、配線導体201と配線導体204、
配線導体202と配線導体205、配線導体203と配
線導体206がそれぞれ導電フィラー14を以て電気的
に接続され、基板2A、2Bの間に内蔵されたチップ部
品71.72が配線導体203と配線導体204との間
に直列接続されている。 このように、複数の内蔵部品を、基板2A、2B間に挟
み込んだ異方性導電膜10を以て電気的に接続すること
ができ、簡易な接続構造を持つ多層基板を容易に形成で
き、内蔵電子部品や多層基板に実装すべき部品の実装密
度の向上を図ることができる。 なお、実施例では、内蔵部品としてペアチップやチップ
部品を例に取って説明したが、この発明の部品内蔵多層
基板は、その他の内蔵電子部品の電気的接続により多層
基板を構成する場合にも適用できるものである。 また、実施例では、2枚の基板を用いた場合について説
明したが、この発明の部品内蔵多層基板は、3枚以上の
基板を積層する場合にも通用できるものである。
Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. FIG. 1 shows an embodiment of a component-embedded multilayer board (hereinafter referred to as "multilayer board") of the present invention. First and second flexible substrates 2A and 2B such as ceramic green sheets are installed on this multilayer substrate,
Each substrate 2A, 2B is arranged facing each other. Board 2
A wiring conductor 4 is formed by a method such as printing,
A pair chip 6, which is a semiconductor circuit device, is placed thereon as a circuit component to be built in, and an insulating layer 8 is formed in a portion surrounding the pair chip 6 by a method such as printing. The pair chip 6 is an IC with a large number of transistors, resistors, etc. built-in, and as shown in FIG. 2, the pair chip 6 has a plurality of electrodes 61 . 62, 63...6n are formed. Each electrode 61 . of the paired chip 6 is provided on the opposing surface side of the substrate 2B.
A plurality of wiring conductors 21.62, 63...6n correspond to the plurality of wiring conductors 21.
22, 23...2n are installed, and these wiring conductors 2
1,22,23...2n are formed by a method such as conductor printing. An anisotropic conductive film 10 is sandwiched between the opposing surfaces of the substrates 2A and 2B, and the anisotropic conductive film 10 is made of an anisotropic conductive adhesive 12. This anisotropic conductive adhesive 1
2 contains a conductive filler 1 for imparting anisotropic conductivity.
Contains 4. According to the above configuration, the anisotropic conductive film 10 is sandwiched between the substrates 2A and 2B to constitute one multilayer substrate, and each electrode 61, 62, 63...6n of the paired chip 6 and the wiring conductor 21 .22. Conductive filler 1 between 23...2n
An anisotropic conductive film 10 including 4 is sandwiched therebetween. By the way, as shown in FIG. 3(A), the substrates 2A, 2
Wiring conductors 20a and 20b are formed on B, and an anisotropic conductive adhesive 12 is sandwiched between them to form a multilayer structure. In this case, in the anisotropic conductive adhesive 12 sandwiched between the substrates 2A and 2B, the conductive fillers 14 contained therein are in a state separated from each other in a steady state, so that the wiring conductor 20
a and 20b are insulated from each other via the anisotropic conductive film 10. Therefore, as shown in FIG. 3(A), the substrates 2A and 2B are
When the anisotropic conductive adhesive 12 is compressed by applying a pressure F between the two and the compressed state is fixed by applying heat, the conductive filler 14 contained in the anisotropic conductive adhesive 12 becomes as shown in FIG. From the insulated state shown in (A) of FIG. 3, as shown in (B) of FIG.
A conductive circuit will be formed between them. Therefore, in the multilayer substrate shown in FIG. 1 in which the anisotropic conductive film 10 formed with such an anisotropic conductive adhesive 12 is sandwiched, the compressed state is fixed by pressurizing the corresponding parts and applying heat. By doing this, each electrode 61.6 of the paired chip 6
2.63...6n and wiring conductor 21.22.23...
2n, a conductive circuit is formed using the conductive filler 14 of the anisotropic conductive film 10, and electrical connection is made via the conductive circuit. Conductor circuits using such an anisotropic conductor trio are easier to work with than conventional connections by printing or soldering, and have the advantage that the connection points can be set arbitrarily by selecting the pressure points. . Next, FIGS. 4 and 5 show other embodiments of the component-embedded multilayer board of the present invention. In the embodiment described above, a relatively large pair chip 6 was used as the circuit component to be built-in, but in the embodiment shown in FIGS. 4 and 5, a chip such as a chip electrolytic capacitor or a chip resistor is used as the built-in component. Parts 71 and 72 are used. As illustrated in FIG.
.. 206 is formed, and the first chip component 71 is installed between the wiring conductors 201.2020 and its electrodes 711.7.
12 are connected, and a second chip component 72 is installed between the wiring conductors 205 and 206, and its electrodes 721 .
722 is connected. In this embodiment, the chip components 71 and 72 are arranged so as not to overlap each other, and the thickness of the multilayer board is adjusted. An anisotropic conductive film 10 is provided between each substrate 2A and 2B.
is formed by an anisotropic conductive adhesive 12, and the substrate 2A,
A conductor circuit is formed by the conductive filler 14 contained in the anisotropic conductive film 10 by press-welding 2B. That is, in this embodiment, the wiring conductor 201, the wiring conductor 204,
The wiring conductor 202 and the wiring conductor 205, and the wiring conductor 203 and the wiring conductor 206 are electrically connected by the conductive filler 14, respectively, and the chip components 71 and 72 built in between the substrates 2A and 2B are connected to the wiring conductor 203 and the wiring conductor 204. are connected in series. In this way, a plurality of built-in components can be electrically connected using the anisotropic conductive film 10 sandwiched between the substrates 2A and 2B, and a multilayer board with a simple connection structure can be easily formed. It is possible to improve the mounting density of components and components to be mounted on a multilayer board. Although the embodiments have been explained using paired chips and chip components as built-in components, the component-embedded multilayer board of the present invention can also be applied to the case where a multilayer board is constructed by electrically connecting other built-in electronic components. It is possible. Further, in the embodiment, the case where two substrates are used has been described, but the component-embedded multilayer substrate of the present invention can also be used when three or more substrates are stacked.

【発明の効果】【Effect of the invention】

以上説明したように、この発明によれば、第1及び第2
の基板間に任意の回路部品とともに異方性導電膜を設置
し、その回路部品の電極と第1又は第2の基板に形成さ
れている配線導体との電気的な接続を異方性導電膜を通
して選択的に行うようにしたので、任意の回路部品を内
蔵し、異方性導電膜を以て必要な電気的な接続を行った
種々の回路形態を持つ多層基板を提供することができる
As explained above, according to the present invention, the first and second
An anisotropic conductive film is installed together with any circuit components between the two substrates, and electrical connections between the electrodes of the circuit components and the wiring conductors formed on the first or second substrate are made using the anisotropic conductive film. Since this is selectively performed through the conductive layer, it is possible to provide multilayer substrates having various circuit configurations in which arbitrary circuit components are incorporated and necessary electrical connections are made using the anisotropic conductive film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の部品内蔵多層基板の一実施例を示す
断面図、 第2図は第1図に示した部品内蔵多層基板におけるペア
チップを示す斜視図、 第3図は第1図に示した部品内蔵多層基板の異方性導電
膜による導体回路の形成を示す図、第4図はこの発明の
部品内蔵多層基板の他の実施例を示す断面図、 第5図は第4図に示した部品内蔵多層基板の製造方法を
示す断面図である。 2A・・・第1の基板 2B・・・第2の基板 4・・・配線導体 6・・・ペアチップ(回路部品) 10・・・異方性導電膜 14・・・導電フィラー 21.2:l =2n、20a、20b、20L 20
2.203.204.205.206・・配線導体 61.62・・・6n、711.712.721.72
2・・・電極 71.72・・・チップ部品(回路部品)しF
FIG. 1 is a sectional view showing an embodiment of the component-embedded multilayer board of the present invention, FIG. 2 is a perspective view showing a pair of chips in the component-embedded multilayer board shown in FIG. 1, and FIG. 3 is the same as shown in FIG. FIG. 4 is a cross-sectional view showing another embodiment of the component-embedded multilayer board of the present invention, and FIG. FIG. 2 is a cross-sectional view showing a method of manufacturing a component-embedded multilayer board. 2A... First substrate 2B... Second substrate 4... Wiring conductor 6... Pair chip (circuit component) 10... Anisotropic conductive film 14... Conductive filler 21.2: l = 2n, 20a, 20b, 20L 20
2.203.204.205.206...Wiring conductor 61.62...6n, 711.712.721.72
2... Electrode 71.72... Chip parts (circuit parts) F

Claims (1)

【特許請求の範囲】  対向して配置される第1及び第2の基板と、これら基
板の何れか一方又は双方に設置される回路部品と、 前記第1又は第2の基板に設置されて前記回路部品の電
極と接続すべき配線導体と、 前記第1の基板と前記第2の基板間に挟み込まれて前記
各基板間を接合するとともに、含有している導電フィラ
ーを以て前記回路部品の前記電極と前記配線導体との間
又は前記配線導体間を選択的に接続する異方性導電膜と
、 を備えてなる部品内蔵多層基板。
[Scope of Claims] A first and a second board disposed facing each other, a circuit component installed on one or both of these boards, and a circuit component installed on the first or second board and the circuit component installed on the first or second board. A wiring conductor to be connected to an electrode of a circuit component; and a wiring conductor that is sandwiched between the first substrate and the second substrate to bond the substrates, and a conductive filler contained therein to connect the electrode of the circuit component. and an anisotropic conductive film selectively connecting between the wiring conductor and the wiring conductor.
JP2183237A 1990-07-11 1990-07-11 Multilayer board provided with built-in component Pending JPH0471297A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2183237A JPH0471297A (en) 1990-07-11 1990-07-11 Multilayer board provided with built-in component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2183237A JPH0471297A (en) 1990-07-11 1990-07-11 Multilayer board provided with built-in component

Publications (1)

Publication Number Publication Date
JPH0471297A true JPH0471297A (en) 1992-03-05

Family

ID=16132177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2183237A Pending JPH0471297A (en) 1990-07-11 1990-07-11 Multilayer board provided with built-in component

Country Status (1)

Country Link
JP (1) JPH0471297A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6625037B2 (en) 1997-11-25 2003-09-23 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method manufacturing the same
KR100406447B1 (en) * 1999-12-30 2003-11-20 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6625037B2 (en) 1997-11-25 2003-09-23 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method manufacturing the same
US7068519B2 (en) 1997-11-25 2006-06-27 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method manufacturing the same
KR100406447B1 (en) * 1999-12-30 2003-11-20 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method

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