JPH0467665B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output port, and particularly to an input/output port configured with complementary field effect transistors (hereinafter referred to as CMOS).

[Conventional technology]

Figure 3 is a basic configuration diagram of CMOS. CMOS
is a P-channel field effect transistor (hereinafter referred to as
(hereinafter referred to as PMOS) 21 and an N-channel field effect transistor (hereinafter referred to as NMOS) 22 are complementarily connected in series. When the input voltage V _IN is at the ground voltage level (hereinafter referred to as low level),
PMOS21 is conductive, NMOS22 is conductive, and the output voltage V _OUT is at the power supply voltage level (hereinafter referred to as high level). On the other hand, when the input voltage V _IN is high level, PMOS21 is conductive, NMOS22 is conductive, and the output voltage V _OUT becomes low level.
This operates as a so-called inverter circuit.

FIG. 4 is a graph showing the input/output characteristics of the CMOS inverter circuit shown in FIG. In the stable state of the CMOS circuit (periods a and c),
Both PMOS21 and NMOS22 are never in a conductive state, and PMOS21 and NMOS22 are not connected to each other from the power supply.
No current flows to GND through NMOS22 and NMOS22 in series. Therefore, a major feature of CMOS circuits is low power consumption during stable operation.
However, in the transition state (period b) where the input and output voltages V _IN and V _OUT change from high level to low level or from low level to high level, the current that charges and discharges the load capacitance from the output to the input of the next stage circuit is , both PMOS21 and NMOS22 become conductive, so PMOS21 is disconnected from the power supply.
There is a current (hereinafter referred to as a through current) that flows through the NMOS 22 and GND in series. In a CMOS circuit, the charging/discharging current and shoot-through current of the load capacitor account for most of the power consumption, and particularly in circuits where the conductive state resistance is reduced to increase the charge/discharge ability of the load capacitor, a large shoot-through current flows.

By the way, in microcomputers and the like that have built-in input/output ports constructed from semiconductor integrated circuits, input/output ports in which the same pin can be switched between input mode and output mode are often used, mainly for the purpose of reducing the number of pins.

FIG. 2 is a circuit diagram of a conventional example of an input/output port configured with this type of CMOS.

In the output mode, when the address signal A goes high and the write signal W goes high, the output of the two-input AND gate 3a goes high, and the data on the bus is stored in the latch circuit 5. Since the input/output switching signal C is at a low level, the output of the inverter 11 becomes a high level, and the output buffer 6 and transfer gate 4 are turned on. Therefore, the data stored in the latch circuit 5 is outputted to the input/output terminal 7 via the output buffer 6, and at the same time is outputted to the node 14 via the transfer gate 4. In the output mode, the data stored in the latch circuit 5 can be outputted to the bus via the transfer gate 4 and the bus driver 13 as necessary, but the transfer gate 4 can be omitted if it is not necessary. In addition, in the input mode, the input/output switching signal C is set to high level and the output of the inverter 11 becomes low level, so the output buffer 6 is turned off and the input buffer 8 is turned on, so that the input to the input/output terminal 7 Data is output to node 14 via input buffer 8.
Then, when the address signal A becomes high level and the read signal R becomes high level, the output of the two-input AND gate 10 becomes high level, the bus driver 13 is turned on, and the data at the node 14 is transferred to the bus driver 13. output to the bus via Input/output operations are performed in this manner.

FIG. 5 is a circuit diagram of the bus driver 13 constructed of CMOS and shown in FIG. 2. Input E is the second
The input from node 14 in the figure, control input signal D, is the second
This is the input from the two-input AND gate 10 in the figure.
Output F is the output of the bus.

When the control input signal D is low level, the output of the inverter 27 is high level, and the PMOS 24
The NMOS 25 is cut off, and the output F becomes a high impedance state that is not connected to either the power supply or GND, regardless of the input E. Furthermore, when the control input signal D is high level, the output of the inverter 27 is low level, and the PMOS 24 and NMOS
25 conducts, PMOS23, PMOS24,
NMOS25 and NMOS26 operate as an inverter that receives the output of inverter 28 as input. Usually, the bus includes a microcomputer, etc.
Many circuits such as arithmetic section, register section, port section etc. are connected, and the load capacity seen from the bus driver is large, PMOS23, PMOS24, NMOS25,
The NMOS 26 is designed to have low resistance in a conductive state in order to increase the charging and discharging ability of the load capacitance.

[Problem that the invention seeks to solve]

In the conventional input/output port described above, when an intermediate level between a high level and a low level is input to the input/output terminal in the input mode, the input buffer enters a transition state and a through current flows through the input buffer. Since the output is at an intermediate level between a high level and a low level, the bus driver also enters a transition state, and there is a drawback that a through current flows through the bus driver.

The through current flowing through the input buffer is smaller than that of a bus driver because the load capacity of the input buffer is small and the input buffer's conduction state resistance can be set to a large value, so it has less of an effect. To increase performance, the conductive state resistance is small, and a large through current flows, causing increased power consumption and noise to the power supply and GND.

An object of the present invention is to provide an input/output port in which the through current flowing through a bus driver is reduced by simply adding a simple circuit.

[Means for solving problems]

The input/output port of the present invention is connected between an input/output terminal, a latch circuit that latches data from the input/output terminal or the bus, and the latch circuit and the bus, and is turned on when the input/output switching signal indicates an output mode; A transfer gate that turns off when the input/output switching signal indicates the input mode, and an input buffer that outputs the input from the input/output terminal to the latch circuit without going through the transfer gate when the input/output switching signal indicates the input mode. , an output buffer that outputs the output from the latch circuit to the input/output terminal when the input/output switching signal indicates output mode, and an output buffer that outputs the output from the latch circuit to the bus when both the address signal and read signal are input. Being a bus driver,
The bus driver is configured such that a through current flows between the power supplies when an intermediate level between a logic "1" level and a logic "0" level is input, and an input/output switching signal is set in an input mode. When the input/output switching signal indicates the output mode, the clock signal input from the outside is output as the latch circuit clock signal, and when the address signal and write signal are both input, the clock signal is output to the latch circuit. It has a clock signal generation circuit.

In this way, in the input mode, the output of the input buffer is once latched in the latch circuit and then output to the bus by the bus driver, so that when an intermediate level is input to the input buffer, the intermediate level becomes high level or low level. The current is amplified and the through current is prevented from flowing through the bus driver. Note that a transfer gate is provided to prevent the data on the bus from being latched into the latch circuit during the input mode, and an external clock is provided to prevent the data on the bus from being latched to the latch circuit during the input mode. is used.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the input/output port of the present invention.

The input of the latch circuit 5 for storing data is connected to the bus via the transfer gate 4 and to the input/output terminal 7 via the input buffer 8. Further, the output of the latch circuit 5 is sent to the bus via the bus driver 9, and is sent to the input/output terminal 7 via the output buffer 6.
connected to. The clock signal of the latch circuit 5 is the AND of the input/output switching signal C (high level in input mode, low level in output mode) and the periodically generated clock signal T input from an external device such as a microcomputer. Output of AND gate 2, address signal A and write signal W
OR gate 1 which takes the logical sum of the output of the 3-input AND gate 3 which takes the logical product of the output of the inverter 11, and the output of the inverter 11
is obtained as the output of Therefore, in the input mode, the clock signal T inputted from the outside is output as it is as a clock signal, and in the output mode, the logical product of the address signal A and the write signal W becomes the clock signal. Further, the output buffer 6 is controlled by the output of the inverter 11 which inputs the input/output switching signal C, the input buffer 8 is controlled by the input/output switching signal C, and the bus driver 9 is controlled by the logic of the address signal A and the read signal R. Controlled by the output of the AND gate that takes the product. Note that the clock signal T and the read signal R are in a relationship such that they do not go to high level at the same time.

Next, the circuit operation of this embodiment will be explained.

In the output mode, the input/output switching signal C is at a low level, the output of the inverter 11 is at a high level, and the transfer gate 4 and output buffer 6 are on. When the address signal A goes high and the write signal W goes high, the output of the 3-input AND gate 3 goes high, the output of the 2-input OR gate 1 goes high, and the data on the bus is transferred. It is stored in the latch circuit 5 via the argate 4. Furthermore, the data stored in the latch circuit 5 is outputted to the input/output terminal 7 via the output buffer 6. In the input mode, the input/output switching signal C is high level, and the inverter 11
The output is at low level. Therefore, the output buffer 6 and transfer gate 4 are turned off, and the input buffer 8 is turned on. The data input to the input/output terminal 7 is passed through the input buffer 8, and when the periodically generated clock signal T is at a high level, the 2-input AND gate 2 is at a high level.
The two-input OR gate 1 becomes high level and is stored in the latch circuit 5. Furthermore, address signal A
is at a high level and the read signal R is at a high level, the output of the two-input AND gate 10 becomes a high level, the bus driver 9 is turned on, and the data stored in the latch circuit 5 is transferred via the bus driver 9. output to the bus. Input/output operations are performed in this manner, and the latch circuit 5 for storing data is used both in the input mode and in the output mode.

〔Effect of the invention〕

As explained above, in the present invention, in the input mode,
After the output of the input buffer is latched in a latch circuit, the bus driver outputs it to the bus. When an intermediate level is input to the input buffer, the intermediate level is amplified to a high level or low level, causing a through current to the bus driver. This has the effect of preventing an increase in power consumption due to through current and noise in the power supply and GND.

[Brief explanation of the drawing]

Figure 1 is a block diagram of one embodiment of the input/output port of the present invention, Figure 2 is a block diagram of a conventional example, Figure 3 is a circuit diagram of an inverter configured with CMOS, and Figure 4 is the same as that of Figure 3. FIG. 5 is a graph showing the input/output characteristics of the inverter circuit, and is a circuit diagram of a bus driver configured with CMOS. 1...2 input OR gate, 2,10...2 input AND gate, 3...3 input AND gate, 4...
...Transfer gate, 5...Latch circuit, 6
...Output buffer, 7...Input/output terminal, 8...Input buffer, 9...Bus driver, 11...Inverter, T...Clock signal, W...Write signal, R...Read signal, A... Address signal.

Claims (1)

[Claims] 1. An input/output terminal, a latch circuit that latches data from the input/output terminal or the bus, and a latch circuit connected between the latch circuit and the bus, which turns on when the input/output switching signal indicates an output mode, A transfer gate that turns off when the input/output switching signal indicates input mode, and an input buffer that outputs the input from the input/output terminal to the latch circuit without going through the transfer gate when the input/output switching signal indicates input mode. and an output buffer that outputs the output from the latch circuit to the input/output terminal when the input/output switching signal indicates output mode, and an output buffer that turns on when both the address signal and read signal are input and outputs the output from the latch circuit to the bus. a bus driver configured to cause a through current to flow between power supplies when an intermediate level between a logic "1" level and a logic "0" level is input; When the input/output switching signal indicates the input mode, the clock signal input from the outside is output as it is as the clock signal of the latch circuit, and when the input/output switching signal indicates the output mode, the latch is activated when both the address signal and the write signal are input. An input/output port that has a clock signal generation circuit that outputs a clock signal to the circuit.