JPH046675A - Error correcting device - Google Patents

Abstract

PURPOSE:To reduce the probability of miscorrection by checking whether corrected 8-bit data is included in a regulated level or not and correcting the data when they are in the regulated range, or deciding the generation of an error exceeding the capacity of the device in the case of the outside of the range. CONSTITUTION:Corrected data are inputted to an image data deciding circuit 109 and a delay circuit III 111 for delaying the data only by processing time corresponding to code length. The circuit 109 checks whether the corrected image data, i.e. all 8-bit data corresponding to W31 to W4 satisfy 15<=Wi<=283 (i=4 to 31) or not. If any one of those words does not satisfy the condition, a result that the number of error words is more than the correcting capacity is decided. In this case, a decision signal is outputted from the circuit 109, a data selection circuit 112 is switched and the decision signal is outputted from a data output terminal 113 together with a correction disabled flag '1'. Consequently, the probability of correcting reproduced data in error can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an apparatus for recording and reproducing digital signals on and from a recording medium.

(b) Prior Art Recently, with the progress of IC technology and high-density recording technology, development of digital recording and reproducing devices for consumer equipment has been progressing in the audio field as well as the video field.

In such digital recording and reproducing apparatuses or digital signal reproducing apparatuses, error correction codes are indispensable. As an error correction code, Reed-Solomon code (R5 code) is theoretically organized and has high coding efficiency.
is often used. This code can be corrected in units of multiple bits, and is generally used in units of 8 bits. Here, as an example, one used in a CD (compact disc) will be explained. Japanese Patent Application Publication No. 5
No. 7-10560 (I (04L 1/10)) describes a method for decoding Reed-Solomon codes applied to CDs.

CD is a Reed-Solomon code RS (28,24) with a code length of 28 and an inter-code distance of 5 as a C2 series code, and a Reed-Solomon code R with a code length of 32 and an inter-code distance of 5 as a C1 series code.
S (32,28) is used. During decoding, C1 first corrects random errors, and the correction results are used to correct burst errors in C2. The present invention is not directly related to the decoding algorithm based on such a combination of CI and C2, so for the sake of simplicity, only the portion corresponding to CI correction will be explained.

In the case of CD, C1 has 24 symbols (one symbol is 8
audio data of 4 symbols of C2 parity (C bit), 4 symbols of C2 parity (C
(already generated before 2 generation), 01 parity of 4 symbols is generated. Here, 24 symbols of audio data are Wl,,W,. ,...,W, and the 02 parity of 4 symbols is W,,W,,W,.

W, close, Cl parity to be generated now P 3+ P
,.

When P l + P, the following formula is satisfied.

Here, α is the primitive polynomial F(x)=x”x
'ten x ''+ x ''+ 1 root, e is mod
This is 2 additions.

The following margin is (7,=Σ α33−Il″W, υ=0.1,2
．． 3) However, Σ is mod 2 addition.

At the time of recording, P, .about.Po are calculated from the input audio data (upper and lower 8 bits) using the formula 12], and are recorded on the disc in a predetermined format.

During playback, the played data is w,,'.

W. + W2 I'+...,P,',P,'
, P,°, P0゛, and by calculating the left side of equation (1), syndromes 80 to S are obtained.

Margin below II II II -Q+　　2 phrase d 　e　e 2-0.

(Phrase ((II II II II Prisoner ω Sword ω) Here, it is assumed that a two-word error has occurred, the error location is a″αノ, and the error patterns are e8 and eJ, respectively.

At this time, the following formula holds true.

5, = a”e, (f) a”e.

(Using formula 43 and transforming (S, 5=eSl")c1'flD(S, S, ΦS, S
,)α'tB(S,S,eS,")=O-[5]where S,S,!S,"=A,S,S,fE19s,s,
=B, s, s, es, ”=c ・・・・・・・・・
・・・・・・・・・ Leave it as [6]. Each coefficient A in the above formula,
By using B and C, corrections of 2 words or less can be performed.

(1) If there is no error, f=Bs7ε is 0. ...[7](
2) In case of 1 word error is:,,”070S2♀o car*it6゜−[8
] At this time, error location a'=s, /S.

Error pattern et=sO It can be found by

(3) In the case of a 2-word error, A≠O, B≠O, and C≠O hold true... (9) A a
”$B a 'eC= O==-=-[10] Here
If we set B/A=D, C/A=E...[11], then equation (7) becomes α"flpDα'19E=O...
・[12] From the relationship between roots and coefficients, D = ale α E = α1 α ... [13] Here, the difference between the two error locations is l(t〉), that is, j = i + t. Then, D=α'(ICDα'), E=a '''' --[1
4]. Therefore, D''/E=(leα')'/α'=α−'CE)α' Then, t=1.2.3..., k (=31 in case of 01 code of CD) It is sufficient to calculate D''/E for each of , use the value of D''/E as the ROM address input, and output the corresponding t. If there is no corresponding t, then 3 Error of one word or more.

Next, by setting X = 1 ea ' Y = 1 @ a -' = D ''/EeX, α ' = D / X, α = D / Y ...
(15), and error locations i and j can be found. The error pattern can be obtained as ...... [16].

In this way, errors of 2 words or less can be correctly corrected.

However, an error of 3 or more words may be incorrectly corrected as an error of 2 or less words. When making corrections, the number of error words is determined using the conditional expression described above, so
If there is an error of 3 or more words that satisfies any of the conditional expressions, it is treated as an error of 2 words or less. but,
In this case, when the error location is finally determined, if the error location exceeds the code length (for example, i or, ? > 31 in CD C1 code), 3
It can be identified as an error of one word or more. If it falls within the code length (i and j≦31), it will be incorrectly corrected.

(c) Problems to be Solved by the Invention The present invention aims to reduce the probability of erroneous correction by using Reed-Solomon codes with equal code lengths and inter-code distances.

(d) Means for Solving the Problems The present invention attempts to reduce the probability of erroneous correction by determining not only the error location but also the data after correction results (excluding parity). however,
When applying the present invention, there must be unused words (data patterns). One application example is a VTR that digitally records a video signal (y-c signal 8 bits/sample) obtained by de-emphasizing and inversely transmitting and gamma-processing the MUSE signal. The video signal just described is 8-bit data with specified levels "15" to "2".
The probability of erroneous correction can be reduced by paying attention to the fact that the 8-bit video data is within this range and checking whether all of the corrected 8-bit video data falls within this range.

(E) Function According to the present invention, when correcting an error, it is checked whether the corrected 8-bit data falls within the specified level "15" to "238", and if it is within the specified range, it is corrected, and the data is corrected. By determining that the error is beyond the ability, the probability of erroneous correction can be reduced. This makes it possible to further improve the reliability of reproduced image data.

(f) Example An example of carrying out the present invention will be described with reference to FIGS. 1 and 2. The embodiment relates to a MUSE digital VTR which performs appropriate shuffling processing on 8-bit/sample data obtained by de-emphasizing and inversely transmitting gamma processing a MUSE video signal (Y/C) and then digitally records the data. FIG. 2 shows the structure of one code word recorded at this time. In Figure 2, as an example, RS (32,2
8), but other than this inversion, the code length or inter-code distance may be arbitrarily set. In Figure 2,
W 31 , W 3°, ..., Wb, W4 are video signals of 8 pits/sample each, and have a specified level "
It falls within the range of 15'' to 238'. Pj.

..., Po are parity words (8 bits each). These parity words are recorded on the recording medium according to the above-mentioned format [generated by Equation 21 and predetermined].

During reproduction, this code word is reproduced and stored in a memory circuit such as a RAM. The data are read out from a storage circuit such as a RAM in the order of the arrow direction in FIG. 2 and input to the input terminal (101) of the correction circuit shown in FIG. The input data is input to the syndrome generation circuit (102), and (3)
According to the formula, the syndrome s,, s,, s,,
s is calculated. The input data is also input to the delay circuit I (103) and delayed by the time required to calculate the error location and error pattern.

After calculating the syndromes s , s , s , s , the number of error words is determined by the error word number determination circuit (104). Here [7][81[
The number of error words is determined based on the conditional expression [9].

According to this information on the number of error words, the error location is calculated by the error location calculation circuit (105). At this time, the error location is a when there is an error in one word, and α when it is an error in two words.

If α1 is calculated, this result is sent to the error location determination circuit (106). In the error location determination circuit (106), i is 0 when there is a 1 word error.
≦i≦31, and when there is a 2-word error, i, 1, 0≦i
, j≦31, and if satisfied, it is determined that there is an 1-word error and a 2-word error, respectively. If you are satisfied, it will be an error of 3 words or more. The result determined by the error location determination circuit (106) is sent to the data correction circuit (108).

Using the error location determined by the error location calculation circuit (105) and the syndrome calculated by the syndrome generation circuit (102), the error pattern calculation circuit (107) generates an error pattern e i+ e.

(respective error patterns for error locations α', α) are calculated. The error location, error pattern, and error location determination result are input to the data correction circuit (108). Data correction circuit (108
) corrects the data by adding an error pattern mod 2 to the erroneous word (8-bit data) in time with the data output from the delay circuit I (103). Further, the output from the delay circuit I (103) bypasses the data correction circuit (108) and is input to the delay circuit IT (110). Delay circuit II (
110), the data correction circuit (108) and the delay circuit I
It is delayed by a time corresponding to the processing time of II (111).

The corrected data is input to the video data determination circuit (109) and also to the delay circuit H1 (111) which delays the data by a processing time corresponding to the code length. In the video data determination circuit (109), the video data after the correction process,
That is, in Fig. 2, all 8-bit data corresponding to W, 1 to W4 are 15≦W,≦283Ci=4°5, ., 31)
Check whether the conditions are satisfied. If even one word does not satisfy this requirement, it can be determined that the number of error words exceeds the correction ability. At this time, a judgment signal is output from the video data judgment circuit (109), and the data selector circuit (112) is switched to select the input from the delay circuit (110) (playback data without correction processing), and the data output terminal ( 113), it is output together with the uncorrectable flag 1''.On the contrary, all of W31-W4 of the corrected data are 15≦W.

When ≦238 (i=4.5..., 31) is satisfied, the data selector circuit (112) selects the corrected data and sends it to the data output terminal (11
3) is output.

The output data is subjected to the following processing along with the uncorrectable flag.

That is, in the video data judgment circuit (109), if even one word after data correction is out of a predetermined range,
When the determination result of the error location determination block (106) is that an error of 3 words or more is detected, the data selector (112) outputs a control signal to select the delay circuit TI (110).

In this way, by checking whether the corrected video data falls within the level range of "15" to "238" defined by the MUSE signal, the reliability of the reproduced data can be increased.

(G) Effects of the Invention As described above, according to the present invention, the probability of erroneously correcting reproduced data can be reduced in the error correction device.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing the structure of a code word showing an example of a Reed-Solomon code. 109...Video data judgment circuit

Claims (1)

[Claims] (1) Add an error correction code to N-bit data of a predetermined number of words and record it on a recording medium in a predetermined format,
An error correction device for a recording/playback device for playback, characterized in that the error correction device checks whether the output after error correction processing includes a non-existent data pattern, and changes the data processing method depending on the presence or absence of the data pattern. .