JPH0462641A - Multiprocessor system - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a multiprocessor system.

, (Prior Art) With the rapid advancement of information processing technology in recent years, the amount of information handled by computers has become enormous. One way to process this information as quickly and accurately as possible is to use a multiple multiprocessor system.

This multiplex multiprocessor system is a system in which a plurality of processors are each configured from a plurality of CPUs to multiplex the system, thereby increasing the speed of information processing and improving operational reliability.

In other words, in a multiplex multiprocessor system, each of the processors constituting the multiprocessor performs separate processing in parallel, thereby making it possible to process a large amount of information at one time. In addition, one processor has multiple CPUs, and by having all the CPUs that make up the processor perform the same processing and constantly comparing the results, it is possible to detect malfunctioning processors and processors. The aim is to improve reliability by not producing results.

In a normal system, when a faulty CPU is discovered, the processor with that CPU is shut down, the system administrator is notified, and repairs are made, or the processor is switched to a spare CPU that has been prepared in advance. Repairs are being carried out without stopping.

(Invention or Problem to be Solved) However, in such conventional multiprocessor systems, if one CPU breaks down, all of the processors, including those that are operating normally, must be stopped and repaired. However, there was a problem that the multiprocessor's ability to process a large amount of information at high speed was reduced.

In addition, in systems where the processor has a spare CPU, and the defective CPU can be replaced and repaired without stopping the processor, the spare CPU is usually not used, and the overall usage Inefficient,
There was a problem in that the cost of the entire system was high.

In addition, the number of CPUs allocated is fixed, so even in cases where reliability is not required or high-speed processing is required, or when there is a high load, the overall processing capacity cannot be increased. There was.

This invention was made in view of these conventional problems, and has a high degree of freedom in combining the CPUs that make up the processor, making it possible to keep the number of spare CPUs to a small number, and preventing CPU failures. To provide a multiprocessor system in which a failed CPU can be repaired without stopping the processor.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a multiprocessor system in which a plurality of CPUs are combined to form one processor, and a plurality of processors and processors are provided. A CP that re-determines the number of processors or the combination of CPUs constituting each processor according to the addition state of the processors.
It is equipped with U combination determining means.

Further, the multiprocessor system of the present invention further includes CPU failure determining means for determining a failure of a CPU belonging to any one of the plurality of processors, and the CPU combination determining means determines whether or not a failure has occurred by the CPU failure determining means. In such a case, the failed CPU can be removed from the processor to which it previously belonged, and a spare CPU can be assigned.

(Operation) In the multiprocessor system of the present invention, the CPU combination determining means determines the number of processors or the number of CPUs constituting each processor according to the addition state of the plurality of processors.
The combination of U can be re-determined.

Further, in the multiprocessor system of the present invention, when the CPU failure determining means determines that a failure has occurred in a CPU belonging to any processor, the CPU combination determining means excludes the failed CPU and selects one of the remaining CPUs. It is possible to determine anew the combination of CPUs that constitute each of the plurality of processors, and to cause each of the processors constituted by the newly determined combination of CPUs to continue executing processing.

(Example) Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Ten CPUs CPUI to CPUl0 are connected to a control unit 1, and four processors A to D are controlled by these CPUI to CPUl0. It is designed to be configured.

The control unit 1 uses software to determine the number of processors, the combination of CPUs belonging to each processor, and even a failed CPU.
It executes the determination of U, etc., and to explain its functions, it consists of a CPU combination determining section 2 that determines the number of processors and the combination of CPUs belonging to each processor;
A CPU failure determination unit 3 that determines a failure of a PU, and each CPU
The CPU is provided with an I10 control unit 4 that controls data input to the CPU and data output from each CPU.

To explain the hardware configuration of the I10 control unit 4 of the control unit 1, as shown in FIG. Register P
The selector 5 includes six registers, ie, a register Q for a faulty CPU, and a register Q for the faulty CPU, and comparators A to COMPARI for providing a CPU fault signal to the faulty CPU determining section 3 are further connected thereto.

Next, the operation of the multiprocessor system configured as described above will be explained.

In the control unit 1, the CPU combination determination unit 2 changes the number of processors according to the load state and also determines the combination of CPUs belonging to each processor. FIG. 2 is a model diagram configuring four multiprocessors.

Normally, as shown in Figure 7, the system is configured with 1 processor and 3 CPUs, and is operated as a multiprocessor consisting of 3 processors A to C. However, as the load increases, it becomes necessary to increase the number of controllers or processors. If it is determined that there is a task, it is determined from the task information whether or not there is a task that must be processed in a 3-CPU configuration.

FIG. 1 shows a case where it is determined that only the task being processed by multiprocessor B needs to be processed by a 3-CPU configuration. In this case, the CPU combination determination unit 2 of the control unit 1 CPU4 to CPU6 are 3CP
Leave the U configuration as is, and install these three CPUs and a spare CPU.
All remaining CPUs except 0 and 2 per processor
Change the CPU configuration.

In this way, when the CPU assignment for each processor is changed, the selector 5 shown in FIG. 4 sets which processor the CPU is assigned to and which CPU is reserved.

That is, for each register A to register D, CPU4 to
A bit is provided corresponding to each CPU 60, and when each bit is set to ``1'', it means that the CPU corresponding to that bit is assigned to the processor whose register is assigned, and register A corresponds to CPUI and CPU2. Set the bit to ``1'' and set all remaining bits to ``1''.
0", the CPUI and CPU
Assign 2.

Similarly, in register B, by setting the bits corresponding to CPU4 to CPU6 to "1", processor B
CPU4 to CPU6 are assigned to CPU3. By setting "1" to the bit corresponding to CPU7, CPU3° and CPU7 are assigned to processor C, and register D is assigned to CPU8. By setting "1" to the bit corresponding to CPU9, the CPU
8° Assign CPU9.

Then, in the spare CPU register P, by setting "1" to the bit corresponding to CPU10, CPU10 is set as a spare CPU.

Note that when both CPUs are normal, []" is not set in any bit of the register Q for the failed CPU.

Now, while executing the process in this state, the comparator is CPU8. Suppose that a discrepancy is found in the calculation results between CPUs 9 and 8. This indicates that a failure has occurred in one of the CPUs 9, but as it is, it is impossible to determine which CPU has the failure.

Therefore, in the control section 1, as shown in FIG.
As a result, the CPU that had been reserved until then for register D
The bit corresponding to l0 is set to ``1'', processor D is temporarily configured with 3 CPUs as shown in Fig. 2, and the processing is continued, and the comparator determines that the calculation results match.
Investigate discrepancies.

The CPU failure/failure section 3 determines that a failure has occurred in the CPU for which there is a disagreement based on the majority rule, in this case CPU8, and disconnects the CPU8 from the processor D as shown in FIGS. 3 and 6. , CPU9. CPUl
Connect 0 and execute the following processing.

For the failed CPU8, turn off the power and
Remove the mount board and repair the failure. Once the repair is complete, reinstall the CPU mount board into the system, and from now on, change the "1" set in the bit corresponding to CPU8 in the register Q for the failed CPU to "0". and reserve CP
Set "11" to the bit corresponding to CPU8 in register P for U, and use the repaired CPU8 as a new spare CPU.
shall be.

In addition, in order to determine which CPU has failed in comparators A to comparators, the output is 2 bits,
If it is "00", it is normal; otherwise, it indicates that the CPU of that number has failed, and the bit corresponding to the corresponding CPU in registers A to D is set to "
0" and set the corresponding bit in the register Q for the faulty CPU to "1" to determine the failure.

In the case of a 2-CPU configuration, as shown in FIG. 2, a spare CPU is used to create a 3-CPU configuration, and then the failed CPU is determined by searching for the failed CPU from the output of the comparator.

If the load is reduced, the basic 3C as shown in Figure 7
Return to the PU configuration, assign CPU1 to CPU3 to processor A, assign CPU4 to CPU6 to processor B,
CP, U7 to CPU9 are assigned to processor C to create a three-processor system, and CPU10 is used as a spare CPU.
Let it be U. In this case, since there is no CPU belonging to processor D, the ninth register
As shown in the figure, the bits corresponding to any CPU have "
1" is not set, and all are set to rOJ.

In the case of this basic 3-CPU configuration, if a failure occurs in one of the CPUs, for example, CPU5, as shown in FIG. processor B instead of
and reconfigure it into a 3-CPU configuration.

In this way, the number of processors can be varied by the control unit 1 according to the load, resulting in a basic 3-CPU configuration or a 2-CP configuration.
It can be configured in a U configuration or in a combination of these configurations, allowing for flexible support depending on the addition.

Furthermore, even if a failure occurs in the CPU belonging to any processor, a spare CPU can be installed in either processor in place of the failed CPU, eliminating the need for each processor to have a spare CPU. Te CP
By reducing the number of U's, usage efficiency can be increased, and because a spare CPU can be installed immediately in place of a failed CPU, processing delays can be suppressed.

[Effects of the Invention] As described above, according to the present invention, it is possible to arbitrarily combine or change the combination of CPUs incorporated into a multiprocessor, and in the event of a failure, spare CPUs can be used. Since it can be incorporated into a processor in place of a failed CPU, it can flexibly respond to CPU failures and load fluctuations, make it possible to repair the CPU without stopping the processor, and improve processing speed. It is also possible to improve the efficiency of CPU usage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing an intermediate stage of CPU recombination processing when a failure occurs in the above embodiment, and FIG. 3 is a block diagram of the CPU in the above embodiment when a failure occurs. FIG. 4 is a block diagram showing the hardware configuration of the above embodiment. FIG. 5 is a block diagram showing the state when the recombination process is completed. FIG. FIG. 6 is an explanatory diagram showing the register bit states at the time of completion of CPU recombination processing when a failure occurs in the above embodiment. FIG. 7 shows the basic multiprocessor configuration of the above embodiment. 8 is a block diagram showing the state at the time of completion of CPU recombination processing when a CPU failure occurs in the multiprocessor configuration of FIG. 7, and FIG. 9 is a block diagram showing the bit states of registers in the multiprocessor configuration of FIG. 8. FIG. ...Control section 2...CPU combination determination section 3...CPU failure bottom section 4...I10 control section 5...Selector

Claims (2)

[Claims] (1) In a multiprocessor system comprising a plurality of processors in which one processor is configured by a combination of a plurality of CPUs, the number of the processors or each processor is configured according to the addition state of the plurality of processors. A multiprocessor system comprising CPU combination determining means for re-determining a combination of CPUs. (2) further comprising CPU failure determining means for determining a failure of a CPU belonging to one of the plurality of processors;
2. The multiprocessor system according to claim 1, wherein when the CPU failure determination means determines that a failure has occurred, the CPU combination determination means removes the failed CPU from the processor to which it previously belonged and allocates a spare CPU.