JPH045861A - Semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize without short channel effect by varying an impurity distribution in a channel region of a field effect transistor in a channel direction. CONSTITUTION:P-type impurity such as boron is so ion implanted into a P-type silicon substrate 8 that the peak position of impurity concentration is approximately in depth of source.drain diffused layer of 0.1-0.2 micron as a punchthrough stopper. A resist is formed. Leaving a channel region, photomechanical process is conducted. Oblique ion implantation is performed. Then, a gate oxide film is formed, a gate polysilicon is mounted, and patterned to obtain a semiconductor device. Thus, it is obliquely ion implanted to provide a lateral profile in a channel to alleviate an electric field near a drain. Accordingly, a short channel effect can be prevented by an extremely simple process as compared with a transistor of an LDD structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which short channel effects associated with miniaturization of field effect transistors are improved.

[Conventional technology]

FIG. 4 is a cross-sectional view showing a field effect transistor, which is a conventional semiconductor device. In the figure, 1 is a source electrode;
2 is a back gate electrode, 3 is a gate electrode, 4 is a gate oxide film, 5 is a drain electrode, 6 is a source diffusion layer, 7 is a drain diffusion layer, and 8 is a substrate.

Next, impurity distribution will be explained.

FIG. 5 shows a current path in the operating state of a field effect transistor, and the region 9 is called a channel.

In order to control the dark voltage of the transistor, impurity ions such as boron and arsenic are added to this channel region 9 at a rate of 10"/
About c♂ has been injected. These impurity ions are implanted using an ion implanter from the space above the field effect transistor toward the wafer, so they have a distribution in the depth direction, but they have a distribution in the lateral direction (i.e., connecting the source and drain). In the direction of the channel (along a straight line), it has no distribution and is uniform.

[Problem to be solved by the invention]

Conventional field effect transistors have the structure described above, so in order to miniaturize the structure to about 0.3 microns, the amount of impurity ions implanted must be increased to suppress the short channel effect, and the drain The problem is that the growth of the depletion layer must be suppressed, and as a result, the electric field strength near the drain becomes stronger, making it necessary to take countermeasures against hot carriers.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device having a field effect transistor that can be miniaturized without causing short channel effects.

[Means to solve the problem]

In the semiconductor device according to the present invention, impurity ions in the channel region of a field effect transistor are also distributed in the lateral direction.

[Effect]

In the semiconductor device according to the present invention, since the impurity ions are distributed laterally in the channel region as described above, the impurity concentration can be increased only in a necessary region such as near the drain.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor device according to an embodiment of the present invention,
In the figure, 1 is a source electrode, 2 is a back gate electrode,
3 is a gate electrode, 4 is a gate oxide film, 5 is a drain electrode, 6 is a source diffusion layer, 7 is a drain diffusion layer, and 8 is a substrate.

FIG. 2 shows the impurity distribution in the xx' cross section of FIG. 1. Note that FIG. 2 shows the impurity distribution in the channel direction assuming an n-channel field effect transistor. Here, since the concentration value on the vertical axis varies depending on the device structure, the concentration is normalized by the maximum impurity concentration.

Next, the manufacturing method will be explained with reference to FIG.

Note that only the channel dose, which is a different step from the conventional method of manufacturing a field effect transistor, will be described here.

■ A P-type impurity such as poron is ion-implanted onto the P-type silicon substrate 8 so that the peak of the impurity concentration is at the depth of the source/drain diffusion layer of 0.1 to 0.2 microns to form a punch-through stopper. shall be.

■ Apply resist and photolithography leaving the channel area.

■ Perform oblique ion implantation.

Thereafter, the semiconductor device of this example is obtained by forming a gate oxide film, attaching gate polysilicon, and performing patterning using the same process as in the prior art.

(2) Oblique ion implantation utilizes differences in resist film thickness along the ion implantation path. If the resist film is thin, ions can penetrate through it. Therefore, in the case of FIG. 3(C), many ions enter the left side of the lower surface of the resist. In a long channel field effect transistor, ions are blocked by the resist, so it is impossible to create a distribution near the drain, but in a short channel field effect transistor, it is possible to create a distribution.

In this way, in this example, by performing ion implantation in an oblique direction, the channel part has a horizontal profile and the electric field near the drain is relaxed, so compared to a transistor with an LDD structure, This is an extremely simple process and is effective in preventing the short channel effect.

In the above embodiment, the electrode 1 and the electrode 2 are attached to the bottom of the element, but they may be attached anywhere as long as they are short-circuited to the P region of the substrate.

〔Effect of the invention〕

As described above, according to the semiconductor device according to the present invention, since the impurity distribution in the channel region is also provided in the lateral direction, it is possible to selectively reduce the concentration near the drain.
The electric field strength near the drain can be weakened. As a result, it is possible to reduce the impact ionization phenomenon, suppress the hot electron effect, and contribute to miniaturization.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the distribution of lateral impurities in a channel, and FIG. 3 is a fabrication of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a sectional view showing a conventional semiconductor device, and FIG. 5 is a diagram showing current paths in the operating state of the conventional semiconductor device. In the figure, ■ is the source electrode, 2 is the back gate electrode,
3 is a gate electrode, 4 is a gate oxide film, 5 is a drain electrode, 6 is a source diffusion layer, 7 is a drain diffusion layer, 8 is a substrate,
9 is a channel, and 0 is a current path flowing through the channel. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A semiconductor device constituting a field effect transistor, characterized in that the impurity distribution in the channel region is changed in the channel direction.