JPH0451196B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention, when a pachinko ball flies into a predetermined winning opening, starts to maintain a state that increases the winning probability of the winning device within a predetermined time, When a pachinko ball flies into the predetermined prize opening again during the winning probability increasing state of the winning device, the winning probability increasing state starts again from the beginning, wherein the winning probability increasing state of the winning winning device The present invention relates to a pachinko machine in which a state in which pachinko balls easily fly into the predetermined prize opening and a state in which the pachinko ball easily flies into the predetermined winning hole are repeated.

(Prior art) Conventionally, a pachinko ball flies into a predetermined winning hole and within a predetermined period of time, while the winning probability increasing state of the winning device is maintained, a pachinko ball flies into the predetermined winning hole. Sometimes, there is a pachinko machine that suppresses the gambling nature and does not reduce the desire to play by maintaining the increased winning probability for a predetermined time from the beginning.

(Problems to be Solved by the Invention) However, in this conventional pachinko machine, the winning probability increasing state simply changes the acceptance state of pachinko balls in the winning device, and the pachinko balls are not accepted by this winning device. After being
Since the winning opening is just waiting, it is unsatisfactory for modern players who are used to complex or sophisticated games, and this is becoming the norm to some extent, and the player's desire to play decreases. It was hot.

Therefore, the present invention has been made with the object of providing a pachinko machine that significantly increases a player's desire to play by providing a variety of gameplay without adding gambling properties as in the past. It is.

(Means for Solving the Problems) Therefore, the basic configuration of the present invention is that it consists of one space and another space, and the probability that a pachinko ball will fly into a predetermined winning hole is higher in the one space than in the other space. a winning space with a higher space; a sorting member that is provided in the winning space so as to be able to move back and forth and distributes pachinko balls between the one space and the other space depending on its position; and the sorting member. and a mechanism for causing the reciprocating motion.

(Function of the Invention) According to the present invention having such a configuration, a state in which a pachinko ball easily flies into a predetermined winning opening and a similar bad state are repeated during the winning probability increasing state of the winning device. Therefore, it is possible to provide a game change in which the winning probability changes even during this state of increasing winning probability.

(Example) An example of the present invention will be described below based on the drawings.

In FIG. 1, 1 is a game board, and this game board 1 includes a winning device 2, winning holes 3, 3 in which a single-action winning ball switch to be described later is provided, and a double-action winning ball to be described later. A winning opening 4 provided with a switch is provided.

In FIGS. 2 and 3, 5 is a casing of the prize winning device 2, and this casing 5 is composed of a casing main body 6, a rear base 7, and a mounting plate 8, which are stacked in this order.
A winning space 9 is formed within the casing 5. A partition plate 10 is provided in the middle part of this winning space 9 in the front and back direction, and as shown in FIG.
The space 11 is defined as a space 11, and the rear portion thereof is defined as a second space 12. At the bottom of the first space 11, a partition plate 13,
13 are erected, and between the partition plates 13 is a predetermined winning opening 14 in which an 18-operation winning switch, which will be described later, is provided. This first space 11 is configured so that the probability that a pachinko ball will fly into a predetermined winning hole 14 is extremely higher than that in the second space 12.

In addition to this predetermined winning hole 14, there are other winning holes provided in the winning space 9.
Pachinko balls that do not fly into the hole will enter there. These winning openings in the winning space 9 are provided with 10 count switches, which will be described later.

Guide vanes 15, 15 are arranged on both sides of the prize winning space 9, and these guide vanes 15, 15,
As shown in FIG. 3, it is fixed to the tip of a support shaft 16 that is inserted through the casing main body 6 and the rear base 7. These guide blades 15, 15 open and close the winning space 9, and when they are opened, pick up pachinko balls and guide them into the winning space 9, and are kept open until they reach the maximum horizontal state.

A solenoid 17 is fixed to the mounting plate 8, and 18 is a plunger thereof, and this plunger 18 is provided with a movement direction changing mechanism 19. The support shafts 16, 16 of the guide vanes 15, 15 are
The guide vanes 15, 15 are connected to this movement direction changing mechanism 19, and are opened and closed by a solenoid 17.

A distribution member 20 is provided in the winning space 9, and this distribution member 20 has the shape of an airplane and also serves as a decoration.
0b is a wing section. The wing parts 20b, 20b are for guiding the pachinko balls into the second space 12. The distribution member 20 has a body portion 20a inserted through a guide shaft 21 extending vertically at the center in the width direction of the winning space 9, so that the distribution member 20 can move up and down, and the wing portion 2
Guide ends 1 of guide vanes 15, 15 of 0b, 20b
The pachinko ball is placed in the first space 1 depending on the position relative to 5a.
1 and a second space 12.

22 is an AC motor, and this AC motor 22 is fixed to the back side of the mounting plate 8, and its rotating shaft 2
2a projects from the front side of the mounting plate 8. As shown in FIG. 6, a rotating disk 23 is fixed concentrically to this rotating shaft 22a.
One end of a cam rod 24 is eccentrically attached to 3, and 25 is a shaft pin projecting from the rotating disk 23. The other end of the camrod 24 is pivoted to the tail of the body 20a of the distribution member 20, and
is its shaft screw. In this configuration, the rotation of the AC motor 22 is converted into vertical power by the cam rod 24 and the guide shaft 21 via its rotating shaft 22a and rotating disc 23, and thereby the distribution member 20 is moved vertically. It has become possible to move.

A cam cylindrical portion 23a is protruded from the side of the rotating disk 23 that is fixed to the rotating shaft 22a, and this cam cylindrical portion 23a is fitted onto the rotating shaft 22a and is connected to the rotating shaft 22a.
It is located concentrically with respect to 2a, and has a groove 23b formed on its outer periphery. This cam cylinder part 2
A micro switch 27 is disposed on the side of 3a, and this micro switch 27 is fixed to the mounting plate 8, and 27a is an opening/closing lever linked to the contact point. This opening/closing lever 27a
has a bent portion 27b at its tip that is protruding from the outer periphery of the cam cylinder portion 23a and is large enough to fit into the groove 23b.
b is in elastic contact with the outer circumferential portion of the cam cylinder portion 23a.
The micro switch 27 opens when the bent portion 27b enters the groove 23b and stops the AC motor 22.

In addition to the above-described configuration, the winning device 2 includes light emitting diodes 28a to 28h arranged on both sides of the casing body 6, and a device 18 provided on the head of the body 20a of the distribution member 20 to numerically display the number of 18 operations. The number of rotations display section 29 and the 10 count numerical display section 30 provided on the top of the casing body 6 and displaying the number of pachinko balls (10 count value) that flew into the winning opening in the winning space 9 during the 18 operations. It is supposed to have the following.

FIG. 7 shows the control circuit, in which 31 is a one-time operation switch input circuit, and 32 is a two-time operation switch input circuit.
Rotary operation switch input circuit, 3 is 18 operation switch input circuit, 34 is 10 count switch input circuit,
35 is a motor stop switch input circuit, 36 is a power-on reset circuit, 37 is a timing signal generation circuit, 38 is a clock circuit, 39 is a timer circuit, 40 is a reset circuit, 41 is a solenoid/lamp driver circuit, and 42 is a motor driver circuit. ,
43 is an LED lighting control circuit, 44 is an LED driver circuit, 45 is a signal stop circuit, 46 is a timing signal output circuit for electronic sound generation, 47 is a power supply circuit for electronic sound generation, 48 is an electronic sound generation circuit, and 49 is a melody generation circuit. 50 is a melody generation circuit,
51 is a mixing amplifier circuit, and 52 is a speaker.

Below, these circuit components will be explained in detail.

The one-time operation switch input circuit 31 includes a one-time operation winning ball switch 53, an inverter 54, and a latch circuit 5.
5, one-time operation winning ball switch 53
is closed when a pachinko ball flies into at least one of the winning holes 3,3. The latch circuit 55 has a data input terminal D, a clock input terminal C, a set terminal S, a positive output terminal Q, a negative output terminal, and a reset terminal _R. Therefore, the data input terminal D is set to H level, the set terminal S is grounded, and the negative output terminal is not used. The clock input terminal C is set to go from L to H when the one-time winning ball switch 53 is closed, and the positive output terminal Q is connected to the clock input terminal C.
When an H clock is input to the terminal, it outputs an H signal, and this state is maintained until an H clock is input to the reset terminal D.

The two-time operation switch input circuit 32 includes a two-time operation winning ball switch 56, an inverter 57, and a latch circuit 5.
8, the winning ball switch 56 operates twice.
is closed when a pachinko ball flies into the winning hole 4. The launch circuit 58 has a data input terminal D, a clock input terminal C, a set terminal S, a positive output terminal Q, a negative output terminal, and a reset terminal R.
V _DD is being applied, the data input terminal D is at H level, the set terminal S is grounded, and the negative output terminal is not used. The clock input terminal C is made to change from L to H when the twice-operating winning ball switch 56 is closed, and the positive output terminal Q
outputs an H clock when an H clock is input to this clock input terminal C, and outputs an H clock to the reset terminal R.
This state is maintained until an input is made.

The 18-time operation switch input circuit 33 includes an 18-time operation winning ball switch 59, an inverter 60, a 3-input AND gate 61, and a latch circuit 62.
The rotating winning ball switch 59 is closed when a pachinko ball enters the predetermined winning hole 14, and one input terminal of the 3-input AND gate 61 is connected to the 18-playing winning ball switch 59. It is made to become H when it is closed. The latch circuit 62 is constructed by crossing two NOR gates 63 and 64, and has a 3-input AND gate 61.
When the high output is output from , it is latched and the NOR gate 6
The output terminal of the NOR gate 63 becomes H, the output terminal of the NOR gate 63 and one input terminal of the NOR gate 64 become L, the output terminal of the NOR gate 64 and the other input terminal of the NOR gate 63 become H, and this state is changed to the 3-input AND gate 61. It is held until the output of the NOR gate 64 becomes L or the other input terminal of the NOR gate 64 becomes L.

The 10 count switch input circuit 34 includes a 10 count switch 65, an inverter 66, a binary counter 67, and an AND gate 68. It is then closed. The 4-bit binary counter 67 has a power input terminal CE, a clock input terminal C, a reset terminal R, and output terminals Q ₁ , Q ₂ , Q ₃ , and Q ₄ .The power input terminal CE has a power supply voltage V _{DD .} is applied, and output terminals Q ₁ and Q ₃ are not used. The clock input terminal C receives the H clock when the 10 count switch 65 is closed. The output terminal Q ₂ is connected to one input terminal of the AND gate 68, and the output terminal Q ₄ is connected to the other input terminal of the AND gate 68. When the count value reaches "10" in decimal notation, an H signal is output from the AND gate 68. It is designed to produce output.

The motor stop switch input circuit 35 includes the aforementioned microswitch 27 and an inverter 69, and when the microswitch 27 is closed, the inverter 69 outputs an H output.

The power-on reset circuit 36 is an OR gate 73
A power supply voltage V _DD is applied to both input terminals of this OR gate 73.
H when a power switch (not shown) is turned on
It is designed to shoot one pulse.

The timing signal generation circuit 37 includes three OR gates 70, 71, and 72. or gate 7
0, the output of the positive output terminal Q of the latch circuit 55 is inputted to one input terminal, and the output of the positive output terminal Q of the latch circuit 58 is inputted to the other input terminal, and this OR gate 70 outputs an H level when at least one of the latch circuits 55 and 58 is latched.
The two input ends of the OR gate 71 are connected, and the output of the NOR gate 64 of the latch circuit 62 is inputted.
It is designed to output an H level when latched. The output of the OR gate 70 is input to one input terminal of the OR gate 72, and the output of the OR gate 71 is input to the other input terminal.
When at least one of them is latched, an H output is made.

The clock circuit 38, as shown in FIG. 8, generates CR oscillation of a clock pulse having a pulse width of 0.00625 seconds.

The timer circuit 39 includes a binary counter 74 and two AND gates 75 and 76. The binary counter 74 has a reset terminal R, a clock input terminal C, and output terminals Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ ,
Q ₇ , Q ₈ , Q ₉ , Q ₁₀ , Q ₁₁ , Q ₁₂ , and the clock pulse of the clock circuit 38 is input to the clock input terminal C, and each output terminal Q ₁ to _Q12 divides the frequency of this clock pulse and outputs a pulse signal as shown in FIGS. 8 to 10. That is, the output terminal Q ₁ has a function of outputting a pulse signal having a period twice the period of the clock signal when the first clock pulse is input, and the output terminal Q ₂ has a function of outputting a pulse signal having a period twice the period of the clock signal. The output terminal _Q3 has a function of outputting a pulse signal having a period of 8 times the period of the clock signal when the second clock pulse is input. The output terminal Q ₄ has the function of outputting a pulse signal having a period 16 times the period of the clock signal when the eighth clock pulse is input, and the output terminal Q ₅ has a function of outputting a pulse signal having a period 16 times the period of the clock signal. has the function of outputting a pulse signal having a period 32 times the period of the clock signal when the 16th clock pulse is input, and the output terminal _Q6 outputs a pulse signal having a period 64 times the period of the clock signal. It has the function of outputting when the 32nd clock pulse is input, and the output terminal _Q7 is 128 times the period of the clock signal.
It has the function of outputting a pulse signal with a period _twice the period of the clock signal when the 64th clock pulse is input. It has the function of outputting when it is input, and is an output terminal.
Q ₉ has the function of outputting a pulse signal with a period 512 times the period of the clock signal when the 256th clock pulse is input, and output terminal Q ₁₀ has a period 1024 times the period of the clock signal. It has the function of outputting a pulse signal when the 512th clock pulse is input, and the output terminal _Q11 outputs a pulse signal with a period 2048 times the period of the clock signal when the 1024th clock pulse is input. Output terminal _Q12 has the function of clock signal.
It has a function of outputting a pulse signal having a period 4096 times as long as the 2048th clock pulse is input. The output signal from the output terminal Q ₄ , the output signal from the output terminal Q ₆ , and the output signal from the output terminal Q ₇ are input to the AND gate 75 . AND gate 76 has output terminal Q ₉
The output signal from the output terminal Q12 and the output signal from the output terminal _Q12 are input.

The reset circuit 40 consists of latch circuits 55, 58, 6.
2 and the binary counters 67 and 74, and three 3-input OR gates 7
7, 78, 79 and Noah Gate 80 and Or Gate 8
1. The output signal from the OR gate 64, the output signal from the OR gate 73, and the output signal from the AND gate 75 are input to the OR gate 77.
has a function of inhibiting the latch circuit 55 from latching when these output signals are at H level. The output signal from the OR gate 64, the output signal from the OR gate 73, and the output signal from the output terminal _Q9 of the binary counter 74 are input to the OR gate 78, and the OR gate 78 receives these output signals. It has a function of inhibiting the latch circuit 58 from latching when is at H level. The output signal from the AND gate 68, the output signal from the OR gate 73, and the output signal from the AND gate 73 are input to the OR gate 79, and when these output signals are H, the OR gate 79 It has a function of inhibiting the latch circuit 62 from latching. Noah Gate 80 has Noah Gate 64
The output signal from the OR gate 70 and the output signal from the OR gate 70 are input to the OR gate 8.
The output signal from the AND gate 61 and the output signal from the NOR gate 80 are input to the OR gate 1, and the OR gate 81 outputs the binary counters 67, 67, 74 to an initial state.

The solenoid lamp driver circuit 41 includes an OR gate 82, a solenoid drive power amplification transistor 83, an AND gate 84, and a lamp drive power amplification transistor 85. The output signal from the output terminal _Q9 of the binary counter 74 is input to the OR gate 82, and the output signal from the OR gate 82 is input to the transistor 83.
The signal is amplified and supplied to the solenoid 17. The output signal from the OR gate 64 of the latch circuit 62 and the output signal from the output terminal Q ₃ of the binary counter 74 are input to the AND gate 84 . The power is amplified and supplied as power for blinking the decorative lamps on the winning device 2 or the game board 1.

The motor driver circuit 42 includes an OR gate 86, a switching transistor 87, and a triax 8.
8, and the output signal from the NOR gate 64 of the latch circuit 62 and the output signal from the motor stop switch input circuit 34 are input to the OR gate 86. This or gate 86
When the output signal of the AC motor 22 is high, the transistor 87 is turned on.
is now being driven.

The LED lighting control circuit 43 is a binary counter 8
9 and an or gate 90'. The binary counter 89 has a reset terminal R and a power input terminal.
CE, clock input terminal C and output terminal Q ₁ , Q ₂ ,
The clock input terminal C is grounded, and _{the output terminals Q 1 , Q 3 and Q 4 are not used .}
A clock signal from a clock circuit 38 is input to the power supply input terminal CE, and a pulse signal obtained by dividing the frequency of this clock signal by two is output from the output terminal _Q2 . The output signal from the OR gate 71 is input to the reset terminal R of the binary counter 89, and the latch circuit 6
When 2 is latched, output is prohibited. The output signal from the AND gate 61 and the output signal from the output terminal _Q2 of the binary counter 89 are input to the OR gate 90', and one of the two output signals is output. It is something.

The LED driver circuit 44 is a shift register 90
and Noah gate 91, or gate 92, and return circuit 9
3, a power supply amplification IC circuit 94, and a current amplification transistor 95, and the shift register 90 has reset terminals Ra, Rb and input terminals Ca, Cb, Da, Db.
and output terminals Qa ₁ , Qa ₂ , Qa ₃ , Qa ₄ , Qb ₁ , Qb ₂ ,
It has Qb ₃ and Qb ₄ . Reset terminal Ra,
The output signal of the NOR gate 91 is input to Rb, and the output signal of the NOR gate 63 and the output signal of the OR gate 71 are input to the NOR gate 91. input terminal
The output signal of the OR gate 90' is input to Ca and Cb, and the shift timing is determined based on the output signal of the OR gate 90'. The output signal from the OR gate 92 is input to the input terminal Da, and the output signal from the OR gate 71 and the output signal from the return circuit 93 are input to the OR gate 92. and connect either of the two output signals to the output terminal.
The shift data is set for Qa ₁ to _{Qa 4} . The output signal of output terminal Qa ₄ is the input terminal
It is designed to be input to Da, and the output terminal
It has come to be used as shift data for Qb ₁ to Qb ₄ . The return circuit 93 is composed of two 4-input NOR gates 96, 97 and an AND gate 98, and the NOR gate 96 has output terminals Qa ₁ -
The output signal of Qa ₄ is input to the NOR gate 97, and the output signals of the output terminals Qb ₁ to _{Qb 4} are input to the NOR gate 97. When the inputs to both NOR gates 96 and 97 are L, the input terminal H is input to Da, forming a ring counter. The current amplification IC circuit 94 and the current amplification transistor 95 are for amplifying the output signals from the output terminals Qa ₁ to Qb ₄ of the shift register 90 and supplying driving current to the light emitting diodes 28a to 28h. The IC circuit 94 has input terminals _I1 to _I7 and corresponding output terminals _O1 to _O7 . Output terminal Qa ₁ of shift register 90
The output signals of Qb ₃ are input to the input terminals I ₁ to _{I 7} of the current amplification IC circuit 94, respectively, and the output signal of the output terminal Qb ₄ of the shift register 90 is input to the base of the current amplification transistor 95. The output signals of the output terminals _O1 to _O7 of the current amplification IC circuit 94 are input to the light emitting diodes 28a to 28g, and the output signal of the transistor 95 is input to the light emitting diode 28h.

The signal stop circuit 45 is composed of an inverter 99 and an OR gate 100.
The output signal from the output terminal _Qb4 of the shift register 90 is input to the input terminal Qb4. The output signal from the NOR gate 63 of the latch circuit 62 and the output signal from the inverter 99 are input to the OR gate 100, and the output signal of the OR gate 100 is configured to become one input of the AND gate 61. ing. That is, the latch circuit 6
When the output of the shift register _Qb4 becomes H when the latch circuit 62 is latched, the latch state of the latch circuit 62 is released, and when the latch circuit 62 is not latched, the output of the shift register _Qb4 becomes H.
Even if the output is H, the 18th operation winning ball switch 59 is not turned on.

The electronic sound generation timing signal output circuit 46 is composed of an OR gate 101, an AND gate 102, a delay circuit 103, and an inverter 104, and the output signal from the AND gate 61 is input to one input terminal of the OR gate 101. The output signal of this OR gate 101 is directly input to one input terminal of an AND gate 102.
It is also input to the other input terminal of the AND gate 102 via the delay circuit 103 and the inverter 104. When an H signal is input to the OR gate 101, a one-shot H signal is output from the AND gate 102.
The clock is now output.

The electronic sound generation power supply circuit 47 is an AND gate 10
5 and a one-shot circuit 179. This AND gate 105 is connected to the output signal of the AND gate 102 and the output terminal Q ₃ of the binary counter 74.
The output signal from the The AND gate 105 outputs the clock signal from the output terminal _Q3 for the one-shot time of the AND gate 102, and this clock signal is attenuated by a group of diodes, resistors, and capacitors, and then input to the electronic sound generating circuit 48. It is becoming more and more like this. The one-shot circuit 109 is composed of a delay circuit 110, an inverter 111, and a three-input AND gate 112. The AND gate 112 has a NOR gate 63 at one input terminal.
At the same time, the output signal from the output terminal Q 7 of the binary counter 74 is directly input to the other input terminal, and the output signal from the output terminal Q ₇ of the binary counter ₇₄ is input directly to the other input terminal. When the signal is input through the delay circuit 10 and the inverter 111, and the latch circuit 62 is not latched, and the one-time winning ball switch 53 or the two-time winning ball switch 54 is When the circuit is closed and the output signal from the output terminal _Q7 of the binary counter 74 becomes H, a one-shot H clock is output.

The electronic sound generation circuit 48 is the electronic sound generation source circuit 47
It outputs a signal to generate a predetermined electronic sound, for example, "beep, beep, beep" using the output signal from the device as a power source.

The melody generation power supply circuit 49 is the inverter 1
06, an AND gate 107, and a constant voltage circuit 108, and the inverter 106 is configured to receive an output signal from the AND gate 102. And gate 107 has or gate 71
The output signal from the inverter 106 and the output signal from the inverter 106 are input to the AND gate 107, and the AND gate 107 outputs an H level after the one shot time by the AND gate 102.
The output signal of the AND gate 107 is input to a constant voltage circuit 108, which converts it into a constant voltage and inputs it to the melody generating circuit 50.

The melody generation circuit 50 uses the output signal from the constant voltage circuit 108 as a power source and outputs a signal for generating a predetermined melody.

The output signal from the electronic sound generation circuit 48 and the output signal from the melody generation circuit 50 are the power amplifier circuit 5.
1, mixed and amplified by this power amplification circuit 51, and supplied to the speaker 52,
The speaker 52 is driven.

Next, the operation of the pachinko machine configured as described above will be explained.

(i) 1st action winning ball switch 53, 2nd action winning ball switch 56, and 18th action winning ball switch 5
When all 9 are in development.

The output of the output terminal Q of the latch circuit 55 and the output of the output terminal Q of the latch circuit 58 are both L, the output of the OR gate 70 is L, and the output of the NOR gate 64 of the latch circuit 62 is also L. Therefore, the output of the NOR gate 80 becomes H, the output of the OR gate 81 becomes H, and the binary counters 67 and 74 are in a state in which output is prohibited. Therefore, the solenoid 17 is not driven.

Since the latch circuit 62 is not latched, the motor 22 is also not driven.

Next, since the latch circuit 62 is in an unlatched state, the output of the NOR gate 63 is H, so H is input to the NOR gate 91, the output of this NOR gate 91 is L, and the shift register 90 is reset. is not applied. Further, the input from the OR gate 71 to the OR gate 92 is also at L level. And since the output of the AND gate 61 is also L,
The input from the AND gate 61 to the OR gate 90' is also at L level. Therefore, since the shift register 90 operates like a ring counter (see FIG. 17), the light emitting diode 2
8a to 28h repeat the state of lighting up one by one starting from the bottom one.

Since the output of the binary counter 74 is prohibited, no sound is generated from the speaker 52.

(ii) When the one-time operation winning ball switch 53 is closed (however, the output of the OR gate 77 is L).

When the one-time operation winning ball switch 53 is closed, an H clock pulse is output from the inverter 5, the latch circuit 55 is latched, and the output of its output terminal Q becomes H. Then, or gate 7
H is input to 0, and the output of the NOR gate 80 becomes L. On the other hand, the output of the AND gate 61 is L
Therefore, the output of the OR gate 81 is L.
As a result, the reset of the binary counter 74 is released. Therefore, the output signal from the output terminal Q _{7 of} the binary counter 72 is input to the OR gate 82 and the solenoid 17 is driven.
Each output signal from Q ₆ and Q ₇ is passed through AND gate 75
0.5 after the output signal from the output terminal _Q7 of the binary counter 74 becomes H.
After a second, the output of the AND gate 75 becomes H and the latch circuit 55 is reset, so the solenoid 17 is driven for only 0.5 seconds (see FIG. 11).

At this time, the output terminal of the binary counter 74
Since the output signal of _Q7 is also input to the one-shot circuit 109, the speaker 52 is driven for the one-shot time and an electronic sound is generated.

Note that the motor 22 is still not driven, and the light emitting diodes 28a to 28h are in the same lighting state as in (i).

(iii) When the twice-operated winning ball switch 56 is closed (however, the output of the OR gate 78 is L).

When the double-operation winning ball switch 56 is closed, an H clock pulse is output from the inverter 57, the latch circuit 58 is latched, and the output of its output terminal Q becomes H. Then, or gate 7
H is input to 0, and the output of the NOR gate 80 becomes L. On the other hand, the output of the AND gate 61 is L
Therefore, the output of the OR gate 81 is L.
As a result, the reset of the binary counter 74 is released. Therefore, the output signal from the output terminal Q ₇ of the binary counter 74 is input to the OR gate 82 and the solenoid 17 is driven, but 2.4 seconds after the output signal from the output terminal Q ₇ of the binary counter 74 becomes H. Later, the output of the output terminal _Q9 of the binary counter 74 becomes H and the latch circuit 58 is reset.
The solenoid 17 will be driven twice for 0.8 seconds each (see Figure 12).

At this time, the output terminal of the binary counter 74
Since the output signal of _Q7 is also input to the one-shot circuit 109, the speaker 52 is driven by the amount of two shots, and an electronic sound is generated.

Note that the motor 22 is still not driven, and the light emitting diodes 28a to 28h are in the same lighting state as in (i).

(iv) When the 18th operation winning ball switch 59 is closed.

When the 18th operation winning ball switch 59 is closed, an H clock pulse is output from the inverter 60, and this H clock pulse is applied to the AND gate 61.
is input. At this time, as a matter of course, one of the latch circuits 55 and 58 is latched, so the input from the OR gate 72 to the AND gate 61 is H, so the H clock pulse is output from the AND gate 61. Therefore, the latch circuit 62 is latched, the output from the NOR gate 63 becomes L, and the output from the NOR gate 64 becomes H, and the latch circuit 5
Outputs of 5 and 58 are prohibited. Then, as in cases (ii) and (iii), the output terminal of the binary counter 74
The solenoid 17 is driven by the output signal from _Q7 , but the binary counter 7
Since each output signal from the output terminal Q ₉ and Q ₁₂ of the binary counter 74 is input to the AND gate 76, the output from the output terminal Q ₇ of the binary counter 74 becomes H first.
After 28 seconds, the output of the AND gate 76 becomes H and the latch circuit 62 is reset, so the solenoid 17 is driven 18 times for 0.8 seconds each (see FIG. 13). ).

By the way, solenoid 17 and 18 like this
During the rotation, the winning ball switch 5 operates again for the 18th time.
When solenoid 9 is closed, binary counter 74 is brought to an initial state by the H clock pulse from AND gate 61, and solenoid 17 is driven 18 times from the beginning (see FIG. 14).

Also, when the 10 count switch 65 is closed 10 times during these 18 operations, each output of the output terminals Q ₂ and Q ₄ of the binary counter 67 becomes H,
Since the output of the AND gate 68 becomes H and is input to the OR gate 79, the latch circuit 62 is reset, and at this point the driving of the solenoid 17 is stopped. That is, if 10 pachinko balls are won in the prize opening in the winning space 9 during the 18th operation, the solenoid 17 is stopped even during the 18th operation (Fig. 15). reference.).

Next, at the same time that the latch circuit 62 is latched, the H output from the NOR gate 64 is input to the OR gate 86, so that the transistor 87
is turned on and the motor 22 is driven. This motor 22 rotates 3 times during 18 operations (see FIG. 13).

Here, if the latch circuit 62 is reset during the 18th operation, the input from the NOR gate 64 to the OR gate 86 becomes L, but if the micro switch 27 is closed at this time, the inverter Since the input from 69 to OR gate 86 is H, motor 22 continues to be driven. When the micro switch 27 is opened, the input from the inverter 69 to the OR gate 86 becomes L, and the motor 22 is stopped. Therefore, the distribution member 20 is always stopped at a fixed position (see FIG. 16).

Furthermore, when the 18th operation winning switch 59 is closed, the H clock pulse output from the AND gate 61 is also input to the OR gate 101.
Further, when the latch circuit 62 is latched, an H signal is input to the AND gate 107, so that the electronic sound generation circuit 48 and the melody generation circuit 50 are driven, and a predetermined sound is generated from the speaker 52.

On the other hand, after the latch circuit 62 is latched,
The input from the NOR gate 64 of the OR gate 92 is H, and the binary counter 89
is reset by the input from the NOR gate 64, and the input to the OR gate 90' is switched to the output signal from the AND gate 61. Therefore, the 18th action winning ball switch 59
Each time the winning ball switch 59 is closed, H is input from the input terminal Da, and from the 4th time the winning ball switch 59 is closed, H is input from the input terminal Db, so the light is emitted. diode 28
a to 28h are in order from light emitting diode 28a.
The number of balls corresponding to the number of times the winning ball switch 59 is closed will be lit (see FIG. 18).

Then, the output terminal Qb ₄ of the shift register 90
When the output signal from the inverter 99 becomes H, the inverter 99
The output from the AND gate 61 becomes L, and the H
Since the output is prohibited, the closing of the 18th operation winning ball switch 59 after the 9th time is invalidated, and the 18th operation ends at the 8th time.

Here, the state in which these 18 operations are performed,
That is, during the winning probability increasing state, since the distribution member 20 reciprocates within the winning space 9 as described above, the pachinko balls that have jumped into the winning space 9 are placed in Since the probability of being allocated to the first space 11 and the second space 12 where the predetermined prize opening 14 is not provided increases or decreases, the game board
You can feel the excitement of wa-ku-wa-ku.

(Effects of the Invention) As is clear from what has been described above, according to the present invention, it is possible to provide a pachinko machine that significantly increases a player's desire to play, compared to the conventional one, without adding gambling features. .

[Brief explanation of the drawing]

FIG. 1 is a front view showing the structure of the game board of a pachinko machine according to the present invention, FIG. 2 is a front view showing the structure of the winning device on the game board shown in FIG. 1, and FIG. 3 is an exploded perspective view of the same. , Fig. 4 is a sectional view showing the structure of the winning space of the winning device shown in Figs. FIG. 7 is a control circuit diagram of the above-mentioned prize winning device; FIGS. 8 to 10 are time charts showing the output signal of the 12-bit binary counter of the control circuit shown in FIG. 7; Figure 11 is 1
A time chart showing the circuit operation when the two-time action winning ball switch is closed. Figure 12 is a time chart showing the circuit operation when the two-time action winning ball switch is closed. Figure 16 is a time chart showing the circuit operation when the winning ball switch is closed 18 times, and Figure 17 shows the lighting state of the light emitting diode in the cases shown in Figures 11 and 12 using the driving signal. The displayed time chart, Figure 18, is the first
This is a time chart showing the lighting state of the light emitting diode in the case shown in FIG. 3 using the driving signal. 2... Winning device, 9... Winning space, 11... First space, 12... Second space, 14... Predetermined winning opening, 15
...Guide vane, 17...Solenoid, 20...Distributing member, 22...Motor, 33...18 operation switch input circuit, 37...Timing signal generation circuit, 38...Clock circuit, 39...Timer circuit, 40...Reset circuit, 41 ...Solenoid lamp drive circuit, 42
...Motor drive circuit.

Claims (1)

[Claims] 1. When a pachinko ball flies into a predetermined winning opening,
When the winning probability of the winning device starts to increase within a predetermined time and a pachinko ball flies into the predetermined winning opening again while the winning probability of the winning device is increasing, the winning probability is increased again from the beginning. In a pachinko machine configured to start an increasing state, the prize entry device comprises one space and another space, and the probability that a pachinko ball will fly into the predetermined prize opening is higher in the one space than in the other space. a prize-winning space with a higher side; a distribution member that is provided in the prize-winning space so as to be reciprocally movable and distributes pachinko balls to the one space and the other space according to its position;
A pachinko machine comprising a mechanism for causing the distribution member to perform the reciprocating motion.