JPH0447987B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a vertical MIS (metal/insulator/semiconductor)
It is related to FET (field effect transistor).

[Prior Art] Conventionally, vertical MIS-FETs were generally manufactured by diffusion technology and had a structure as shown in FIG. In FIG. 1, 1 is a drain electrode;
2 is a drain region, 3 is an active region, 4 is a source region, 5 is a source electrode, 6 is an insulating layer, 6 is a gate electrode, and 8 is a base electrode. This MIS-FET is
From the gate electrode 7 through the insulating layer 6, the semiconductor layer 2,
An electric field is applied to the cross sections of 3 and 4, thereby inducing or extinguishing a conductive channel indicated by C between the source region 4 and the drain region 2, and the current between the drain and source is controlled by the gate voltage. be.

[Problems to be Solved by the Invention] The above-mentioned vertical MIS-FET usually uses a single crystal semiconductor substrate which becomes the drain region 2, and forms the active region 3, source region 4, etc. by diffusing impurities. Therefore, the drain region was inevitably large, and the parasitic capacitance between the gate and the drain caused by the planar overlap with the gate electrode became extremely large. Furthermore, because electrodes and the like are drawn out over the drain region, which serves as a substrate, through an insulating layer, a large parasitic capacitance generated between the drain region and the wiring has also become a problem. If the parasitic capacitance is large like this, the operation of the FET will be slow.
This adversely affects circuit operation, such as deteriorating the high frequency characteristics of MIS-FET.

On the other hand, by forming a source region, an active region, and a drain region in a mesa shape on a substrate, and providing a gate electrode on the side surface of the active region with an insulating layer interposed therebetween,
A vertical MIS-FET that solved the above problems was proposed in Japanese Patent Application Laid-Open No. 17071/1983.

An object of the present invention is to further improve the mesa-type FET described above, and to easily configure a multi-input circuit that performs signal processing by weighting the gains of multiple input signals without increasing parasitic capacitance. vertical
Our goal is to provide MIS-FET.

[Means for Solving the Problems] The above object of the present invention is to provide a structure in which a source region, an active region, and a drain region made of a semiconductor are stacked on a substrate in a mesa shape, and a gate electrode is formed on a side surface of the active region via an insulating layer. Vertical MIS-FET with
wherein the substrate is a single-crystal insulating substrate, the source region, the active region, and the drain region are formed of a single-crystal semiconductor; This is achieved by constructing the gate electrode.

[Example] FIGS. 2a to 2c are diagrams for explaining the schematic configuration of a vertical MIS-FET that is the basis of the present invention. Here, Fig. 2b is a plan view of the FET, Fig. 2a is a front sectional view of the FET along line segment A-A' in Fig. 2b, and Fig. 2c is a line segment in Fig. 2c. B-
A side cross-sectional view of the FET along B' is shown, respectively.

In FIGS. 2a to 2c, 9 is an insulating substrate, 11 is a drain electrode, 12 is a drain region,
13 is an active region, 14 is a source region, 15 is a source electrode, 16 is an insulating layer, and 17 is a gate electrode. In addition, 11 and 12 were respectively drain electrodes and drain regions, and 14 and 15 were respectively source regions and source electrodes, but by taking the opposite configuration, 11, 12,
14 and 15 can be respectively used as a source electrode, a source region, a drain region, and a drain electrode. Here, the conductive channel C is induced by applying an electric field to the gate electrode 17 via the insulating layer 16.

As shown in this figure, in the present invention, by forming the semiconductor layer in a mesa shape, the drain region is not used as a substrate, so the drain region can be made small, and the drain region and gate electrode, etc. The parasitic capacitance between can be reduced.

Furthermore, since the semiconductor layer is electrically isolated by the insulating substrate, parasitic capacitance associated with wiring from each electrode does not occur. That is, according to the present invention, a vertical MIS-FET that operates quickly and has good high frequency characteristics can be realized.

Figure 3 shows the vertical MIS-
FIG. 7 is a side sectional view illustrating another example of the FET. In this example, a part of the drain (source) region of the FET shown in FIG. 2 is removed, and corresponding parts to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this example, the portion of the drain (source) region 12 that overlaps the electrode extraction portion of the source (drain) region 14 in plan dimension is removed by etching or the like during the manufacturing process. This reduces the parasitic capacitance between the drain region and the source region, and further improves the high frequency uniformity of the vertical MIS-FET.

The present invention is based on the configuration shown in FIG. 2 or 3, and is provided with a plurality of gate electrodes each having a different area and into which signals are input independently. A plan view of an embodiment of the present invention in which four gate electrodes are provided is shown in FIG.

In FIG. 4, 21 is a drain electrode, 25 is a source electrode, 26 is an insulating layer, 27a, 27b, 2
7c and 27d are gate electrodes. In a conventional FET as shown in Figure 1, as the number of gate electrodes increases, the parasitic capacitance between the gate electrode and the wiring drawn from the gate electrode and the drain region, which is the substrate, increases, which adversely affects the electrical characteristics. Ta.

However, in the vertical MIS-FET of the present invention, the parasitic capacitance between the gate electrode and other regions is small, and the wiring from each gate electrode also runs on the insulating substrate without causing parasitic capacitance. Therefore, many gate electrodes can be provided without significantly deteriorating the electrical characteristics.

Furthermore, in the present invention, since the width of the gate electrode indicated by W in FIG. 4 is changed, it is possible to manufacture a plurality of input gates in which the zein is given a desired weight. Vertical MIS of this example manufactured as shown in Fig. 4
Figure 5 shows the current-voltage characteristics of the FET. The horizontal axis is the source-drain voltage V _D and the vertical axis is the drain current I _D
The curves 27a, 27b, 27c, and 27d correspond to the curves 27a, 27b, 27c, and 27 in FIG. 4, respectively.
The V _D −I _D characteristics are shown when the same gate voltage is applied to the gate electrode of d. In this way, the vertical type of the present invention
In MIS-FET, a drain current proportional to the area of the gate electrode flows through the same source electrode and drain electrode.

Vertical MIS-FET with multiple gates like the present invention
One of the advantages of this is that it is compact and allows easy creation of multi-input analog OR circuits with good characteristics. For example, when an analog OR circuit detects four input signals input at different times, conventionally four transistors are required. On the other hand, in the vertical MIS-FET of the present invention,
As explained above, only one transistor is required. Therefore, the area required to create this circuit is smaller than that of the conventional circuit, and since the same source and drain are used, the characteristics of each input are also very well matched. Furthermore, by changing the area of the gate electrode as in the present invention, a multi-input analog circuit can be created in which the gain of the input gate is weighted. That is, according to the present invention, the characteristics of analog circuits and the like can be improved and the degree of integration can be significantly increased.

An example of the method for manufacturing the FET of the present invention will be explained with reference to FIGS. 2a to 2c. First, the drain region 12 is epitaxially grown on a single crystal insulating substrate such as sapphire. For example, this is the case with SiCl ₄ vapor.
Substrate 9 heated to high temperature by mixing H ₂ gas and PH ₃
By sending it upward, n-type silicon is grown as a single crystal. Next, the implantation of PH ₃ is stopped to form the active region 13, and only silicon is grown. Or B ₂ H ₆
P-type silicon may be formed using a dopant such as . Next, n-type silicon is epitaxially grown again in the same manner as the drain region 12 to form the source region 14. Here, the semiconductor layer 12,1
3 and 14, unnecessary portions are removed by etching, leaving only the gate portion and the extraction portions of the source and drain electrodes, as shown in FIGS. 2a to 2c. Next, the entire surface of the substrate is coated with silicon nitride using plasma CVD, etc.
It is covered with an insulating layer 16 of SiO ₂ or the like, and contact holes are made by etching to take out the drain and source electrodes. Then, molybdenum is vacuum-deposited over the entire surface and unnecessary parts are removed by etching to form a drain electrode 11, a source electrode 15, and a gate electrode 17, thereby manufacturing the vertical MIS-FET of the present invention. Further, although a method of forming each region in a layered manner using a vapor phase growth method is shown here, other epitaxial growth methods may be used, and each region may also be formed by a diffusion method.

[Effect of the invention] As explained above, the present invention provides a mesa-shaped vertical type
In the MIS-FET, signals are input independently from each other, and multiple gate electrodes with different areas are provided, so there is no increase in parasitic capacitance.
This has the effect of easily configuring a multi-input circuit that performs signal processing by weighting the gains of a plurality of input signals.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional vertical MIS-FET.
Figures 2a to 2c are vertical type, which is the basis of the present invention.
FIG. 3 is a side sectional view showing another configuration example of the vertical MIS-FET, which is the basis of the present invention, and FIG. 4 is a diagram showing the configuration of the MIS-FET. FIG. 5 is a plan view showing an embodiment of the invention, and is a diagram showing voltage-current characteristics in the embodiment of FIG. 4. 9... Insulating substrate, 11, 21... Drain electrode, 12... Drain region, 13... Active region,
14... Source region, 15, 25... Source electrode, 16, 26... Insulating layer, 17, 27a, 27
b, 27c, 27d...gate electrodes.

Claims (1)

[Claims] 1. In a vertical MIS-FET in which a source region, an active region, and a drain region made of semiconductor are stacked in a mesa shape on a substrate, and a gate electrode is provided on the side surface of the active region with an insulating layer interposed therebetween, the substrate is A single-crystal insulating substrate, in which a source region, an active region, and a drain region are formed of a single-crystal semiconductor, and the gate electrode is composed of a plurality of gate electrodes each having a different area and to which signals are input independently of each other. Vertical MIS-FET featuring: