JPH044619B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a serial LSI that facilitates data transfer between a transmission LSI of a serial input/output port that connects an external device to a control device and a transmit/receive data buffer memory within the control device. This relates to a data transfer control device for input/output ports.

[Technical Background of the Invention and Problems Therein] There are already established techniques for serial input/output methods between control devices or between control device terminals. For example, for electrical/mechanical connections, RS-232C,
RS-422, 20mA current loop, full-duplex, half-duplex, unidirectional communication, synchronous transmission, asynchronous transmission, no-procedure, basic procedure, BSC procedure, etc. are widely used. There are many IC/LSIs that support these functions on the market.

Current issues are transmission speed and processing speed and miniaturization. That is, as control devices become more sophisticated, a large number of serial input/output ports are required, and the transmission speed of terminals and the like is increasing, making it necessary for control devices to support a large number of high-speed ports.

One of the problems in this case is the transfer process between the transmission LSI and the buffer memory. For example, if the transfer is performed by a microprocessor, it will not only put a heavy load on the microprocessor, but also may not be able to complete the transfer process in time.As a countermeasure to this problem, as shown in Figure 3, a buffer FIFO (FIFO) (in first out) or using multiple DMA controllers as shown in Figure 4.
DMA transfer is performed, but there is a problem that this increases the size of the circuit.

[Object of the Invention] An object of the present invention is to provide a data transmission control device for serial input/output ports, which enables miniaturization of the device by reducing the data transfer circuit of the control device having a large number of high-speed serial input/output ports. It is said that

[Summary of the Invention] The present invention comprises a microprocessor, a control ROM, an internal RAM, a serial input/output transmission/reception data buffer memory, an electrical level conversion circuit for transmitting/receiving serial input/output signals to/from external equipment, and controlling serial input/output. A serial input/output port consisting of a transmission LSI for data transfer between the transmission LSI and the serial input/output transmission/reception data buffer memory.
A control device consisting of a DMA controller and an interrupt controller that performs serial input/output with external equipment is equipped with a request conversion circuit that generates a DMA request signal or an interrupt signal from the transmission/reception data transfer request signal from the transmission LSI. During synchronous/asynchronous transmission during duplex communication, transmit and receive data transfer request signals are
One DMA channel is used alternately to transfer transmit/receive data using the OR signal as a DMA request signal, and during asynchronous transmission during full-duplex communication, the transmit data transfer request signal is converted to an interrupt signal and the microprocessor Transmission is performed using interrupt processing, and the received data transfer request signal is processed by the DMA controller as a DMA request signal. This enables data transfer with one port/one DMA channel for high-speed serial input/output, and the control circuit This is a data transfer control device for input/output ports that has been miniaturized.

[Embodiments of the Invention] The present invention conventionally relates to transmission/output of a serial input/output port.
The two DMA channels allocated for reception are made into one channel, and the data transfer between the transmission LSI and the buffer memory is changed to 1 channel because in the case of synchronous/asynchronous transmission of half-duplex communication, transmission and reception are not performed at the same time. In the case of full-duplex asynchronous transmission using two DMA channels alternately, the received data cannot be made to wait, but the transmission can be synchronized with the timing of the control device, so the DMA
The channel is used only for reception, and transmission is performed by a microprocessor using an interrupt. The configuration of the control circuit used in the present invention is shown in FIG. FIG. 2 is a detailed diagram of the request conversion circuit in FIG. 1.

In FIG. 1, the control device includes a microprocessor 1, a control ROM 2, an internal RAM 3, a buffer memory 4 for serial input/output transmission/reception data, a plurality of serial input/output ports 5, a DMA controller 6 having DMA channels equal to the number of ports, and ports. It consists of an interrupt controller 7 having several minutes of interrupt inputs.

In addition, the input/output port 5 is connected to a level conversion circuit 8 that converts the electrical level of serial input/output signals, a transmission LSI 9 that controls input/output operations, and transmit/receive data transfer request signals 10 and 11 output from the transmission LSI.
It is composed of a request conversion request circuit 14 that generates a DMA request signal 12 and an interrupt signal 13.

Each LSI and controller are connected to an internal bus 15, allowing the microprocessor 1 to write commands and read status.

Furthermore, the DMA controller 6 and the interrupt controller 7 have interrupt signals 16 and 17, respectively.
Generates an interrupt to the microprocessor 1.

Further, as shown in FIG. 2, the request conversion circuit 14 converts the transmission/reception data transfer request signals 10 and 11 from the transmission LSI into a DMA request signal 12 and an interrupt signal by a switching signal 18 specified by a switch or the like. Generate 13.

In addition, the microprocessor, interrupt controller,
The DMA controller, transmission LSI, electrical level conversion circuit, etc. are well known and have no direct relation to the present invention, so their explanation will be omitted.

In the case of half-duplex communication (synchronous/asynchronous transmission), transmission and reception are not performed simultaneously;
Since the DMA channel can be switched and used, the switching signal 18 is set to logic "1" and the transmission and reception data transfer request signal 1 output from the transmission LSI 9
0 and 11 are ORed and converted into a DMA request signal 12. At this time, interrupt signal 13 is inhibited.

Also, microprocessor 1 transmits data except when transmitting.
The LSI 9 is enabled for reception/disabled for transmission, and the DMA controller 6 is also designated as a reception buffer area and placed in a reception standby state.

That is, during reception, upon reception of serial data, the reception data transfer request signal 11 is made active by the transmission LSI 9, and the DMA request signal 12 is made active by the request conversion circuit 14. This results in
The DMA controller 6 writes the received data from the transmission LSI 9 to the buffer memory 4 by DMA.

The microprocessor 1 periodically reads the status of the transmission LSI 9 or learns of the start of reception from a reception start interrupt from the transmission LSI, and thereafter periodically checks the contents of the received text and executes reception completion processing.

Also, during transmission, microprocessor 1 is the transmission LSI
9 is set to enable transmission/disable reception, the DMA controller 6 is set with the storage address of the transmission data and the number of transmissions, and the DMA controller is activated. After that, the DMA controller writes the transmission data to the transmission LSI.

The microprocessor 1 learns of the completion of transmission by reading the status of the periodic DMA controller 6 or by an interrupt from the DMA controller, and performs transmission completion processing.

Further, in the case of full-duplex communication (asynchronous transmission), the switching signal 18 is set to logic "0". As a result, the request conversion circuit 14 converts the transmission data transfer request signal 10 from the transmission LSI 9 into an interrupt signal 13, and notifies the microprocessor 1 of the transmission request via the interrupt controller 17. The microprocessor 1 thereby writes the transmission data into the transmission LSI 9.

When receiving, DMA is performed using the same procedure as the half-duplex communication described above.
Data transfer is performed by

[Effects of the Invention] As explained above, according to the present invention, the number of DMA channels is reduced to 1 channel/1 port using a request conversion circuit, so the number of DMA controllers is reduced to 1/2 of the conventional one, and the number of DMA controllers is reduced to 1/2. This makes it possible to perform high-speed transmission using multiple ports and to downsize the device.

[Brief explanation of drawings]

Figure 1 is a system diagram showing one embodiment of the present invention, Figure 2 is a system diagram showing an embodiment of the present invention.
This figure is a circuit diagram showing details of the request conversion circuit in FIG. 1, and FIGS. 3 and 4 are system diagrams showing an example of a conventional data transfer control device, respectively. 1...Microprocessor, 2...Control ROM,
3...Internal RAM, 4...Transmission/reception data buffer memory, 5...Serial input/output port, 6...
DMA controller, 7... interrupt controller,
8...Electric level conversion circuit, 9...Transmission LSI, 1
4...Request conversion circuit, 15...Internal bus.

Claims (1)

[Claims] 1 Microprocessor, control ROM, internal RAM,
A serial input/output port consisting of a serial input/output transmit/receive data buffer memory, an electrical level conversion circuit for transmitting and receiving serial input/output signals to and from external equipment, and a transmission LSI for controlling serial input/output; Output Send/Receive Data Buffer In a control device that includes a DMA controller and an interrupt controller that perform data transfer between memories and performs serial input/output with external equipment, a DMA request signal or a A request conversion circuit that generates an interrupt signal is provided, and the request conversion circuit converts an OR signal of transmit and receive data transfer request signals into a DMA request signal during synchronous/asynchronous transmission during half-duplex communication,
A data transfer control device for a serial input/output port, characterized in that during asynchronous transmission during full-duplex communication, a transmission data transfer request signal is used as an interrupt signal and a reception data transfer request signal is used as a DMA request signal.