JPH0440549A - Information processor - Google Patents

Abstract

PURPOSE:To shorten the memory access time by detecting a request signal outputted from information processing resources at the time when an information transmission line is not used, outputting an access arbitrating signal to a memory part at the time when its request signal is detected and starting the access arbitration. CONSTITUTION:A memory access control circuit 56-n is provided with a request signal detecting means 56-1a for detecting a request signal outputted from information processing resources at the time when an information transmission line is not used, and an access arbitration executing means 56-1b for outputting an access arbitrating signal at the time when the request signal is detected. In such a state, when the request signal is detected, the access arbitration is started so that a competition of a memory access operation and a memory refresh operation in a memory part is prevented. In such a way, the access arbitrating operation exerts no influence on the access time, and the processing efficiency and the utilization efficiency of a hardware can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a dynamic random access memory (
The present invention relates to an information processing device that has a DRAM (hereinafter referred to as a DRAM) as a storage element and accesses the DRAM such as reading/writing information, and particularly relates to an information processing device that ensures smooth operation during access.

(Prior Art) When using DRAM as a storage element in an information processing device, apart from normal memory access operation, DRAM
The storage unit of is capacitance, and one bit of information is expressed depending on whether a certain amount of charge is stored in this capacitance.

The information stored in this capacitance is stored in the DRAM.
It is not always held while the power is turned on. If left as is, the charge in the capacitance will inevitably be lost, making it impossible to store accurate information.

Therefore, it is necessary to periodically perform a memory refresh operation on the DRAM.

However, from information processing device resources such as processors, DRA
Since the memory access operation for M occurs asynchronously with respect to the memory refresh operation, a conflict occurs between the memory access operation and the memory refresh operation.

Conventionally, in order to arbitrate this contention (hereinafter referred to as access arbitration), a timing operation as shown in FIG. 2 has been performed.

FIG. 2 is a timing chart showing an example of the operation timing of a conventional information processing apparatus, and shows a case where the required number of clocks for memory access is 35 clocks and access arbitration is relatively slow.

Referring to FIG. 2, the operation when the processor in the information processing apparatus performs read access to the DRAM via the bus will be described.

First, a request signal BRp is sent out by the processor at the II L I+ level to request the right to use the bus. At this time, if no information processing device resource other than the processor is using the bus, the bus control circuit sends the bus ground signal BGp to the information processing device resource “L”.
″ level.

The information processing device resource acquires the bus right and becomes a bus mask, and the bus busy signal B indicates that the bus is in use.
After sending out B at 11 L 1 level fS, the request signal BRp and the bus ground signal BGp become "H" level and are released.

Next, after transmitting the address ADR, the processor transmits the address strobe signal ASR at "L" level to indicate that the address ADR is valid. DR that has information on the information storage location corresponding to address ADH
The AM starts an access arbitration operation (period RAA in the figure) upon receiving the address I/lobe signal ASR.

At this time, if the arbitration operation and memory refresh operation start at the same time (or within the same clock), the memory access operation is given priority, and if the memory refresh operation is in progress, the memory access operation is performed immediately after the memory refresh operation ends. Start.

When this arbitration operation is completed, data DAT is sent,
After that, the memory accredited signal MAC is set to 11 L I
Send at + level. The processor receives the memory access signal MAC and outputs the address strobe signal AS.
R is set to "H" level, and the sending of the address ADH is stopped. Then, after an appropriate time, the memory access signal MAC is set to II HI+ level, and the sending of the data DAT is stopped. The processor that receives the memory access signal MAC outputs the bus busy signal BB.
is set to "H" level to release the state in which the bus is being used (hereinafter referred to as the busy state). The above method avoids conflicts between memory access operations and memory refresh operations.

Further, assuming that the number of clocks required for memory access is 30 clocks, the operation timing when access arbitration is relatively fast is as shown in FIG.

(Problem to be Solved by the Invention) However, in the above information processing device, since access arbitration is performed after the address is determined, data cannot be sent during the access arbitration.As a result, memory access Since it takes time, there is a problem that the bus is occupied for a long time and the processing efficiency and hardware utilization efficiency are significantly reduced.

The present invention provides an information processing device that solves the problem of the prior art, which is that the bus occupancy time becomes long and the processing efficiency and hardware utilization efficiency are significantly reduced.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a request for the right to use an information transmission path. an information processing resource to be output; a memory access control circuit that outputs an access arbitration signal and a read/write signal based on the output of the information processing resource; and after performing a predetermined access arbitration operation based on the access arbitration signal, the The information processing apparatus includes a memory section that reads/writes data corresponding to the address based on a read/write signal, and takes the following measures.

The memory access control circuit includes request signal detection means for detecting the request signal output from the information processing resource when the information transmission path is not in use, and when the request signal is detected by the request signal detection means, and access arbitration execution means for outputting the access arbitration signal.

(Function) Since the present invention has configured the information processing device as described above,
When performing a memory access operation from the information processing device resource to the memory section, the request signal detection means detects a request I~ signal output from the information processing resource when the information transmission path is not used.

Upon detection, the access arbitration execution means outputs an access arbitration signal to the memory section to start access arbitration, and acts to prevent conflict between the memory access operation and the memory refresh operation in the memory section.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration block diagram of an information processing apparatus showing an embodiment of the present invention.

This information processing device is of a bus-coupling type and has information processing device resources such as a processor 50, an input/output control bag W51, a disk control device 52, and a storage device 53. These information processing device resources are interconnected via a bus 54 which is an information transmission path, and after acquiring the right to use the bus 54 by outputting a request signal BRp requesting the right to use the bus 54, It has a function of outputting the address ADR of and exchanging data with other information processing device resources. The bus 54 includes a bus control circuit 55 that arbitrates the usage state of the bus 54 and a plurality of memory access control circuits 56.
-1 to 56-n are connected to each other, and each memory access control circuit 56 to 1 to 56n4 is a memory section DR,
AM modules 571 to 57-n are connected.

The memory access control circuits 56-1 to 56-n receive a signal for causing a DRAM module to perform a refresh operation in response to a signal from an information processing device resource, and a DRA.
This circuit outputs control signals such as read/write signals for reading/writing the M modules 57-1 to 57n and access arbitration signals for access arbitration.

Here, the memory access control circuits 56-1 to 56-
n is a request signal detection means 56-1a that detects a request signal BRp output from the information processing resource when the bus 54 is not used; and a request signal detection means 56-1a.
When the request I to signal BRp is detected, the access arbitration signal is transmitted to the DRAM modules 57-1 to 57-n.
and access arbitration execution means 56-1b for outputting to.

The DRAM modules 57-1 to 57-n are circuits that perform a predetermined access arbitration operation based on an access arbitration signal, and then read/write data DAT corresponding to the address ADR using a read/write signal.

FIG. 4 is a detailed view of the main part of FIG. 1.

The bus control circuit 55 has a terminal for a request signal BRp for requesting the right to use the bus 54, a terminal for a bus ground signal BGp indicating successful acquisition of the bus right which is a request from the processor 50, and a terminal for the bus ground signal BGp used by the bus 54. It is provided with a terminal for a bus busy signal BB indicating that the bus is currently in operation.

In addition to the terminal for the request signal BRp, the terminal for the bus ground signal BGp, and the terminal for the bus busy signal BB, the processor 50 also has a terminal for the address ADR, and an address strobe to indicate that the address ADR is valid. Terminal for signal ASR, memory accredited signal MA
It has a terminal for C and a terminal for inputting data DAT.

Furthermore, the memory access control circuits 56-1 to 56-n have a terminal for a bus ground signal BGp, a terminal for a bus busy signal B
It has a terminal for address ADR, a terminal for address strobe signals A and SR, a terminal for memory access signal MAC, and a terminal for inputting data DAT. These terminals are interconnected via a bus 54.

FIGS. 5(a) and 5(b) are timing charts showing the operation of FIG. FIG. 3 is a diagram showing a case where the speed is relatively high.

Next, referring to FIG. 5, the processor 50
The operation when performing read access to the AM module 57-H will be described.

(A) Operation when access arbitration is relatively slow. First, the processor 50 sends a request signal BRp to the bus 54 to request the right to use the bus 54. All memory access control circuits 56-1 to 56-
Each of the n riffers 1 to the signal detecting means detects that the request signal BRp is sent when the bus 54 is not in a busy state. At the time of detection, each access arbitration execution means transmits the access arbitration signal to the DR and AM modules 57-1 to 57-1.
Output to 7-n. As a result, access arbitration shown in FIG. 5(a>) is started.

On the other hand, upon receiving the request signal BRp, if no other information processing device resources are using the bus 54 at this point, the bus control circuit 55 sends a bus ground signal to the processor 50 at the "L" level. As a result, the processor 50 acquires the right to use the bus 54 and becomes the bus 54 master, and the processor 50 receives the bus 54 elbow signal from I
I LI Transmit at I+ level. Then processor 5
0 sends out the address strobe signal at II L I+ level after sending out the address ADH.

The sent address ADH is the DRAM module 57
If it does not exist within the range of -1, the access arbitration operation is immediately interrupted when the address ADH is determined, and subsequent processing such as memory refresh is continued. Further, if the sent address ADR exists within the range of the DRAM module 57-1, the following operation is performed.

If the access arbitration operation and the memory refresh operation start at the same time (within the same clock), the memory access operation is given priority, the access arbitration operation is immediately terminated, and the memory refresh operation is started immediately after the memory access operation is completed. Start.

If the memory refresh operation is in progress, the memory refresh operation is continued, and the memory access operation is started immediately after the memory refresh operation. In addition, if none of the above occurs, that is, if the start of the access arbitration operation and the start of the memory refresh operation are not simultaneous, and if the memory refresh operation is not in progress, the memory access operation is given priority and the access arbitration operation is performed immediately. finish. In addition,
FIG. 5(a) shows that there are two Gs when the memory refresh operation is not in progress.

When this access arbitration operation is completed, the data DAT is read from the memory storage location corresponding to the sent address ADH, and after sending the data DAT to the bus 54, the memory access signal is The address strobe signal is returned to the ``H'' level in response to this memory accelerator signal, and in response to this address strobe signal, the sending of the address ADR is stopped.

Then, after a predetermined period of time has elapsed, the memory clearance signal is returned to the "H" level and transmission of the data DAT is stopped.In response to the return of the memory clearance signal, the processor 50 raises the busy signal BB to the II HI+ level. to clear the busy state.

(B) Operation when access arbitration is relatively fast The operation is almost the same as when access arbitration is relatively slow, as shown in FIG.
The operation is as shown in b).

This embodiment has the following advantages.

The operation when access arbitration is relatively slow is shown in Figure 5 (
As shown in a), since the time required for access arbitration is relatively long, DRA
It is determined whether or not there has been an access to the M module 57-1, and a memory access operation is performed. However, depending on the system, the operating speed of the bus control circuit 55 may be slow due to its physical conditions, the distance between each information processing device resource may be remote, or the operating speed of the memory access control circuit 56-1 may be slow. The faster the access arbitration operation ends before the address ADR is determined, the faster the memory access control circuit 56 can operate.
-1 may work. In such a case, in the prior art, as shown in FIG. 3, the access arbitration operation still affects the access time, but in this embodiment, as shown in FIG. will no longer affect.

Next, as an example, the case of the prior art shown in FIGS. 2 and 3 will be compared with the case of the present embodiment shown in FIGS.

The number of locks required for each memory access operation, ie, from the time the request signal BRp is sent until the bus busy signal BB is released, is as follows.

35 clocks when the access arbitration is relatively slow as shown in Figure 2, 26 clocks when the access arbitration is relatively slow as shown in Figure 5(a), and when the access arbitration is relatively high as shown in the third factor. In the case where the access arbitration is relatively fast as shown in FIG. 5(b), it is 24 clocks.

In this way, in this embodiment, the access time of the memory access operation to the DRAM module can be minimized.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following variations.

(B) In the above embodiment, a bus coupling method is adopted, but the system is not limited to this, and may be used in a system coupled by a multi-stage network using a data exchanger such as a Batcher network, a Banyan network, or an Omega network. Can be applied. in this case,
The input/output port of the multi-stage network is bus 5, which is the information transmission path.
Corresponds to 4.

(b) In the above embodiment, a plurality of DRAM modules are provided, but it is not necessarily necessary to provide a plurality of DRAM modules, and only one DRAM module may be provided.

(Effects of the Invention) As described in detail above, according to the present invention, when performing a memory access operation on a memory section, a request signal output from an information processing resource when an information transmission path is not used is detected. However, when the request signal is detected, an access arbitration signal is output to the memory unit to start access arbitration, which reduces memory access time and prevents performance degradation associated with memory access. .

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an information processing device showing an embodiment of the present invention, FIG. 2 is a timing chart showing operation timings of a conventional information processing device, and FIG. 3 is a timing chart showing operation timings of a conventional information processing device. Timing chart, Figure 4 is a detailed view of the main part of Figure 1, Figures 5 (a) and (b) are the first
2 is a timing chart showing the operation of FIG.
(b) is a diagram showing a case where access arbitration is relatively slow;
) is a diagram showing a case where access arbitration is relatively fast. 50... Processor, 54... Bus,
56-1 to 56-n...Memory access control circuit, 561a...Request signal detection means, 5
6-1b... Access arbitration execution means, BRp...
...Request signal, DAT...Data.

Claims (1)

[Scope of Claims] An information processing resource that outputs a predetermined address after acquiring the right to use an information transmission path by outputting a request signal requesting the right to use the information transmission path; a memory access control circuit that outputs an arbitration signal and a read/write signal, and after performing a predetermined access arbitration operation based on the access arbitration signal, reads/writes data corresponding to the address based on the read/write signal; In the information processing apparatus, the memory access control circuit includes: request signal detection means for detecting the request signal output from the information processing resource when the information transmission path is not used; An information processing apparatus comprising: access arbitration execution means for outputting the access arbitration signal when the request signal is detected by the signal detection means.