JPH043621A - A/D converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a successive approximation type A/D converter, and more specifically, to shortening the conversion time of a successive approximation type A/D converter.

<Prior art> Fig. 5 is a circuit configuration diagram showing an example of a conventional successive approximation type A/D converter. In Fig. 0, 1 compares the analog value to be measured and the analog output of the D/A converter. comparator,
2 is a microprocessor that performs predetermined control and settings from the output signal of the comparator 1; a control means 3 that controls bits according to the output signal of the comparator 1; and a setting that performs bit settings according to the output of the control means 3. Equipped with utensils. 5 is a D/A converter which takes in the digital signal set by the setting device 4 and converts it into an analog value 6 Next, the present invention will be explained in detail using FIGS. 5 and 6. FIG. 6 is a flowchart showing the operation of this A/D converter. First, all bits of the setting device 4 in the microprocessor 2 are set to 0, and at the same time as the start, the control means 3 sets 1 to the most significant bit of the setting device 4.Next, the digital value of this setting device 4 Convert it to D/A,
Comparator 1 compares it with the analog value to be measured. Steps A to C> Here, if the output of comparator 1 is 1, that is,
If the output of the D/A converter 5 is larger than the analog value to be measured, the control means 3 resets 0 to the most significant bit of the setting device 4, and checks whether this access bit is the least significant bit. , if it is not the least significant bit, the control means 3 sets the next bit of the setter 4 to 1. Then, setter 4
The set value of is converted by D/A converter 5, and
and compare it again with the analog value to be measured. Steps D to G, B to C> If the output of comparator 1 is O, that is, D
If the output of the /A converter 5 is smaller than the analog value to be measured, leave that bit as is and check whether that bit is the least significant bit, and if it is not the least significant bit,
The control means 3 sets the next bit of the setter 4 to 1. Thereafter, the set value of the setter 4 is converted by the D/A converter 5, and input to the comparator 1, where it is again compared with the analog value to be measured.

Steps D, F to G, B to C> After this, the output of the D/A converter 5 and the analog value to be measured are sequentially compared by the comparators, and the output of the comparator 1 is 1.
If so, put 0 in the access bit at that time and 1 in the next bit. If the output of comparator 1 is 0, the access bit at that time remains 1 and 1 is written to the next bit. Thereafter, the setting and comparison are repeated until the access bit becomes the least significant bit, and when the access bit becomes the least significant bit, the digital value of the setter at that time is output as an A/D conversion output. Steps B to H> In the conventional successive approximation type A/D converter, conversion is performed by sequentially setting and comparing bits one by one.

<Problems to be Solved by the Invention> In such conventional successive approximation type A/D converters, resolution and conversion time conflict, and if the number of bits of the A/D converter is increased to improve resolution, conversion At times, there is a problem that the number of analog comparisons for each bit increases, resulting in a longer conversion time.

On the other hand, if a high-speed D/A converter or high-speed operational amplifier is used in the A/D converter in order to shorten the conversion time, there is a problem in that the price increases accordingly.

The present invention has been made to solve these problems, and the present invention aims to provide a successive approximation type A/D converter that can shorten conversion time. Means> The present invention is an A/D converter having the following configuration.

In a successive approximation type A/D converter, a D/A converter, an analog sample holder that captures and stores the analog output of the D/A converter, an analog output potential of the D/A converter, and an analog sample holder that captures and stores the analog output of the D/A converter; A voltage divider that divides the potential between the analog potentials stored in the sample holder into equal potentials, and a voltage divider that is attached to the analog sample holder and can be switched between the D/A converter side and the voltage divider side. a changeover switch, a plurality of comparators that input the analog value to be measured and introduce the potential divided by the voltage divider as a reference voltage for comparison; an encoder that encodes the outputs of the plurality of comparators as input; a microprocessor that reads a signal from an encoder and sends a digital signal corresponding to the signal to the D/A converter; the microprocessor is configured to set a digital signal to be sent to the D/A converter; reading/writing means for reading the output of the encoder and writing a setting value into the digital signal setting means; controlling reading/writing of the reading/writing means; controlling one of the digital signal transmissions of the digital signal setting means; and controlling the digital signal transmission of the digital signal setting means; and a control means for controlling a changeover switch of a sample holder, and dividing the number of bits of the D/A converter equally into a plurality of bit blocks, and sequentially comparing the number of bits of the D/A converter with the analog value to be measured starting from the upper bit block. It is characterized by

Further, the voltage divider divides the voltage by a number obtained by subtracting 1 from a power of 2, the comparators are present as many as the number to be divided, and the number of output bits of the encoder is as many as the power. do.

In the present invention, the number of bits of the D/A converter is equally divided into unit bit blocks, and the output of the D/A converter is calculated by subtracting 1 from the power of 2 using this number of bits as an exponent. The voltage is divided by the number of voltage dividers, and inputted to a comparator having a number equal to the power of 2 minus 1, and compared with the analog value to be measured.

Thereafter, the bit output of the comparator equal to the power of 2 minus 1 is encoded by an encoder into the number of bits equal to the power of 2, and this bit information is sent to the microprocessor. This microprocessor operates as follows.

The bit information of the encoder is read by the read/write means based on the control signal of the control means, and the bit information of the encoder is written into the unit bit block being accessed at that time of the digital signal setting means. Thereafter, the control means switches the changeover switch of the analog sample Holter to the D/A converter side, provides a transmission signal to the digital signal setting means, and the digital signal setting means sends the digital signal to the D/A converter. After the analog conversion value of the D/A converter is stored in the analog sample holder, the control means switches the changeover switch to the voltage divider side. Thereafter, the control means gives a write signal to the read/write means, and the read/write means sets all 1s to the next unit bit block into which the bit information of the encoder is written. The control means again sends a transmission signal to the digital signal setting means, and the digital signal is D/A converted. After this, the analog output potential of the D/A converter and the analog potential of the analog sample Holter are divided into equal potentials by a power of 2 minus 1 using a voltage divider, and the analog value to be measured is again used by the comparator. and sends the output of the comparator to the encoder.

In this way, the bit information from the encoder is put into the unit bit block of the digital signal setting means, and the operation of putting 1 in the next unit bit block and D/A conversion is repeated until the lowest bit. value A
/ Obtain the D conversion value.

<Example> The present invention will be described in detail below using the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a successive approximation type A/D converter according to the present invention. In this embodiment, the number of bits of the D/A converter is 12, the unit bit block is 3 bits, and the number of comparators is 7. In the figure,
5 is a 12-bit D/A converter, 6 is a switch SW is D
An analog sample holder 7 captures and stores the analog output of the D/A converter 5 when it is on the /A converter 5 side, and provides a terminal potential to the voltage divider 7 when the switch SW is on the voltage divider 7 side. This voltage divider is composed of resistors R1 to R7 having the same resistance value, and divides the analog output potential of the D/A converter 5 and the analog potential of the analog sample holder 6 into seven equal potentials. The partial pressure here refers to the difference between the analog output potential of the D/A converter 5 and the analog potential of the analog sample holder 6 divided into seven equal parts.
This is the addition of the analog potential of the analog sample holder. SW is a changeover switch 80 to 86 that switches between the D/A converter 5 side and the voltage divider 7 side based on the control signal.
9 are seven comparators that compare the analog value to be measured as an input voltage and the potential divided by the voltage divider 7 as a reference voltage, and 9 encodes the output signals of the seven comparators 80 to 86 into 3-bit bit information. It is an encoder that

10 is a microprocessor, which is composed of the following elements. 11 sets a 12-bit digital signal and
A digital signal setting means 12 that sends a digital signal to the /A converter 5 reads the 3-bit bit information of the encoder 9 and writes it to the digital signal setting means 11, and also writes 1 to the unit bit block based on the control signal. 13 is a read/write means 12 for controlling read/write and digital signal setting.
This is a control means that controls the digital signal transmission of the switch SW and the switching of the switch SW.

Next, the present invention will be explained in detail using FIGS. 1, 2, and 3. FIG. 2 is a flowchart showing the operation of the A/D converter according to the present invention, FIG. 3 is a diagram showing the status of digital values of the digital signal setting means, and FIG. 4 is a number corresponding to the digital values in FIG. In the diagram showing positions on a straight line, X is a full span of 12 bits. Here, it is assumed that the measured value is point y in FIG.

First, based on the write signal of the control means 13,
1 of the digital signal setting means in the reading/writing means 12
Set all 2 bits to 0 (Figures 3 and 4).

Thereafter, based on the transmission signal from the control means 13, the digital signal from the digital signal setting means 11 is sent to the D/A converter 5 for D/A conversion. side to hold the conversion value of the D/A converter 5 in the analog sample holder 6, and switch the switch SW to the voltage divider 7@ to set the potential on the low potential side of the resistor R7 in the voltage divider 7 to 0. . After that, the control means 1
3 sends a write signal to the read/write means to write 11N2) into the upper three bits (most significant bit block) of the digital signal setting means 11 (FIGS. 3 and 4). Steps a to e> Thereafter, the digital signal whose most significant bit block is 11H2) is D/A based on the transmission signal of the control means 13.
The signal is sent to converter 5 and subjected to D/A conversion. The voltage divider 7 divides the voltage between this D/A-converted analog potential and the analog potential of the analog sample Holter 6 (the interval between ■ and ■ in Fig. 4) into seven equal potentials, and this potential is used to be measured. The analog values are introduced as reference voltages into seven comparators 80 to 86 that receive analog values for comparison. In this example, y in FIG.
Since there is an analog value to be measured at the point, the comparator 80~
83 outputs 0, and comparators 84 to 86 output 1. Next, the encoder outputs 1.
The output of 6 is encoded into 3-bit bit information as a 7-bit input signal.

At this time, since the three comparators 84 to 86 output 1, the encoder 9 outputs 011(2).

Thereafter, based on the read signal from the control means 13, the read/write means 12 reads the output signal of this encoder (in this case, 011f2), and writes 111[2) in the previous stage of the digital signal setting means 11 based on the write signal. 011f2) is written in the bit block (Figures 3 and 4). At this time, the top 3 digital conversion values
The bit is fixed at 011(2).

Steps f to i> Next, check whether the bit block into which the 3 bits of bit information have been entered is the least significant bit block (last 3 bits), and if it is the least significant bit block, the bit block in the digital signal setting means 11 is checked. The digital signal is output as a digital conversion output. However, in this case, since it is not the least significant bit block, the digital signal is sent to the D/A converter 5 and subjected to D/A conversion based on the transmission signal of the control means 13. Similarly to the previous stage, based on the control signal from the control means 13, the switch SW is switched to the D/A converter 51111 to store the analog conversion value in the analog sample holder, and then the switch SW is switched to the voltage divider 71PJ.

This operation limits the potential of the resistor R7 in the voltage divider 7 on the low potential side. Thereafter, based on the write signal from the control means 13, the reading/writing means 12 writes 111(2) to the next bit block (next 3 bits) in the digital signal setting means 11 (Figs. 3 and 4). ■).

The idea is to reduce the resolution by 1/8 by making the bit block 3 bits. Steps j to n> Note that the explanation of the control operation of the control means 13 will be omitted after this.

After this, the digital signal 01 of the digital signal setting means 11
1111000000(2) is D/A converted. This D
The voltage divider 7 divides the voltage between the /A converted analog potential and the analog potential of the analog sample Holter 6 (the interval between ■ and ■ in Figure 4) into seven equal potentials, and the comparators 80 to 8
6 as a reference voltage and compare it with the analog value to be measured. Here, since the measured value is point y in Figure 4, the outputs of comparators 80 and 81 are O, and the outputs of comparators 82 to 86 are O.
The output of becomes 1. Therefore, the input to encoder 9 is
The result is 0011111(2), and since 51 is set, the encoder 9 encodes it to 101(2). After that, the 3-bit information 101F is read and written by the reading/writing means 12.
2) is read and set to 1 at the front stage of the digital signal setting means 11.
101(2) to the bit block where 11(2) was written
(Figure 3, Figure 4 ■). Here, check that this bit block is the least significant bit block. In this case, since it is not the least significant bit block yet, the digital signal of this digital signal setting means 11 is 01110100.
0000(2) is D/A converted and held in an analog sample Holter. As a result, the digital conversion value of the analog value to be measured is determined up to the upper 6 bits. Thereafter, the read/write means 12 writes 111f2) into the bit block adjacent to the bit block in which 1ON2) was written in the previous stage of the digital signal setting means 11 (FIGS. 3 and 4). Steps f to n> After that, in order to further reduce the resolution to 1/8 as in the previous step, the fourth step
Divide the interval between ■ and ■ in the figure into seven equal parts, input this analog potential to the comparators 80 to 86, and repeat the same operation.The operation after this is the loop of steps f to n in Figure 2. Therefore, detailed explanation will be omitted. Assuming that the output of encoder 9 is 001 (2) in this loop and the output of encoder 9 is 110 (2) in the next loop, the digital conversion value is determined to be the upper 9 bits and the upper 12 bits, respectively. Figure 3 ■, ■). Here, step j in Figure 2
When checking whether it is the least significant bit block, the upper 12 bits are determined, so the digital signal setting means 11 outputs the digital conversion output 0111 based on the signal from the control means 13.
Outputs 01001110(2). Step f′″
-n, f~j, o) Therefore, when the resolution of the D/A converter is 12 bits and the unit bit block is 3 bits, the A/D of the analog value to be measured is
In the conversion, three bits are determined at a time, and the conversion result can be obtained by four successive approximations.

In this embodiment, the number of bits of the D/A converter is 12 bits and the unit bit block is 3 bits, but the number of bits of the D/A converter is 16 bits, the unit bit block is 4 bits, and the comparator is 15 bits. Similar results can be obtained by using both.

<Effects of the Invention> As explained in detail above, in the present invention -A/D
By dividing the number of bits of the D/A converter included in the converter into equal bit blocks, it is now possible to perform successive comparisons using unit bit blocks, which was previously performed successively one bit at a time. In comparison, the conversion speed can be significantly increased.

Also, in order to speed up the conversion speed, you can use the expensive high-speed D
It is not necessary to use an A/A converter or a high-speed operational amplifier, and it is possible to realize a relatively low-cost A/D converter.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of a successive approximation type A/D converter according to the present invention, FIG. 2 is a flowchart showing the operation of the present invention, and FIG. 3 is a diagram showing the digital value of the digital signal setting means. FIG. 4 is a diagram showing the position on the number line according to the digital values in FIG. 3. FIG. 5 is a circuit configuration diagram showing an example of a conventional successive approximation type A/D converter. FIG. 6 is a flowchart showing the operation of a conventional A/D converter. 5...D/'A converter 6...Analog sample holder 7...Voltage divider 80-86...Comparator 9...Encoder 10...Microprocessor 11...Digital signal setting means 12 ...Reading/writing means 13...Control means SW...Switch R
~R7...Resistance

Claims (2)

[Claims] (1) In a successive approximation type A/D converter, a D/A converter, an analog sample holder that captures and stores the analog output of the D/A converter, and an analog output potential of the D/A converter. , a voltage divider that divides the potential between the analog potentials stored in the analog sample holder into equal potentials; and a voltage divider that is attached to the analog sample holder and switches between the D/A converter side and the voltage divider side. a plurality of comparators that input the analog value to be measured and perform comparison by introducing the potential divided by the voltage divider as a reference voltage; and an encoder that encodes the outputs of the plurality of comparators as input. and a microprocessor that reads the signal from the encoder and sends a digital signal corresponding to the signal to the D/A converter, and the microprocessor sets the digital signal to be sent to the D/A converter. digital signal setting means; reading and writing means for reading the output of the encoder and writing a set value into the digital signal setting means; controlling reading and writing of the reading and writing means; controlling digital signal transmission of the digital signal setting means; a control means for controlling a changeover switch of the analog sample holder, dividing the number of bits of the D/A converter equally into a plurality of bit blocks, and sequentially comparing the number of bits of the D/A converter with the analog value to be measured starting from the upper bit block. An A/D converter characterized by: (2) The voltage divider divides the voltage by a number obtained by subtracting 1 from a power of 2, the comparators are present as many as the number to be divided, and the number of output bits of the encoder is as many as the power. The A/D converter according to claim (1).