JPH04340645A - Memory access circuit - Google Patents

Abstract

PURPOSE:To shorten the access time by providing a memory control circuit which always repeatedly transfers data stored in a memory to a memory read circuit on the central processing unit side. CONSTITUTION:A shared memory read control part 124 is provided with a memory read circuit 123, and this circuit 123 is connected to an access control part 159 as the memory control circuit in a shared memory device through communication lines 125, 128, and 166 and connectors 126 and 142. The access control part 159 connected to a memory 141 always repeatedly reads out data in the memory 141 having a certain capacity from head data to end data. This data is always transferred to the memory read circuit 123 on the memory access request source side through the communication line 128. This memory read circuit 123 detects the address of data transferred through the communication line 128; and when it coincides with a specific address designated by the memory access request source, data sent at this time is transferred to the memory access request source.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access circuit for a memory device, and more particularly to a device for shortening the access time of a shared memory device installed at a remote location.

0002

2. Description of the Related Art Conventional memory access circuits employ a system in which a memory reading circuit sends out an address of a memory to be accessed, and as a result, a memory control circuit transfers data in the corresponding memory to the memory reading circuit. This method is a procedure widely used not only for semiconductor memories but also for storage devices in general, including external storage devices such as disk devices and magnetic tape devices, and access circuits based on the same principle have been used for shared memories as well. For example, the explanation of memory access method in semiconductor memory is “68000
"Microcomputer" (edited by Ryoichi Mori, published by Maruzen Co., Ltd., 1983) Chapter 3 Interface Signals and Bus Operations, Section 3.2 Bus Operations. Also, for an explanation of the operation method for input/output when accessing external storage devices, see "MVS Functions and Structure".
(Masahiko Senda, published by Kindai Kagakusha, 1986) Chapter 5 Input/output management functions, Section 5.3 Access method routine functions,
Section 5.6 shows the functionality of the channel subsystem.

0003

However, in the above conventional technology, the access time increases in proportion to the distance of the communication line between the memory reading circuit and the memory control circuit.
Therefore, there is a problem in that the shared memory device cannot be installed in a remote location in order to keep the access time within a certain period of time. That is, the memory read circuit sends an address value to the memory control circuit, the memory control circuit sends the memory contents at that address location to the memory read circuit,
In order for the memory reading circuit to receive the data, it is necessary to transfer data back and forth through a communication line between the memory reading circuit and the memory control circuit. An object of the present invention is to provide a memory access circuit that suppresses the access time of a shared memory device installed in a remote location and shared by a plurality of central processing units to within a certain period of time regardless of distance.

0004

[Means for Solving the Problems] The above object is to provide a memory control circuit that constantly repeats data stored in a certain capacity of memory in a shared memory device and transfers it to a memory reading circuit on the central processing unit side; This is achieved by using a signal line with a sufficiently large throughput as a communication path between the memory control circuit and the memory reading circuit.

[0005]

[Operation] When the shared memory device and the central processing unit connected thereto are far apart, one-way communication between them takes a very long time even when communicating at the speed of light. For example, if the shared memory device and the central processing unit are 10 kilometers apart, even if they could communicate at the speed of light, it would take about 33 microseconds, and the data would be returned after sending the read address for traditional shared memory access. A round-trip communication is required to wait for this, and it takes about 66 microseconds, which is twice that time. Since this shared memory access time is determined by the distance of the communication path and the signal propagation speed of the communication path, the access time increases in proportion to the distance between the shared memory device and the central processing unit. Ignoring minute overhead factors such as transmission of communication protocol data, the shared memory access time can be expressed as shown in the following equation. (Conventional shared memory access time) = 2 x (communication path distance) / (signal propagation speed) On the other hand, if the shared memory device and the central processing unit are connected using a communication line with high throughput such as an optical fiber, for example, Data transfer of about 1 gigabyte per second can be expected. This is a throughput that can transfer 4 kilobytes of data in 4 microseconds.

[0006] Therefore, by creating a structure in which 4 kilobytes of data is constantly transferred from the shared memory device to the central processing unit, and the central processing unit acquires the data when it detects the desired data, it takes a maximum of 4 microseconds. You can read data from shared memory within This maximum read time is determined by the throughput of the communication path and the size of the memory that is constantly and repeatedly transferred, so it is constant regardless of the distance between the shared memory device and the central processing unit, and there is minimal overhead such as address synchronization signal transfer and protocol conversion. Ignoring the factors, it can be expressed as the following formula. (Maximum read time for continuous repeat transfer method) = (Repeated data transfer amount) / (throughput of communication path) Therefore, (Maximum read time for continuous repeat transfer method) <(
It can be seen that the access time of the shared memory access using the constant repeat transfer method is shorter and faster within the range of the shared memory access time of the conventional method. In other words, if we transform the above inequality, (distance of communication path) > (signal propagation speed) x (repeated data transfer amount) / (2 x
(Throughput of communication path)) It can be seen that when the distance of the communication path is long enough to satisfy the above equation, accessing the shared memory by the constant repeat transfer method according to the present invention is effective.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the basic configuration of a memory access circuit according to the present invention. In FIG. 1, a memory access request source is a central processing unit 101 (CPU), which is connected to one shared memory device 141. Inside the central processing unit 101,
In order to accept memory access requests instructed via the common bus 102, a shared memory read control unit 124 that accepts read requests and a shared memory write control unit 103 that accepts write requests are provided.

A memory read circuit 123 is provided in the shared memory read control unit 124, and includes a communication line 125, a connector 126, a communication line 128, a connector 142, and a communication line 1.
66 to an access control unit 159, which is a memory control circuit provided within the shared memory device 141. A memory write circuit 112 is provided in the shared memory write control unit 103, and includes a communication line 104, a connector 126,
It is connected via a communication line 127, a connector 142, and a communication line 151 to a write control distribution unit 152, which is a write control distribution circuit provided within the shared memory device 141.

Within the shared memory device 141 is a memory unit 160 having a capacity of 4 kilobytes for holding memory contents.
are provided, and one access control unit 1 is provided for each one.
59 is an address line 161, a data line 163, a control line 16
Connected by 2. A set of these access control section 159 and memory unit 160 is connected to memory access unit 1.
It's called 58. When configuring a large-capacity shared memory device, the required number of memory access units 158 is provided to secure the capacity.

In this embodiment, as shown later using FIGS. 2a and 2b, the shared memory device 141 has a total capacity of 4 megabytes and 1024 memory access units 1.
It is equipped with 58. The addresses assigned to the shared memory device 141 are from X'7FC00000' to X'7
FFFFFFFF', and 4096 bytes of addresses are allocated to each memory access unit 158, and the first memory access unit, memory access unit 0 158, has addresses from X'7FC00000' to X' Addresses up to 7FC00FFF' are assigned. Here X'aaa
The notation of a' indicates the value of aaaa in hexadecimal notation. The same notation will be used below.

Further, the internal configuration of central processing unit 101 shown in FIG. 1 will be explained in detail. Shared memory access requests are communicated via address bus 115, data bus 113, and control bus 114 within common bus 102. Common bus 1
The read request generated at 02 is input to the shared memory read control unit 124 via the bus lead-in lines 116, 117, and 118 connected to the common bus 102, and the request address is from X'7FC00000' to X'7FC00.
If it is up to FFF', the selector circuit 122 is in the selected state and the read request is sent to the address line 119,
Reading circuit 1 via data line 121 and control line 120
23.

[0012] The address of the read request generated on the common bus 102 is from X'7FC00000' to X'7FC00.
Unless it is before FFF', the selector 122 will be in a non-select state and the read request will not be transmitted to the read circuit 123. The detailed operation of the reading circuit 123 will be explained later with reference to FIG. When the data arrives, an operation is performed to output the data as read data to the data bus 113 of the common bus 102.

A write request generated on the common bus 102 is sent to a bus lead-in line 105 connected to the common bus 102.
, 106 and 107, the shared memory write control unit 10
3, and the requested address is X'7FC0000
If the range is from 0' to
The data is transmitted to the write circuit 112 via. Common bus 1
The address of the write request that occurred in 02 is X'7FC0
Unless it is between 0000' and X'7FFFFFFFF', the selector 111 will be in a non-selected state and the write request will not be transmitted to the write circuit 112. The detailed operation of the write circuit 112 will be explained later using FIG.
The write request address and write data pair are sent to the address.

Here, the write request is sent to the shared memory device 1.
In the write control distribution section 41, it is necessary to determine which memory access unit 158 is to be accessed, so it is necessary to transfer all 32 bits of address information. Address line 108 has a width of 32 bits. On the other hand, in the read circuit 123 of the shared memory read control unit 124, each memory access unit 15
Since it is sufficient to determine the data position within 8, the address line 119 has a width of 12 bits.

Furthermore, the shared memory device 141 shown in FIG.
will be explained in detail. The shared memory device 141 is provided with signal line connectors equal to the number of central processing units that can be connected, and as in this embodiment, three connectors are provided.
In the case of a shared memory device 141 to which two central processing units are connected, three connectors 142, 143, and 144 are provided. Write signal lines 127, 145, 147 and read signal lines 128, 146, 148 are connected to each connector from outside the shared memory device 141, and each write signal line is connected to the write control distribution unit 152 inside. A signal line 166 that connects the signal lines 151, 150, 149 and each reading signal line to the access control circuit 159.
, 156, 157, etc. are posted.

The write control distribution unit 152 receives write requests arriving from all central processing units connected to the shared memory device 141, calculates the number of the corresponding memory access unit 158 from the write address, and selects the number of the write target. The write request is distributed to the access control section 159 via a signal line 155 connected to the memory access unit 158. The access control unit 159 is a control circuit that constantly repeatedly sends out the 4 kilobytes of data recorded in the memory unit 160 to the three central processing units, and is used to synchronize data transfer with the central processing unit 101. The write request received from the write control distribution unit 152 is executed while the read operation of the memory unit 160 is stopped. These light control distribution parts 15
The detailed operation of step 2 will be explained later using FIG. 5, and the detailed operation of the access control unit 159 will be explained later using FIG.

Next, the overall connection configuration of the shared memory system in this embodiment will be explained using FIGS. 2a and 2b. The shared memory device has a total capacity of 4 MB and 10
24 memory access units 158-1 to 158
-1024. There are three central processing units connected, 101-1 and 101-2, and three central processing units (not shown) that are connected in exactly the same way.
1 connectors 142, 143, and 144.

The internal structure of each central processing unit 101 is exactly the same for all three units, so the explanation will be based on the central processing unit 101-1. The central processing unit 101-1 has an instruction processing unit 201 that executes programs, an input/output processing unit 202 that executes input/output, and a main memory 203 that is a memory inside the central processing unit. It is connected. In the central processing unit 101-1, shared memory read control units 124-1 to 124-1024 are further provided corresponding to the memory access units 158-1 to 158-1024 in the shared memory device 141,
These are also connected to the instruction processing device 201 and the like by a common bus 102. Only one shared memory write control unit 103 is provided in the central processing unit 101-1, and is connected to the instruction processing unit 201 and the like via the common bus 102, and is connected to the write control distribution unit 152 in the shared memory device 141. It is connected.

The signal line assembly 204 connecting the central processing unit 101-1 and the shared memory device 141 consists of one write signal line and 1024 read signal lines. Shared memory write control unit 1 in central processing unit 101-1
The signal line 104 connected from 03 is a collection of signal lines 20
The signal line 1 is connected to the signal line 151 connected to the write control distribution unit 152 in the shared memory device 141 via the 1024 shared memory read control units 124 via the signal line 1
25-1 to 125-1024 are a collection of signal lines 204
are connected to signal lines 166-1 to 166-1024, which are connected to 1024 access control units 159, respectively. Similarly, a collection of signal lines 2 from other central processing units
05 and 206 are connected, and the light control distribution unit 1 is connected from each.
Signal lines 150, 149 to 52 and signal lines 156-1 to 156-102 to 1024 access control units 159
4, 157-1 to 157-1024 are connected.

[0020] Inside the shared memory device 141, write requests are received from three central processing units, and the requests are forwarded from 1024 memory access units 158-1 to 1.
A write control distribution unit 152 that distributes write request signal lines 155-1 to 155-1024 to 58-1024 is connected to three read request signal lines for receiving read requests from each central processing unit. There is 1
024 access control units 159-1 to 159-10
A memory unit 1 has a storage capacity of 24 and 4 kilobytes and is connected to the access control unit 159 by a signal line 207.
60-1 to 160-1024.

Next, the reading circuit 123 will be explained in detail using FIG. The reading circuit 123 reads only the requested portion of the 4 kilobyte memory contents that are constantly repeatedly sent from the shared memory via the communication line 125 to the data on the common bus 102 of the central processing unit via the data line 121. This is a circuit that sends data to the bus 113. In this embodiment, the signal line 125 is assumed to be a high-speed serial signal line such as an optical fiber cable, and the optical signal is converted into an electrical signal via the receiving module 311 and sent to the signal line 312. The serial signal is converted to 32 by a serial/parallel conversion circuit 313.
It is converted into a parallel signal in units of bits (=4 bytes) and sent to the data line 315. When this conversion circuit 313 finishes converting 32 bits of serial data into parallel data, the data enable signal becomes '1'. The data enable signal becomes '1' for a certain period of time and then returns to '0'.

The signal appearing on the signal line 125 is a repetition of a 16-byte synchronization signal and a 4-kilobyte data signal, as shown in FIG. It has a detect sync signal line 314 which becomes '1'. The 1024 counter 307 is a counter for calculating the address of the data obtained from the signal line 125 in 4-byte units, and the data enable signal 3
A count-up operation is executed at the rising edge of 03. This causes the counter 307 to always indicate the address of the data currently arriving from the shared memory. This counter stops counting up by the reset signal 323 on the control line and the OR signal 308 on the detect sync signal line 314, and when both signals become '0', the value of X'FFF' set in the fixed value register 301 is A value is preset in counter 307. The comparison circuit 310 compares the address 3 requested to be read by the memory access request source.
06 and the address 309 of the data currently arriving from the shared memory device 141, and if they match, it outputs '1' to the signal line 316, and if they do not match, it outputs '0'. Perform a comparison. However, since data transfer is performed in units of 4 bytes, 12 of address line 119
The signal line 305 for the lower 2 bits of the book address is not used for comparison and is connected to the termination circuit 304, and only the signal line 306 for the upper 10 bits is input to the comparison circuit 310.

A signal line 120, which is a collection of control lines, is connected to a control circuit 330 to send and receive necessary control signals. In the read/write signal 319, '1' indicates a read request, and '0' indicates a read request.
' represents a write request. Data request signal 321
indicates that the data of the address appearing on the address line 119 is requested while it is '1', and the reading circuit 123 sets the data in the read data register 324, and the data acknowledge signal 325 is set to '1'. ', the data request source reads the data via the data line 121, and then returns the data request signal 321 to '0'. The condition for setting data in the read data register 324 and setting the data acknowledge signal line 325 to '1' is to set the data to the control line 319 from the common bus 102 via the control line 120.
is in read request mode and data request 32
1 is '1', the transfer data on the signal line 125 is not synchronous data (that is, the detect sync signal line 314 is '0'), and the requested address and the address of the current data are equal (that is, the comparison result The value of the signal line 316 is '1'). When this condition is met, the set input of the read data register 324 becomes '1', the value of the data 315 arriving from the shared memory 141 at that point is set in the register 324, and the buffer 32
2, the data acknowledge signal 3 is slightly delayed because it goes through 2.
25 becomes '1'. Next, an example of the operation of the reading circuit 123 will be explained in chronological order.

FIG. 4 shows that an access request for address X'000' is transmitted from a memory access request source, the requested data is set in the read data register 324, a data acknowledge signal 325 is sent, and the memory access request source receives the data. This is a specific example of the operation from receiving the data request signal 321 to setting the data request signal 321 to '0'.

This specific example will be explained below with reference to FIG. Note that FIG. 3 is also referred to. The received signal 312 is serial data, and until the first data is sent, it is synchronized data 4.
01 is being sent. While the synchronization data is being sent, the detect sync signal 314 of the serial-parallel conversion circuit 313 becomes '1' (431). Therefore, the count-up operation of the output 309 of the 1024 counter is stopped (44
1). At this time, the read request for address X'000' has already been sent, so the address line 119 is set to X'000'.
′ is held. Also, data request signal 3
21 is also '1' (461). At this time, the read data register 324 retains the previously set value and has not reached a specific value (481). When the synchronization data on the received signal 312 disappears and reception of the 0th word begins, the detect sync signal 314 becomes '0' (485). As a result, the value of X'FFF' set in the fixed value register 301 becomes 1024
7, and the value of the output 309 of the 1024 counter is preset to X'FFF' (492). 0th
Until the data of the word (first 32 bits) is complete, the value of the data output line 315 is undefined 411, and the data enable signal remains at '0' (421).

When the reception of the 0th word is completed and the reception of the 1st word begins (486), the data value of the 0th word is output to the data line 315 of the serial/parallel conversion circuit 313 (41
2), the data enable signal 303 becomes '1' (4
88,422). As the data enable signal 303 rises, the output 309 of the 1024 counter is counted up and becomes X'000' (490, 443). At this time, the value of the output 309 of the 1024 counter and the value of the address line 119 become equal, and the control line 1
20 is in the read request mode, the data request 321 is '1', and the transfer data on the signal line 125 is not synchronous data, so the value of the 0th word is stored in the read data register 324. is set (482), and the data acknowledge signal 325
also becomes '1' (472, 493). After the memory access request source detects the data acknowledge signal, it reads the data from the data bus and disables the data request signal 321 and address line 119 (494, 462,
452). Independently of the series of operations triggered by these data acknowledge signals 325, the data enable signal 3
03 becomes '0' (423).

Next, when the data of the first word appearing in the received signal 312 (data from the 33rd bit to the 64th bit counting from immediately after the synchronization signal 401) is completed, the serial/parallel conversion circuit 313 outputs the data to the data line 315. Outputs 1 word of data (487, 413) and outputs data enable signal 303
becomes '1' (489, 424), and the output 309 of the 1024 counter is further counted up to become X'001.
' (491, 444). Here, since the data request signal 321 has already become '0' (462), the data acknowledge signal 473 has not become '1', and therefore the data of the first word is transferred to the read data register 32.
4 and is not sent to the memory access request source. The reading circuit 123 operates as described above and can always return the data that is arriving at the reading circuit to the memory access request source, so there is no need to communicate with the shared memory 141 and high-speed response is possible.

Next, the operation of the write circuit 112 will be explained in detail using FIG. The write circuit 112 receives a 32-bit address value 108, a 32-bit data value 109, and a control signal 107 from the common bus 102 of the central processing unit 101.
and sends a write request to the shared memory 141 via the signal line 104. Among the control signals 107, read/
When the write signal 906 indicates write, that is, '0', and the data request signal 907 becomes '1', it means writing the value indicated by the data line 109 into the memory indicated by the address line 108, so the parallel-to-serial conversion circuit 901
The strobe signal is set to '1' (909), and the synchronous data transfer signal sink is set to '0' (910). The parallel-to-serial conversion circuit 901 always transmits a synchronization data pattern on the signal line 902 until the strobe signal becomes '1'. When the strobe signal 909 becomes '1', the address input 108 and data input 109 at that moment are saved,
Next, it is converted into serial data and sent out on the signal line 902. Since the signal line 104 connected to the shared memory is an optical fiber, the signal line 902 which is an electrical signal is converted into an optical signal and sent out via the transmission module 903.

Next, using FIG. 5, the shared memory device 141
The operation of the light control distribution section 152 provided in the device will be described in detail. The write control distribution unit 152 is a shared memory 141
This is a circuit that receives write requests from each central processing unit connected to the central processing unit, and in this embodiment, three signal lines 1
51, 150, and 149 are connected. Write request data sent from the central processing unit side is transmitted through the signal line 151.
, 150, and 149 are transmitted in the format shown in FIG. This format is a format in which data write requests are transmitted in units of one word, and a synchronization pattern of 4 bytes or more 601
A set of 4 bytes of address data 602 and 4 bytes of write data 603 is transmitted.

Serial write request data transmitted on signal line 151 is converted into an electrical signal by receiving module 530-1 and sent to signal line 531-1. Next, the signal is received by the serial-parallel conversion circuit 532-1.
It converts into 2-bit address data 533-1 and 32-bit write data 534-1, and sets the respective values in address register 537-1 and data register 536-1. The timing of setting to both registers is given by the signal line 535-1 of the serial/parallel conversion circuit. This write request is input to the selector 501 via signal lines 538-1 and 539-1.

Similarly, write requests transmitted from other central processing units are also input to the selector 501. The selector 501 selects signal lines 502 and 5 in the order in which write requests arrive.
03 to the write request alignment queue 504. Address and data pairs of write requests arranged in queue 504 are stored in write request transmission buffers 510-1 to 510-5.
10-1024. One buffer 510 is prepared for each memory access unit 158 to be written, and it is determined whether or not to transmit the request to the signal line 155 depending on the value of each select input 506. The select input 506 is the upper 20 bits of the 32-bit address data 505, and when the value of the upper 20 bits matches the address of the target memory access unit 158, signal transmission to the signal line 155 is permitted. . For example, in the case of buffer 510-1, signal transmission to signal line 155-1 is permitted only when the upper 20 bits of the write request address are X'7FC00'. The signal line of the lower 12 bits of the address data 505 is used as a write address within the memory access unit 158, so it is directly transmitted to the access control unit 159 via the buffer 510. Also, 32-bit data 50
9 and control line 508 as well as buffer 510 and signal line 5.
15, 514 to the access control unit 159. Control lines 508 and 514 are for controlling the timing of writing data into the buffer.

Next, the operation of the access control section 159 will be explained in detail using FIG. The access control unit 159 is a circuit that constantly repeatedly reads the 4 kilobyte memory and sends it to the three central processing units, and when a write request exists, sends write data to the memory at the corresponding address. Access to the 4 kilobyte memory unit 160 is via address line 161, data line 162 and control line 16.
3, and data transfer to the central processing unit is performed by communication lines 166, 156, 157. Also,
Acceptance of the write request is transferred via the signal line 155.

The access control unit 159 uses the basic clock 7
It operates based on a four-phase clock generated by a timing generation circuit 727 connected to 25 via a signal line 726. The first phase is input to a 4112 counter 724 via a signal line 728 to generate a 13-bit counter output, but when it counts up to 4111, it becomes 0. The value of the most significant bit 723 of this counter 724 is '
When the bit is 1', the parallel-to-serial converter circuit 716 generates a synchronization signal, and when the most significant bit 723 is '0', it executes a data read operation from the memory unit 160. Further, since the write operation is executed when the most significant bit 723 is '1', the write operation can be executed while the data read process necessary for transmitting data to the central processing unit is paused.

To explain in more detail, the counter 724
While the count value is between 0 and 4095, the most significant bit 723 is '0', so the data sent to the parallel-to-serial conversion circuit 716 is not synchronous data but parallel data 71
It is 4. This data line 714 is connected to the read data register 712, and since a read mode signal is sent to the control circuit 722 at this time, the bidirectional buffer 720 is controlled by the signal line 721 so that it is connected to the read register 712. and reads the 32-bit data sent from the memory unit 160 via the signal line 713. The read data address is the counter 72
Using the lower 12 bits of the output value of No. 4, it is set in the address data register 708 via the signal line 719, selector 706 and signal line 707. Here, since the read data is in 4-byte units, the values set in the address register 708 are in 4-byte increments. Memory unit 16
Data transfer from 0 to the read data register is executed in response to the data request signal 718, and this signal is output by the second phase clock of the timing generation circuit 727. Furthermore, the data set in the read data register 712 is converted from parallel data to serial data according to the timing of the third phase clock output 717, and is sent to three optical fibers for three different central processing units via a signal line 715. Transmission module 7 which is a cable driver
30, 731, and 732.

[0035] The value of the counter 724 is from 4096 to 411.
1, the value of the most significant bit 723 is '1', so synchronization data continues to be sent from the parallel-to-serial conversion circuit 716, and during that time the data for synchronization is received via the signal lines 515, 514, and 513. Execute a write request. Write requests that arrive while the access control unit 159 is sending data are stacked in the write request queue 704, and when synchronous data transfer begins, the address is transferred to the signal line 705.
and is set in the address register 708 via the selector 706 and signal line 707. Also, the data is on the signal line 70
9 to the write data register 710,
Data is written to a corresponding address within the memory unit 160 in response to a write request signal transmitted through the control line 163. The format of the data generated by the access control unit 159 and transferred to the central processing unit is a 16-byte synchronized data pattern 8 as shown in FIG.
01 and 4 kilobytes of data 802 are repeated (
803, 804).

Next, the period of "repeated data transfer" which makes the memory access according to the present invention superior to the conventional memory access will be described. If the time it takes for the first byte of data sent from the access control unit to reach the memory reading circuit is T, then the cycle of "repeated data transfer" must be within 2T to achieve the above advantage. This is because the time required for memory access in the conventional method is the time from the CPU sending out an address to the memory receiving the address (Ta), the time from the memory receiving the address to sending data (α), and the memory The time from when the CPU sends data to when the CPU receives the data (Tb
) and becomes Ta+α+Tb. here,
If T, Ta, and Tb are approximately equal, and the overhead of circuit operation on the memory side is small, the above required time is 2
T+α, where α is a negligible time. In order for the memory access according to the present invention to be superior to the conventional memory access, the cycle of "repeated data transfer" must be made shorter than the above-mentioned required time. Therefore, it is necessary to keep the period of "repeated data transfer" within 2T.

Next, the effects of this embodiment will be explained using FIG. 10. FIG. 10 is a graph in which the vertical axis represents the access time during a read operation, and the horizontal axis represents the distance between one central processing unit and the shared memory device. Here, a case is shown in which the throughput of the connection communication line between the central processing unit and the shared memory is 1 gigabyte per second (10 gigabit per second), and the storage capacity per memory access unit 158 is 4 kilobytes. A straight line 1004 indicates the access time according to the method of the present invention, and the access time is always maintained at about 4 microseconds regardless of the distance. On the other hand, the broken line 1003 is the access time according to the conventional address sending-data receiving method.
Access time increases as distance increases. In other words, in the conventional method, in order to keep the access time within a certain amount of time, the longest connection distance must be within a certain distance.For example, in order to keep the access time within 4 microseconds, the longest connection distance must be about 0.5 km. However, according to the present invention, there is no limit to the maximum connection distance, and the central processing unit and the shared memory device can be placed at an arbitrary distance. Therefore, it can be seen that the method of the present invention is advantageous in terms of access time when shared memory devices are installed at a distance of 0.5 km or more (1005).

Further, the access time during write operation will be explained using FIG. 11. FIG. 11 is a graph in which the vertical axis represents the access time during a write operation, and the horizontal axis represents the distance between one central processing unit and the shared memory device. straight line 1
Reference numeral 104 indicates an access time according to the method of the present invention, which is always constant regardless of distance and is 1 microsecond or less. The write process referred to here is only a process for transmitting a set of a write address and write data, and does not particularly affect the throughput of the communication line. A broken line 1103 indicates the access time of the conventional method when a method of waiting for a write completion report after simultaneously executing address sending and write data sending is adopted. In the case of writing, the method of the present invention is completely advantageous in terms of access time, but such a throwaway write method is common in other fields as a cache memory access method or a data transfer method in local area networks. is known for. Although the method of applying the present invention to the case where two or more central processing units share one shared memory device has been described above, the memory access circuit of the present invention is limited to use in a shared memory device. Rather, it can be applied to general access to storage devices installed in remote locations.

[0039]

Effects of the Invention According to the present invention, the access time of a storage device located in a remote location can be suppressed within a certain period of time regardless of the distance, so that the central processing This has the effect that a computer system can be configured with less performance degradation without considering the distance between the two.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of a memory access circuit according to the present invention.

FIG. 2a shows a half of the overall configuration of the connection between a shared memory device and a central processing unit;

FIG. 2b shows another half of the overall configuration of the connection of the shared memory device and the central processing unit;

FIG. 3 is a diagram showing the configuration of a memory reading circuit.

FIG. 4 is a timing chart showing the operation of the memory reading circuit.

FIG. 5 is a diagram showing the configuration of a write control distribution section.

FIG. 6 is a diagram showing the structure of data transferred from the central processing unit to the shared memory.

FIG. 7 is a diagram showing the configuration of an access control section.

FIG. 8 is a diagram showing the structure of data transferred from the access control unit to the memory reading circuit.

FIG. 9 is a diagram showing the configuration of a memory write circuit.

FIG. 10 is a diagram showing the relationship between shared memory device connection distance and read access time.

FIG. 11 is a diagram showing the relationship between shared memory device connection distance and write access time.

Claims (14)

[Claims] 1. A memory access circuit that reads storage contents in a memory corresponding to an address in response to a specific address specified by a memory access request source, the memory access circuit being connected to a memory reading circuit and connected to the memory via a communication path. and an access control unit connected to the memory reading circuit, the access control unit constantly repeatedly reading data from the first data to the last data in the memory of a certain capacity, and transmitting the read data to the memory reading circuit via a communication path, The memory reading circuit detects the address of the data transferred via the communication path, and transfers the data to the memory access request source at the time when the data at the designated specific address is transferred via the communication path. A memory access circuit featuring: 2. The memory access circuit according to claim 1, wherein the data that is constantly and repeatedly transferred from the access control unit to the memory reading circuit includes the first data to the last data in the memory of a certain capacity, and A memory access circuit comprising a control unit and synchronization data for calculating an address value of data transferred between the memory reading circuit. 3. The memory access circuit according to claim 2, wherein a communication path is provided with a memory write circuit, and the memory write circuit sends a specific address and specific data designated by a memory access request source through the communication path at any time. and the access control unit stores the transferred set of the specific address and specific data, and the access control unit executes the transfer of the synchronous data to the memory reading circuit. A memory access circuit characterized in that the stored specific address and specific data value are read out within a certain time period, and the specific data is written to the specific address of the memory. 4. A memory access circuit that reads storage contents in a memory consisting of a plurality of memory units corresponding to a specific address specified by a memory access request source, the memory access circuit having a selector for each memory unit. and a memory read control unit comprising a memory read circuit, an access control unit connected to a memory unit, and a communication path connecting the memory read control unit and the access control unit, each access control unit having a corresponding constant The data from the first data to the last data in the memory unit of the capacity is constantly repeatedly read and transferred to the corresponding memory read control unit via the corresponding communication path, and the selector of the memory read control unit is specified by the source of the memory access request. Among the specific addresses, only those corresponding to the addresses assigned to the corresponding memory unit are selected and output to the memory read circuit of the memory read control section, and the memory read circuit reads the data transferred via the communication path. A memory access circuit that detects an address and transfers the data at the designated specific address to the memory access request source when the data is transferred via a communication path. 5. The memory access circuit according to claim 4, wherein the data that is constantly and repeatedly transferred from the access control section to the memory reading circuit includes data from the first data to the last data in the memory unit having a certain capacity; A memory access circuit comprising an access control section and synchronization data for calculating an address value of data transferred between the memory reading circuit. 6. The memory access circuit according to claim 5, further comprising: a memory write control section comprising a selector and a memory write circuit; and a memory write control section connected to the memory write control section via a communication path and connected to the access control section. A write control distribution unit is provided, and the selector of the memory write control unit specifies the specific address specified by the memory access request source only when the specific address specified by the memory access request source corresponds to an address assigned to all memory units. The data is output to the memory write circuit of the memory write control section, and the memory write circuit transfers the specific address and specific data specified by the memory access request source to the write control distribution section via the communication path at any time. , the write control distribution unit sends the specific address and specific data to the access control unit connected to the memory unit corresponding to the specific address, and the access control unit that has received the specific address and specific data sends them. Save and
Read the stored specific address and specific data value and write the specific data to the specific address of the corresponding memory unit during the time when the synchronous data is being transferred to the memory reading circuit. A memory access circuit characterized in that: 7. A plurality of memory access request sources, a memory reading circuit connected to each memory access request source, an access control section connected to a shared memory of a certain capacity, the access control section and the memory reading circuit. A memory access circuit for a shared memory comprising a communication path that separately connects the communication path, wherein the access control unit constantly repeatedly reads data from the first data to the last data in the shared memory of a certain capacity, and The memory reading circuits detect the address of the data transferred via the communication path, and the data at the specific address specified by the connected memory access request source is communicated. A memory access circuit characterized in that the data is transferred to the memory access request source at the time the data is transferred via the memory access line. 8. The memory access circuit according to claim 7, wherein the data that is constantly and repeatedly transferred from the access control unit to the memory reading circuit includes the first data to the last data in the fixed capacity shared memory; A memory access circuit comprising an access control section and synchronization data for calculating an address value of data transferred between the memory reading circuit. 9. The memory access circuit according to claim 8, wherein a memory write circuit is connected to each memory access request source, a first-in first-out stack circuit is connected to the access control unit, and the stack circuit and each memory write circuit are connected to the memory access circuit. A communication path is provided to connect the circuits, and each memory write circuit transfers a specific address and specific data specified by a connected memory access request source to the first-in, first-out stack circuit at any time via the communication path, The access control unit receives and stores the specific address and specific data from the first-in, first-out stack circuit, and the access control unit receives the specific address and specific data from the first-in, first-out stack circuit, and stores the specific address and the specific data stored in the memory read circuit within a time when the synchronized data is transferred to the memory read circuit. A memory access circuit characterized in that the memory access circuit reads a specific data value and writes the specific data to the specific address of the shared memory. 10. A memory access circuit for a shared memory that transfers storage contents in a shared memory consisting of a plurality of memory units to each request source in response to each memory access request from a plurality of memory access request sources. , an access control unit connected to each memory unit constituting the shared memory, a memory read control unit connected to each memory access request source and provided corresponding to each memory unit for each request source, and each memory. A communication path is provided to separately connect a read control section and a corresponding access control section. It is transferred to the corresponding memory read control unit of the access request source via a communication path, and the selector of the memory read control unit corresponds to the address assigned to the corresponding memory unit among the specific addresses specified by the memory access request source. The selected data is output to the memory read circuit of the memory read control section, and the memory read circuit detects the address of the data transferred via the communication path, and the data at the designated specific address is output to the memory read circuit of the memory read control section. A memory access circuit characterized in that the data is transferred to the memory access request source at the time the data is transferred via the memory access circuit. 11. The memory access circuit according to claim 10, wherein data that is constantly and repeatedly transferred from each of the access control units to each of the corresponding memory reading circuits is stored at the beginning of each of the corresponding memory units of fixed capacity. A memory access circuit comprising data to end data and synchronization data for calculating an address value of transfer data between each of the access control units and each of the corresponding memory reading circuits. 12. The memory access circuit according to claim 11, further comprising a memory write control unit comprising a selector and a memory write circuit connected to each memory access request source, and connected to each memory write control unit via a communication path. and a write control distribution unit including a first-in, first-out stack circuit connected to each of the access control units, and a selector of each of the memory write control units is configured to assign a specific address designated by a memory access request source to all memory units. The specific address and specific data specified by the memory access request source are output to the memory write circuit of the memory write control section only when the address corresponds to the specified address, and each memory write circuit outputs the specific address and specific data specified by the memory access request source. is transferred to the write control distribution unit via a communication path at any time, and the write control distribution unit
A specific address and specific data transferred from each memory write circuit are stored in the first-in, first-out stack circuit, and the specific address and specific data are sent to the access control unit connected to the memory unit corresponding to the specific address. The access control unit that has received the specific address and specific data stores them and reads out the saved specific address and specific data value within the time when the synchronous data is being transferred to the memory reading circuit. A memory access circuit, wherein the specific data is written to the specific address of the corresponding memory unit. 13. The memory access circuit according to claim 7, wherein each access control section transfers data read from a corresponding memory unit to each memory access request source connected to the memory access request source. A memory access circuit comprising a data transmission distribution circuit that simultaneously transmits data to each of the memory reading circuits. 14. The memory access circuit according to any one of claims 1 to 13, wherein data is sent from the access control unit and transferred until it reaches the memory reading circuit via a communication path. time 2
A memory access circuit characterized in that the memory access circuit constantly repeats data from the first data to the last data in the certain capacity memory and transfers it to the memory reading circuit using a cycle shorter than twice the time.