JPH04332011A - Clock monitoring system - Google Patents

Abstract

PURPOSE:To detect a noise included in a clock of a TTL level by providing this clock monitoring system with a comparing part and a noise detection part and detecting a positive polarity noise included in an 'L' level area of an input clock. CONSTITUTION:The comparing part 100 compares the voltage of an input clock with a reference voltage Vref1. The comparing part 100 outputs the input clock a prescribed signal in accordance with the input clock or a compared result that the voltage of a positive or negative polarity noise included in the 'L' level area of the input clock is larger or smaller than the reference voltage Vref1. At the time of inputting the output of the comparing part 100, the noise detection part 300 outputs a signal indicating the detection of noise only when the voltage of the positive polarity noise is larger than the reference voltage Vref1. Thus the positive polarity noise included in the 'L' level area of the input clock can be detected. In the case of using the clock monitoring system for a device processing a synchronizing signal or the like, a noise included in a TTL level clock can be detected without observing its waveform and a circuit can be miniaturized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock monitoring system used in devices that handle synchronous signals.

[0002] At this time, there is a need for a clock monitoring system that detects noise existing in a TTL level clock.

0003

2. Description of the Related Art Devices or packages that handle synchronous signals often receive a clock from another package and use the clock for signal processing. If picked up, the device or package may malfunction. Conventionally, there was no method for detecting noise present in a TTL level clock, so the only way to do so was to observe the clock waveform with an oscilloscope or the like.

0004

As mentioned above, conventionally there was no method for detecting noise existing in a TTL level clock, so the only way to do so was to observe the clock waveform with an oscilloscope or the like. Therefore, if noise is picked up on the cable or wiring that is the supply path of the clock, there is a problem that the package that uses this clock for signal processing may malfunction.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a clock monitoring method for detecting noise present in a TTL level clock.

[0006]

[Means for Solving the Problems] The above problems are solved by the circuit configuration shown in FIG. 1 or 2. That is, in FIG. 1 showing the first invention, the "L" level region and the "H" level region
In a device that performs signal processing using an input clock consisting of a level region, 100 compares the voltage of the input clock with a reference voltage Vref1, and detects positive polarity noise that mixes into the input clock or the "L" level region of the input clock. The first comparator section outputs a predetermined signal depending on whether the voltage of the reference voltage Vref1 is higher or lower than the reference voltage Vref1.

300 inputs the output of the first comparator 100 so that the voltage of positive polarity noise is equal to the reference voltage Vref.
The first noise detection unit outputs a signal indicating detection of noise only when the value is greater than 1.

The device is configured to detect positive polarity noise mixed into the "L" level region of the input clock. Further, in FIG. 2 showing the second invention, in a device that performs signal processing using an input clock consisting of an "L" level region and an "H" level region, 110 is a voltage between the input clock voltage and the reference voltage Vref2. This is a second comparison unit that compares the input clock or the voltage of the negative polarity noise mixed in the "H" level region of the input clock and outputs a predetermined signal depending on whether the voltage of the input clock or the negative polarity noise mixed in the "H" level region of the input clock is higher or lower than the reference voltage Vref2.

310 inputs the output of the second comparator 110 and determines that the negative polarity noise voltage is equal to the reference voltage Vref2.
a second signal that outputs a signal indicating the detection of noise only when the noise is smaller than
This is the noise detection section.

[0010] The device is configured to detect negative polarity noise mixed into the “H” level region of the input clock.

[0011]

[Operation] In FIG. 1 showing the first invention, the first comparing section 100 compares the voltage of the input clock with a preset reference voltage Vref1. Then, a predetermined signal is output depending on whether the voltage of the input clock or the voltage of positive noise mixed in the "L" level region of the input clock is larger or smaller than the reference voltage Vref1.

Next, the output of the first comparator 100 is
input into the noise detection section 300 of. The first noise detection section 300 is composed of, for example, a mono multivibrator and an AND circuit, and by inputting the output of the first comparison section 100 to the mono multivibrator, it responds to the rising edge of the input signal from the mono multivibrator. outputs a pulse with a fixed time width.

By inverting the sign of the output of the first comparator 100 mentioned above and adding it to the AND circuit together with the output of the mono multivibrator and calculating the AND of the two, the "L" level of the input clock is output from the AND circuit. Only when the voltage of positive noise mixed into the region is higher than the reference voltage Vref, a signal indicating noise detection is output.

As a result, positive polarity noise mixed into the "L" level region of the input clock can be detected. Next, in FIG. 2 showing the second invention, the second comparing section 11
0, the voltage of the input clock is compared with a preset reference voltage Vref2. Then, a predetermined signal is output depending on whether the voltage of the input clock or the voltage of negative polarity noise mixed in the "H" level region of the input clock is larger or smaller than the reference voltage Vref2.

Next, the output of the second comparator 110 is
input to the noise detection section 310 of. The second noise detection section 320 is composed of, for example, a mono multivibrator and an AND circuit, and by inputting the output of the second comparison section 110 to the mono multivibrator, it responds to the rising edge of the input signal from the mono multivibrator. outputs a pulse with a fixed time width.

By inverting the sign of the output of the second comparator 110 mentioned above and adding it to the AND circuit together with the output of the mono-multivibrator and calculating the AND of the two, the "H" level of the input clock is output from the AND circuit. Only when the voltage of negative polarity noise mixed in the area is lower than the reference voltage Vref2, a signal indicating noise detection is output.

As a result, negative polarity noise mixed into the "H" level region of the input clock can be detected.

[0018]

Embodiment FIG. 3 is a block diagram showing the configuration of a positive noise detection section according to an embodiment of the first invention. FIG. 4 is a diagram for explaining the operation of the embodiment of the first invention.

FIG. 5 is a block diagram showing the configuration of the negative noise detection section according to the second embodiment of the invention. FIG. 6 is a diagram for explaining the operation of the embodiment of the second invention. FIG. 7 is a block diagram showing the configuration of a noise detection circuit according to the third embodiment.

FIG. 8 is a diagram for explaining the operation of the third embodiment. The same reference numerals indicate the same objects throughout the figures. The case of detecting positive polarity noise mixed into an input clock will be described using FIGS. 3 and 4. FIG.

In FIG. 3, for example, the potential comparator 1 shown in FIG.
A clock as shown in (2) is inputted, and the potential comparator 1 compares it with a preset reference voltage V1. (Reference voltage V1
is set to 0.5 V, for example. ) and when the input clock potential is higher than the reference voltage V1 or the reference voltage V1
When the potential of the input clock is lower than the reference voltage V1, it outputs an "H" level signal (constant value), and when the potential of the input clock is lower than the reference voltage V1, it outputs an "L" level signal (for example, 0V).

That is, as shown in (■) in FIG.
No noise is mixed in the input clock to (a)
In the region of and (c), as shown in ■ in Figure 4, "H"
” level pulses (a)' and (c)' are output from the potential comparator 1. In addition, positive polarity noise a is input to the input clock to the potential comparator 1.
In the region (d) where 1, a2, and a3 are mixed, positive polarity noise a1 whose potential is higher than the reference voltage V1,
For a2, instantaneous pulses a1' and a2' are output from the potential comparator 1, and in the part where positive polarity noise a1 and a2 are not present, the potential is lower than the reference voltage V1, so "L"
” Outputs a level signal.

[0023] Also, negative polarity noise b1, b2, b3
In the region (b) where the voltage is mixed, as shown in ■ in FIG. In a portion where negative polarity noise b1 does not exist, the potential is higher than the reference voltage V1, so an "H" level signal is output.

These outputs are branched and applied to one input terminal of a pulse generator 2 and a logical product circuit (hereinafter referred to as an AND circuit) 3 with its sign inverted. The pulse generator 2 is composed of, for example, a mono-multivibrator (not shown), and when the rising edge of the pulse is input from the potential comparator 1, the fixed values shown by (a)'' to (e)'' in ■ in Figure 4 are generated. Outputs a pulse of time length (T). (
Here, T is, for example, 20 nS, which is set shorter than the pulse length of one clock, 61 nS. ) In this case, since the instantaneous pulses a1', a2', b1' corresponding to the positive polarity noises a1, a2 and the negative polarity noise b1 also have rising edges, pulses with a fixed time length (T) are output.

This output is applied to the other input terminal of the AND circuit 3. Since the output of the potential comparator 1 mentioned above is applied to one input terminal of the AND circuit 3 with its sign inverted, the output of the potential comparator 1 is "L" from the AND circuit 3.
Further, it outputs a signal that is at the "H" level only when the output of the pulse generator 2 is at the "H" level, and is at the "L" level in other cases. As a result, the AND circuit 3 outputs positive polarity noises a1 and a2 as shown in (■) in FIG.
Outputs a pulse corresponding to . As a result, the reference voltage V
1 Positive polarity noise with a higher potential is reliably detected,
The AND circuit 3 outputs it as a noise detection pulse.

It should be noted that an OR circuit (hereinafter referred to as an OR circuit, not shown) may be used in place of the AND circuit 3 of the positive noise detection section shown in FIG. In this case, the output of the pulse generator 2 is inverted in its sign and is added to an OR circuit (not shown) together with the output of the potential comparator 1 to calculate the logical sum of the two. Then, by inverting the sign of the obtained logical sum result and outputting it from an OR circuit (not shown), a signal as shown in ■ in FIG. 4 is obtained.

Next, the case of detecting negative polarity noise mixed into the input clock will be explained using FIGS. 5 and 6. In FIG. 5, the potential comparator 4 has, for example,
A clock such as shown in FIG. (The reference voltage V2 is set to 0.5 V, for example.) When the potential of the input clock is higher than or equal to the reference voltage V2, an "H" level signal (constant value) is output, and the input clock When the potential is lower than the reference voltage V2, an "L" level signal (for example, 0V) is output.

That is, as shown in FIG.
No noise is mixed in the input clock to (a)
In the area of and (c), as shown in ■ in Figure 6, “H”
” level pulses (a)' and (c)' are output from the potential comparator 4. Also, negative polarity noise b is input to the input clock to the potential comparator 4.
In the region (b) where 1, b2, and b3 are mixed, negative polarity noise b1 whose potential is lower than the reference voltage V2,
For b2, instantaneous pulses b1' and b2' are output from the potential comparator 4, and in the part where negative polarity noise b1 and b2 are not present, the potential is higher than the reference voltage V2, so "H" is output.
” Outputs a level signal.

[0029] Also, positive polarity noise a1, a2, a3
In the region (d) where V2 is mixed, as shown in (■) in FIG. In the portion where the positive polarity noise a1 does not exist, the potential is lower than the reference voltage V2, so an "L" level signal is output.

These outputs are branched and applied to one input terminal of a pulse generator 5 and an AND circuit 6, which will be described later. The pulse generator 5 is composed of, for example, a mono-multivibrator (not shown), and when the falling edge of the pulse is input from the potential comparator 4, the signal shown in (a)'' in FIG.
(d) Output a pulse with a fixed time length (T) indicated by ''. (Here, T is 20 nS, for example, and is set shorter than the pulse length of one clock, 61 nS.) In this case, instantaneous pulses a1', b1' corresponding to positive polarity noise a1 and negative polarity noises b1, b2. , b2' also have a falling edge, so they output a pulse with a fixed time length (T).

This output is applied to the other input terminal of the AND circuit 6. Since the output of the potential comparator 4 mentioned above is added to one input terminal of the AND circuit 6, the output of the potential comparator 4 is "H" and the output of the pulse generator 5 is "H" from the AND circuit 6. ” level, outputs a signal that is “H” level only, and otherwise outputs “L” level. As a result, the AND circuit 6 outputs pulses corresponding to the negative polarity noises b1 and b2, as shown in (■) in FIG. As a result, negative noise having a potential lower than the reference voltage V2 is reliably detected and output from the AND circuit 6 as a noise detection pulse.

Next, the operation of the circuit for simultaneously and independently detecting positive noise and negative noise present in the input clock will be explained using FIGS. 7 and 8. In FIG. 8, the output of the positive noise detection section 7 for detecting positive polarity noise shown in FIG. 3 and the output of the negative noise detection section 8 for detecting negative polarity noise shown in FIG. 5 are added to the latch section 9. 9, the two are combined.

That is, since the positive noise detection section 7 has the circuit configuration shown in FIG. 3 as described above, and the negative noise detection section 8 has the circuit configuration shown in FIG. 5, the clock shown in ■ in FIG. When this signal is added to the positive noise detector 7 and the negative noise detector 8 shown in FIG. 7, the positive noise detector 7 outputs a signal as shown in ■ in FIG. ■■
A signal as shown in is output as a noise detection pulse. The outputs of the positive noise detection section 7 and the negative noise detection section 8 are applied to the latch section 9. The latch section 9 is composed of, for example, a flip-flop circuit (not shown), and outputs an "H" level signal (constant value) when a positive pulse is input from the positive noise detection section 7 or the negative noise detection section 8 even once. Output. In addition, the latch section 9 sends the clear signal to the clear terminal (CLR
) to return the output to "L" level (constant value).

As a result, by applying the outputs of the positive noise detecting section 7 and the negative noise detecting section 8 to the latch section 9, the latch section 9 outputs an "H level signal (
output a constant value). By inputting a clear signal as shown in Figure 8 to the clear terminal (CLR),
The latch section 9 returns its output to an "L" level signal (constant value) as shown in (2) in FIG.

As a result, if there is noise in the input clock, the output of the latch section 9 becomes an "H" level signal (constant value), so that the presence of this noise is notified to the outside. Further, by inputting a clear signal to the clear terminal (CLR) of the latch unit 9, this notification is canceled.

[0036]

As described above, according to the present invention, the presence of noise mixed in a clock can be detected without observing the waveform of the clock using an oscilloscope or the like.

Furthermore, since it is a small-scale circuit, it can be easily incorporated into a transmission device package, etc., and the cause of noise mixed into the clock can be determined in a short time.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the first invention;

[Fig. 2] is a diagram of the principle of the second invention;

FIG. 3 is a block diagram showing the configuration of the positive noise detection section of the embodiment of the first invention;

FIG. 4 is a diagram for explaining the operation of the embodiment of the first invention;

FIG. 5 is a block diagram showing the configuration of the negative noise detection section of the embodiment of the second invention;

FIG. 6 is a diagram for explaining the operation of the embodiment of the second invention;

FIG. 7 is a block diagram showing the configuration of the noise detection circuit of the third embodiment;

FIG. 8 is a diagram for explaining the operation of the third embodiment.

[Explanation of symbols]

100 is the first comparison section, 110 is a second comparison section; 300 is a first noise detection unit; 310 is a second noise detection unit shows.

Claims (2)

[Claims] 1. In a device that performs signal processing using an input clock consisting of an "L" level region and an "H" level region, the voltage of the input clock and a reference voltage (Vre
f1) and outputs a predetermined signal depending on whether the input clock or the voltage of positive polarity noise mixed in the "L" level region of the input clock is larger or smaller than the reference voltage (Vref1). inputs the outputs of the comparison section (100) and the first comparison section (100), and outputs a signal indicating detection of noise only when the voltage of the positive polarity noise is higher than the reference voltage (Vref1). 1. A clock monitoring system, comprising: a first noise detection unit (300) configured to detect positive polarity noise mixed into an "L" level region of the input clock. 2. In a device that performs signal processing using an input clock consisting of an "L" level region and an "H" level region, the voltage of the input clock and a reference voltage (Vre
f2) and outputs a predetermined signal depending on whether the input clock or the voltage of negative polarity noise mixed in the "H" level region of the input clock is higher or lower than the reference voltage (Vref2). inputs the outputs of the comparison section (110) and the second comparison section (110), and outputs a signal indicating detection of noise only when the voltage of the negative polarity noise is lower than the reference voltage (Vref2). A clock monitoring system characterized in that a second noise detection section (310) is provided to detect negative polarity noise mixed in the "H" level region of the input clock.