JPH04334007A - Ceramic capacitor - Google Patents

Abstract

PURPOSE:To obtain a ceramic capacitor which has a solder heat resistance and solder wettability and is excellent in various kinds of characteristics and high in reliability, because no crack is formed in its dielectric body even when the capacitor is subjected to a thermal or mechanical shock. CONSTITUTION:This ceramic capacitor is constituted of a ceramic base body 10 and an external electrode 11 containing a baked electrode layer 12 which is formed on the external surface of the body 10 and is composed of a metal and inorganic binder. An alloy layer 13 which is composed principally of Pb and contains at least one of Sn, Ag, and In, Ni-plated layer 14, and Sn- or Sn/Pb-plated layer 15 are successively formed in this order on the surface of the baked electrode layer. The alloy layer acts as a stress buffer layer.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic capacitor having an external electrode having a plurality of layers formed on the surface of a baked electrode layer.

0002

[Prior Art] Among ceramic capacitors, multilayer ceramic capacitors form a ceramic body in which a plurality of internal electrodes face each other by alternately laminating internal electrodes and ceramic dielectrics, and the outer surface of this ceramic body by forming an external electrode electrically connected to the internal electrode. This external electrode has a baked electrode layer formed by applying and baking a paste containing metal and an inorganic binder so as to cover the internal electrode taken out on the outer surface of the ceramic body. If this capacitor is a chip-type multilayer ceramic capacitor for surface mounting, its external electrodes are soldered directly to the circuit board when it is mounted on a circuit board. A ceramic capacitor having a plating layer formed of at least one of Ni, Cu, Sn, and Sn/Pb has been proposed (Japanese Patent Laid-Open No. 2-150007). The above capacitor has a plating layer formed by electrolytic or electroless plating, which increases the heat resistance of the baked electrode layer, eliminates electrode erosion by solder, and improves oxidation prevention of metal components and solder wettability. It has the advantage of making soldering easier. Usually, as shown in FIG. 3, a first Ni plating layer 4 is formed on the surface of the baked electrode layer 2, and a second Sn or Sn/Pb plating layer 5 is formed thereon. The first layer of Ni film prevents the electrode from being eaten away by solder.
The second Sn or Sn/Pb plating film ensures solder wettability.

0003

[Problems to be Solved by the Invention] However, the electrolytically deposited Ni plating film generally generates tensile stress during deposition, which affects the characteristics of the capacitor, particularly the thermal shock resistance. This effect increases as the capacitor becomes larger,
For example, if it is immersed in a solder bath of 300° C. or higher and pulled up from room temperature without preheating, cracks 7 are likely to occur in the dielectric portion of the ceramic body 6 inside the external electrode 1, as shown in FIG. When cracks occur, the moisture resistance deteriorates, and moisture infiltrates through the cracks, resulting in a deterioration of the insulation resistance of the capacitor. Further, as shown in FIG. 4, this capacitor is mounted as a chip type ceramic capacitor on the surface of the circuit board 8 by soldering 9, for example, -5
If a temperature cycle test is performed in which the temperature is raised from around 0°C to around +150°C via room temperature and then lowered, a crack 7 will grow from the high thermal stress and the external electrode 1 portion will break. Alternatively, there was a problem that the insulation resistance of the capacitor deteriorated.

[0004] In order to solve these problems, the plating bath composition and plating conditions during Ni plating have been studied in detail, but even if these methods are used, it is not always sufficient for large capacitors, and it is difficult to There was still room for improvement in terms of reliability in environments where rapid heating and cooling occur. In addition, a Cu plating layer and a Sn plating layer are added to the surface of the baked electrode layer.
Alternatively, if the two Sn/Pb plating layers are formed in this order, the above problems caused by forming the Ni plating layer will be resolved, but since Cu has poorer heat resistance than Ni, the baked electrode layer The disadvantage was that the heat resistance of the electrodes could not be sufficiently improved and the electrodes would be eaten away by the solder. Furthermore, if the board is bent or subjected to vibration after mounting,
Since the Ni plating layer or the Cu plating layer has insufficient stress relaxation due to deflection, cracks may similarly occur or grow, resulting in a reduction in capacity or poor insulation.

[0005] An object of the present invention is to reduce the stress when the external electrode is subjected to thermal shock or mechanical shock, thereby preventing cracks from occurring in the dielectric portion covered by the external electrode. Our goal is to provide ceramic capacitors with high performance.

[0006]

[Means for Solving the Problems] The present inventor has solved the problems of conventional capacitors in which two plating layers are provided on the surface of a baked electrode layer by providing a stress buffer layer between these plating layers and the baked electrode layer. This problem was solved and the present invention was achieved. In order to achieve the above object, the present invention as shown in FIG.
This is an improvement of a ceramic capacitor including a ceramic body 10 and an external electrode 11 formed on the outer surface of the ceramic body 10 and including a baked electrode layer 12 made of metal and an inorganic bonding material. Its characteristic structure is that on the surface of the baked electrode layer 12, there is an alloy layer 13 containing Pb as a main component and at least one of Sn, Ag, and In, a Ni plating layer 14, and a Sn plating layer 14.
Alternatively, the Sn/Pb plating layer 15 is formed in this order.

The present invention will be explained in detail below. The ceramic capacitor of the present invention includes not only a multilayer capacitor but also a single layer capacitor. A multilayer capacitor forms a ceramic body in which a plurality of internal electrodes face each other by alternately laminating internal electrodes and ceramic dielectrics, and an external electrode is provided on the outer surface of this ceramic body to electrically connect to the internal electrodes. It is made by forming. For this ceramic dielectric, lead perovskite-based, barium titanate-based dielectrics, etc. are used, and the internal electrodes are Pd, Pt, Ag/P.
A noble metal such as d, or a base metal such as Ni, Fe, Co, or Cu is used.

[0008] The external electrode is a baked electrode layer made by applying a paste made by adding an inorganic binder to noble metal powder such as Ag, Pd, Pt or base metal powder such as Ni, Al, Cu, etc. to the outer surface of the ceramic body and baking it. Equipped with On the surface of this electrode layer, a first layer which is an inner layer, an alloy layer mainly composed of Pb,
The second Ni plating layer is the intermediate layer, and the third Ni plating layer is the outer layer.
A Sn or Sn/Pb plating layer is formed. The second and third plating layers are similar to conventional capacitors.
They are provided to prevent the electrode from being eaten away by solder and to ensure solder wettability. A distinctive feature of the present invention lies in the first (inner) alloy layer provided between the baked electrode layer and the second Ni plating layer. This alloy has Pb as its main component and also contains at least one of Sn, Ag, and In. This alloy is Ni or Ag, Pd, P for the baked electrode layer.
It is more flexible than metals such as T, easily deforms plastically when subjected to stress even at room temperature, and has a high melting point that does not melt during soldering.

Generally, depending on the alloy system, at a certain temperature, the entire alloy may not melt at the same time, but a portion may melt, resulting in a coexistence of solid and liquid. In this case, when the heating temperature is further increased, the entire alloy melts. . Here, the temperature at which a liquid phase is first generated is called the solidus temperature, and the temperature at which the entire material melts is called the liquidus temperature. Also, an alloy composition in which the solidus temperature and the liquidus temperature are the same is called a eutectic composition, and in this case, when heated, the entire alloy melts at the same time. The alloy constituting the alloy layer of the present invention may or may not have a eutectic composition. If the alloy does not have a eutectic composition, the solidus temperature is preferably 280° C. or higher so that the alloy does not melt during soldering.

[0010] Characteristics depending on the composition of the alloy will be described below. (a) Pb/Sn alloy system In this alloy system, Pb90wt%/Sn10wt%~P
A Pb-rich composition of 100% by weight b/0% by weight Sn is suitable for the purpose of the present invention. This alloy system has a solidus temperature above 280°C and is flexible at low temperatures. Ag may be added in an amount of about 1 to 5% by weight in order to obtain a eutectic composition, but this is not essential. Pb90wt%/S outside the above range
A composition of 10% by weight of n to 0% by weight of Pb/100% by weight of Sn has a solidus temperature of 183°C to 270°C, which is not suitable for the purpose of the present invention. (b) Sn/Ag alloy system In this alloy system that does not contain Pb, 100% by weight of Sn/A
The solidus temperature is 221° C. in the composition range of 0% by weight of g to 30% by weight of Sn/70% by weight of Ag, which is not compatible with the purpose of the present invention. In addition, in a composition with a large amount of Ag, Ag3 is extremely fragile.
This composition is unsuitable because it tends to generate intermetallic compounds with a Sn composition and has an effect that is opposite to the purpose of stress relaxation. (c) Pb/Ag alloy system This alloy system, which does not contain Sn, has a solidus temperature of 304° C. over almost the entire region, and is particularly suitable for compositions containing a large amount of Pb, since they also have flexibility. (d) Pb/In alloy system In this alloy system, Pb100wt%/In0wt%~P
A composition containing a large amount of Pb (90% by weight of b/10% by weight of In) has a solidus temperature of 300° C. or higher. This alloy system is also very flexible, which makes it suitable.

From the above (a) to (d), a composition suitable for the purpose of the present invention contains Pb as a main component and a small amount of Sn.
, Ag, In. It is preferable to add a small amount of Sn, since this greatly improves the wettability of the alloy with respect to Ag, which is the main component of the baked electrode layer. In terms of cost, Pb is the cheapest, followed by Sn, In, and Ag, which are expensive in that order. From the above, practical alloys include 93.5% by weight Pb/5% by weight Sn/1.5% by weight Ag (eutectic composition, melting temperature 296°C), 92.5% by weight Pb/5% by weight In/
A composition containing 2.5% by weight of Ag (solidus temperature 304° C.) is useful.

The alloy layer of the present invention is formed on the surface of the baked electrode layer with a thickness of 3 to 50 μm, and Ni is formed on this alloy layer.
A plating layer is formed with a thickness of 1 to 5 μm, and this Ni
3 to 30 Sn or Sn/Pb plating layers on the plating layer
It is formed with a thickness of μm. The method for forming the alloy layer is as follows:
As with the other two plating layers, electroless plating and electrolytic plating may be performed by barrel plating using a known plating bath, or a dipping method in which the outer surface of the ceramic body is immersed in a molten alloy. If the capacitor is small, plating is suitable. Furthermore, a dipping method is suitable for increasing the thickness of the alloy layer.

[0013]

[Operation] By forming an alloy layer having the above composition on the surface of the baked electrode layer and providing a Ni plating layer thereon, stress caused by electrolytic deposition of Ni is alleviated by plastic deformation of the alloy layer. Furthermore, if an alloy layer having the above composition is formed to a thickness within the above range,
The stress caused by deflection after being mounted on a circuit board is also alleviated by the plastic deformation of this alloy layer. Furthermore, from about -50℃ to 150℃
Stress caused by rapid temperature changes on the order of degrees Celsius can also be alleviated by providing an alloy layer having the above composition. Also, during soldering, the Ni plating layer prevents the baked electrode layer from being eaten away.
The Sn or Sn/Pb plating layer enhances the solder wettability of the external electrode and prevents oxidation of the alloy and Ni.

[0014]

As described above, according to the present invention, the surface of the baked electrode layer contains Pb as the main component and Sn, Ag, In.
By forming an alloy layer containing at least one type of , a Ni plating layer, and a Sn or Sn/Pb plating layer in this order, the capacitor can resist thermal shock or mechanical shock while having solder heat resistance and solder wettability. No cracks occur in the dielectric material even when the capacitor is subjected to a lot of heat, and as a result, a highly reliable ceramic capacitor with excellent various properties can be obtained. Furthermore, since the present invention achieves its purpose by devising the structure and composition of the plating film, conventional capacitor materials, baked electrode materials, and manufacturing equipment can be used as they are. Therefore, by implementing the present invention, no new problems occur, and a high-performance capacitor can be obtained at low cost by only slightly changing the manufacturing conditions.

[0015]

EXAMPLES Next, examples of the present invention will be described in detail with reference to the drawings together with comparative examples. <Example 1> In this example, as a ceramic capacitor,
JI with rated voltage 500V and capacitance 2.2±0.1nF
A chip-type multilayer ceramic capacitor (product number C30R2H222K, manufactured by Mitsubishi Materials Corporation) having SR characteristics and having a length of 3.2 mm, a width of 1.6 mm, and a thickness of 1.0 mm was used. As shown in FIG. 1, the multilayer ceramic chip capacitor 20 includes a lead perovskite ceramic body 1.
0, and an external electrode 11 is provided on the outer surface of this ceramic body 10. The ceramic body 10 has an internal electrode 1 made of Ag/Pd.
9 is formed, a plurality of ceramic dielectrics 16 are laminated,
It was formed by firing this. The external electrode 11 is
It is composed of a baked electrode layer 12, an alloy layer 13 whose main component is Pb, a Ni plating layer 14, and a Sn/Pb plating layer 15. The baked electrode layer 12 is made of an Ag paste containing an inorganic bonding material having resistance to plating liquids and attached to the ceramic body 10.
It was coated on the outer surface of the film, dried at 180°C for 15 minutes, and then baked at a maximum temperature of 750°C. When the Ag paste is 100% by weight, Ag powder is 75% by weight,
This Ag powder contains 8% by weight of an inorganic binder.

In this example, the alloy layer is a Pb/Sn alloy layer, and this layer was also formed by a plating method. The plating conditions for the three layers 13 to 15 will be described below. ■ Pb/Sn plating (inner layer) The bath composition is 15g/L of lead (Pb) and 4g/L of tin (Sn).
/L, the pH of the bath was 4.5, and the temperature of the bath was 25°C. Electrode layer 12 is formed by electrolytic barrel plating using this bath.
An alloy layer 13 of 90% by weight Pb/10% by weight Sn and having a thickness of 30±5 μm was formed on the surface. ■ Ni plating (intermediate layer) The bath composition is nickel sulfamate Ni (NH2SO
3) 2.4H2O was 120 g/L, the pH of the bath was 4.0, and the temperature of the bath was 50°C. Using this bath, the surface of the alloy layer 13 was coated with a thickness of 1.5±0.3μ by electrolytic barrel plating.
A Ni plating layer 14 having a thickness of m was formed. ■ Sn/Pb plating (outer layer) The bath composition is 15g/L of tin (Sn) and 6g/L of lead (Pb).
/L, the pH of the bath was 4.5, and the temperature of the bath was 25°C. Using this bath, a Sn/Pb plating layer 1 with a thickness of 15±2 μm was formed on the surface of the Ni plating layer 14 by electrolytic barrel plating.
5 was formed.

<Example 2> As a ceramic capacitor, J with a rated voltage of 500V and a capacitance of 6.8±0.2nF
Length 3.2mm, width 2.5mm, with IS-R characteristics.
Chip-type multilayer ceramic capacitor with a thickness of 1.2 mm (
Product number C40R2H682K, manufactured by Mitsubishi Materials Corporation)
was used. The external electrode 11 was formed in the same manner as in Example 1. <Example 3> As a ceramic capacitor, the rated voltage is 5
Length 4.5mm, width 3.3mm, thickness 1.4mm with JIS-R characteristics of capacitance 47.5±0.3nF at 00V
mm chip type multilayer ceramic capacitor (product number C70
R2H473K (manufactured by Mitsubishi Materials Co., Ltd.) was used. The external electrode 11 was formed in the same manner as in Example 1.

Comparative Example 1 A 1.5±0.5 μm thick Ni layer and a 15±2 μm thick Ni layer were formed on the surface of the baked electrode layer in the same manner as in Example 1 except that the Pb/Sn plating layer (■) was not formed. A plating layer having a two-layer structure consisting of Sn/Pb layers was formed. <Comparative Example 2> The surface of the baked electrode layer was coated with 1.5±
A plating layer having a two-layer structure consisting of a 0.5 μm thick Ni layer and a 15±2 μm thick Sn/Pb layer was formed. <Comparative Example 3> The surface of the baked electrode layer was coated with 1.5±
A plating layer having a two-layer structure consisting of a 0.5 μm thick Ni layer and a 15±2 μm thick Sn/Pb layer was formed.

<Test Method> The chip-type multilayer ceramic capacitors produced in Examples 1 to 3 and Comparative Examples 1 to 3 above were subjected to a thermal shock test, a temperature cycle test, and a limit deflection test. The number n in parentheses is the number of samples tested. (a) Thermal shock test (n=100) As shown in FIG. 2, each sample chip capacitor 20 placed at room temperature was grabbed with tweezers 21 so that the narrow side of the capacitor was the top and bottom sides. Heat this to 250℃, 270℃, 300℃, 350℃, 400℃ without preheating.
After being immersed in a eutectic solder bath of 63 wt % Sn/37 wt % Pb at a temperature of 0.degree. C. for 3 seconds, it was pulled out and allowed to cool in the air. The appearance of this sample was examined using an optical microscope to determine the presence or absence of cracks. In addition, the insulation resistance of samples without cracks was examined, and the number of samples with cracks and the number of samples with deteriorated insulation resistance were totaled to determine the number of defects.

(b) Temperature cycle test (n=30) A sample chip capacitor was placed on an alumina substrate with a thickness of 0.635 mm using solder paste SPT- manufactured by Senju Metal Co., Ltd.
Reflow soldering was performed at a temperature of 230°C using 55-2062. Using a vapor phase temperature shock tester, the soldered sample was maintained at -55℃ for 30 minutes, then the temperature was increased and maintained at room temperature for 3 minutes, and the temperature was further increased and maintained at 125℃ for 30 minutes. , 25, 50, 100, 150, and 200 cycle tests were conducted in which the temperature was lowered in the opposite direction with the same maintenance time. The number of defects was counted in the same manner as the thermal shock test in (a) above. (c) Limit deflection test (n=5) After a sample capacitor was mounted on a glass epoxy substrate with a thickness of 1.6 mm and a width of 40 mm by reflow soldering, this substrate was placed on a support stand with a span of 90 mm. Using a strength testing machine, apply a load of 10mm to the center of the span of the board.
The amount of deflection was measured at a rate of 1/min, and the critical amount of deflection when the capacitance of the capacitor decreased by 10% or more. (a) to (c) above
) results are shown in Table 1. In the table, the values for the thermal shock test and temperature cycle test indicate the number of defective pieces.

[0021]

[Table 1]

<Test Results and Evaluation> From Table 1, in the thermal shock test, cracks occurred, capacity decreased, or There was a defective product with deteriorated insulation resistance. On the other hand, in Examples 1 and 2, there were no such defective products even at a soldering temperature of 400°C. Further, in Comparative Example 3, defective products began to occur at a soldering temperature of 270°C, whereas in Example 3, defective products began to occur when the soldering temperature exceeded 350°C. In the temperature cycle test,
In Comparative Examples 1 to 3, defective products were generated after 100 cycles or more, whereas in Examples 1 to 3, there were no defective products even after 200 cycles. In the limit deflection test, the limit deflections were all larger in Examples 1 to 3 than in Comparative Examples 1 to 3. This revealed that the stress buffering effect of the alloy layer was remarkable.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a ceramic capacitor according to an embodiment of the present invention.

FIG. 2 is a perspective view showing how the sample is handled when conducting the thermal shock test.

FIG. 3 is a cross-sectional view showing the occurrence of cracks due to thermal shock in a conventional ceramic capacitor.

FIG. 4 is a cross-sectional view showing a situation in which cracks have further grown after the capacitor shown in FIG. 3 is soldered to a board. 10 Ceramic body 11 External electrode 12 Baked electrode layer 13 Alloy layer 14 Ni plating layer 15 Sn/Pb plating layer 16 Ceramic dielectric 19 Internal electrode 20 Ceramic capacitor

Claims (4)

[Claims] 1. A ceramic element comprising: a ceramic body (10); and an external electrode (11) including a baked electrode layer (12) formed on the outer surface of the ceramic body (10) and made of metal and an inorganic bonding material. In this ceramic capacitor, the surface of the baked electrode layer (12) contains Pb as a main component and Sn as a main component.
, Ag, In and an alloy layer (13) containing at least one of N
i plating layer (14) and Sn or Sn/Pb plating layer (1
5) is formed in this order. [Claim 2] The thickness of the alloy layer (13) is 3 to 50 μm.
The thickness of the Ni plating layer (14) is in the range of 1 to 5 μm.
Sn or Sn/Pb plating layer (15)
The ceramic capacitor according to claim 1, wherein the thickness of the ceramic capacitor is in the range of 3 to 30 μm. 3. The ceramic capacitor according to claim 1, wherein the alloy layer (13) is formed by a plating method. 4. The ceramic capacitor according to claim 1, wherein the alloy layer (13) is formed by a dipping method.