JPH04326186A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the area of a chip by reducing the increase of wiring accompanied with the increase of display segments and to reduce the control of an arrangement in the inside of a microcomputer. CONSTITUTION:Display data read in a first shift register A121 are transferred to a second shift register B123 as a serial data signal 122 by one bit unit, synchronously with a corrected shift clock signal 128 prepared by a shift clock preparing circuit 125, and corrected by a shift correcting circuit 126.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a microcomputer with a built-in display controller, and particularly relates to a method for transferring display data from near a display memory to near a terminal for outputting display segment signals. Note that in this specification, the display controller includes a display driver.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing the essential parts of an example of a microcomputer incorporating a conventional fluorescent display tube controller, and shows the fluorescent display tube controller section.

The microcomputer 500 of this conventional example is a microcomputer that controls a fluorescent display tube by dynamic driving. Display memory 502 stores display data. Display digit signal output terminal 501 (
501-1 to 501-n) output a plurality of display digit signals that become active sequentially. Also, the contents of the display memory 502 are read out for each display digit signal, and multiple display segment/digit signal output terminals 503 (503-1 to 503-
m).

[0004] The display memory 502 includes an address selector 5
The address is selected by the output from 04, and the data bus 5
It is possible to read from or write to 05. Further, reading can be performed on the display data latch 506. Reading or writing between display memory 502 and data bus 505 is performed using memory read signal 517 or memory write signal 507, and reading from display memory 502 to display data latch 506 is performed using display data read signal 508.

Address selector 504 includes means for time-divisionally switching the memory address between an address from address bus 509 and an address output from address generation circuit 510. When reading or writing between display memory 502 and data bus 505, an address from address bus 509 is selected. Furthermore, when reading data from the display memory 502 to the display data latch 506, an address based on the output from the address generation circuit 510 is selected.

The counter 511 performs a counting operation based on a count clock signal 512, and outputs the overflow of the counter as a display data read signal 508 to a timing counter 515. The display data read signal 508 is a signal that becomes "H" level at the end of each digit signal output. The timing counter 515 is the counter 51
The display timing decoder 5 is a counter that performs counting operation based on the display data read signal 508 outputted by the display timing decoder 5.
16 and outputs the count value to the address generation circuit 510. Further, the timing counter 515 receives the coincidence signal 52.
Inputting 0 clears the count value to zero.

The number of digits setting circuit 518 stores the number of display digits, compares the count value of the timing counter 515 with the set number of display digits, and outputs a match signal 520 to the timing counter 515 if they match. Number of digits setting circuit 5
18, the number of display digits is written in advance via the data bus 505.

The display timing decoder 516 decodes the count value output by the timing counter 515, generates a display digit signal, and outputs the display digit signal to the plurality of display digit signal output terminals 50.
The high voltage buffer 5 sequentially sends “H” active signals from 1 to
14. Further, when the number of display digits set in the number of digits setting circuit 518 is greater than the number of display digit signal output terminals, the overflow digit signal output signal is output from the output of the display timing decoder 516 through an OR circuit (OR) 519, The signal is output from the display segment/digit signal output terminal 503 via the high voltage buffer 513.

Address generation circuit 510 is a circuit that outputs an address that is updated as the timing counter 515 counts up, and generates an address for display memory 502 for reading display data corresponding to each display digit signal output. The display data latch 506 has a two-stage master-slave configuration, and takes in multiple bits of data in parallel from the display memory 502 when the display data read signal 508 is at the "H" level. When the level is set to "L", the captured data is transferred from the master side to the slave side, and the slave side outputs multiple display segment/digit signal output terminals 5.
03 through the high voltage buffer 513. The maximum number of segments of display data depends on the number of display digits, and the display segment/digit signal output terminal 503
Of these, the number of terminals not used for display digit signal output can be used for display segment signal output.

Next, display output timing will be explained using FIG. 7. In FIG. 7, 501-1, 501-
2 and 501-3 are outputs of the display digit signal output terminal 501. The display digit signal output terminal 501 outputs an "H" active signal in the order of the output terminals 501-1, 501-2, and 501-3 while the timing counter 515 counts up by the number of display digits. In addition, in FIG. 7, the falling edge of the output terminal 501-1 and the falling edge of the output terminal 501-1
2, and the fall of the output terminal 501-2 and the rise of the output terminal 501-3 are at the same timing, but in reality there is a time gap to prevent leakage of light from the fluorescent display tube.

Address generation circuit 510 generates an address in which display data corresponding to the next digit of the active display digit signal is stored. Therefore, when the output terminal 501-2 is active, the address of the display memory 502 storing the display data that must be output when the output terminal 501-3 is active is generated. Reading to the display data latch 506 is executed when the display data read signal 508 output at the end of each display digit signal is at "H" level. When the display data read signal 508 is at the "H" level, display data is fetched from the display memory 502 to the master side of the display data latch 506, and when the display data read signal 508 falls to the "L" level, the display data is fetched from the master side of the display data latch. The display data is transferred from the slave side to the slave side, and is outputted from the display segment/digit signal output terminal 503 via the OR circuit 519 and the high voltage buffer 513.

In this conventional example, when accessing the display memory 502, reading or writing to the data bus 505 and reading to the display data latch 506 are performed in a time-sharing manner. Some examples use dual port RAM.

As described above, the microcomputer 500 incorporating the conventional fluorescent display tube controller transfers display data from the display memory 502 to the display data latch 506 by parallel transfer. Therefore, the wiring from the display memory 502 to the display data latch 506 must be provided for the number of display segment outputs, and as the number of display segments increases, the number of wiring increases, and as a result, the chip area of the microcomputer 500 increases. In addition, in the wiring inside the microcomputer,
There is a restriction that the display memory 502 and display segment/digit signal output terminal 503 must be located close to each other.

As another conventional example, an OR circuit 519
The logical sum input is 3 inputs, and in addition to the display timing decoder output and display data latch output, the general-purpose port latch output is input, and when the number of display digits and display segments is small, the remaining display segments and digit signals are also used. Output terminal 50
3 can be used as a general-purpose port output terminal, but in this case, there is a general-purpose port output terminal between the terminals that output display digit signals and display segment signals that are connected to the same fluorescent display tube. It becomes difficult to route the wiring when it is assembled.

As explained above, in this conventional example, the explanation was given using a microcomputer with a built-in fluorescent display tube controller as an example, but the control of a microcomputer with a built-in LCD (liquid crystal display element) controller can also be performed from the display memory. Data transfer to the output terminal is performed in the same manner as in this conventional example. However, in order to convert the level of the external output signal, an LCD drive voltage controller is added to this conventional example. Further, the configuration is such that the high voltage buffer 513 is replaced with a segment driver controlled by the LCD drive voltage controller, and the high voltage buffer 514 is replaced with a common driver controlled by the LCD drive voltage controller.

[0016]

As described above, in a conventional microcomputer with a built-in display controller, data transfer of display data from the display memory to the display data latch is performed in parallel.

However, in such a data transfer method,
Wiring from the display memory to the display data latch must be done for the number of display segment outputs, and as the number of display segments increases, the number of wires increases, resulting in a disadvantage that the chip area of the microcomputer increases. Another drawback is that the display memory and display segment/digit signal output terminal must be located close to each other in the wiring inside the microcomputer.

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby reducing the increase in the number of wires due to an increase in display segments, reducing the chip area, and reducing restrictions on placement inside a microcomputer. The purpose of the present invention is to provide a microcomputer with a built-in controller.

[0019]

[Means for Solving the Problems] The present invention provides a display memory that stores display data, a digit number setting circuit that can specify the number of display digits, a display timing decoder that outputs a display digit signal, and a display memory that outputs a display digit signal. The display controller includes a display data latch that latches and outputs read display data, and a plurality of display segment/digit signal output terminals that output the outputs of the display timing decoder and the display data latch to the outside. In the microcomputer, there is provided a multi-bit first shift register for reading and storing display data in the display memory and serially outputting the display data, and a display data latch for storing the display data output from the first shift register. a second multi-bit shift register that outputs the second shift register in parallel; a shift clock generation circuit that generates a shift clock signal for shifting the first and second shift registers; and a shift clock generation circuit that generates the generated shift clock signal. and a shift correction circuit that controls the digit number setting circuit according to the value of the digit number setting circuit.

Further, in the present invention, it is preferable that the display controller is a fluorescent display tube controller.

Further, in the present invention, it is preferable that the display controller is an LCD controller.

[0022]

[Operation] According to the shift clock signal generated by the shift clock generation circuit and controlled by the shift correction circuit according to the value of the number-of-digits setting circuit, the first shift register reads display data from the display memory and stores it. The display data is transferred in units as a serial data signal to the second shift register, stored in the second shift register, and the stored display data is output in parallel to the display data latch. As a result, display data is output to the display segment/digit signal output terminal.

Therefore, the only wiring required for display data transfer is one serial data signal line from the first shift register to the second register, and two shift clock signal lines, which reduces the number of display segments. It is possible to reduce the increase in the number of wires due to the increase in the number of wires, reduce the chip area, and
It becomes possible to reduce restrictions on placement within the microcomputer.

[0024]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a first embodiment of the present invention, which shows a fluorescent display tube controller section and corresponds to the conventional example shown in FIG.

The first embodiment includes a display memory 502 that stores display data, a digit number setting circuit 518 that can specify the number of display digits, a display timing decoder 516 that outputs a display digit signal, and a display memory 502. A display data latch 506 that latches and outputs read display data, a display timing decoder 516, and a display data latch 5.
In a microcomputer 500a equipped with a display controller including a plurality of display segment/digit signal output terminals 503 (503-1 to 503-m) that output the output of 06 to the outside, the present invention is characterized by: A multi-bit first shift register A12 that reads out display data in the display memory 502, stores it, and outputs it serially.
1, a multi-bit second shift register B123 that stores the display data serially output as the serial data signal 122 from the shift register A121 and outputs it in parallel to the display data latch 506, and a clock signal 124 and Shift clock mask signal 13
A shift clock generation circuit 125 generates a shift clock signal 127 for inputting 0 and shifting the shift registers A121 and B123, and converts the generated shift clock signal 127 into a digit number data signal from a digit number setting circuit 518. 129 and outputs a corrected shift clock signal 128.

[0027] In FIG. 1, 501 (501-1
~501-n) are display digit signal output terminals, 504 is an address selector, 505 is a data bus, 507 is a memory write signal, 508 is a display data read signal, 509 is an address bus, 510 is an address generation circuit, 511 is a counter, 512 are count clock signals, 513 and 514
is a high voltage buffer, 515 is a timing counter, 51
7 is a memory read signal, 519 is an OR circuit and 52
0 is a match signal.

Next, the operation of the first embodiment will be explained.

In the first embodiment, in order to simplify the explanation,
The display data width is 5 bits, the number of display digits is 11, and the display digit signal output terminals 501 are 8 (501-1 to 501-8).
), and display segment/digit signal output terminal 5
03 is also assumed to be eight (from 503-1 to 503-8).

The shift clock generation circuit 125 generates a shift clock signal 127 from the clock signal 124, and also masks a predetermined period of the clock signal 124 to "L" level using a shift clock mask signal 130 output from the counter 511. do. Display data is read from the display memory 502 while the shift clock signal 127 is masked and is at the "L" level.

The number of display digits set in advance in the number of digits setting circuit 518 is sent to the shift correction circuit 126 as a number of digits data signal 129. The shift correction circuit 126 determines the actual number of shift clocks from the digit number data signal 129. The actual number of shift clocks is {(number of display segment/digit signal output terminals 503 + display digit signal output terminals 501
number) - number of displayed digits}. In this case, the actual number of shift clocks is {(8+8)-11}=5. The shift correction circuit 126 further masks the reference shift clock signal 127, which is the output of the shift clock generation circuit 125, to generate a corrected shift clock signal 128, and outputs it to the shift register A121 and shift register B123.

The number of display digits is previously set in the digit number setting circuit 518 by a command via the data bus 505. In this case, "11" is set. As mentioned above, this value is sent to the shift correction circuit 1 as the digit number data signal 129.
26. Further, the number of digits setting circuit 518 internally compares the set number of digits with the value of the timing counter 515, and when the set value and the value of the timing counter 515 match, a match signal 5 is sent to the timing counter 515.
Outputs 20.

The 5-bit wide display data read from the display memory 502 and stored in the shift register A 121 is sent to the shift register B 123 as a serial data signal 122 by five corrected shift clock signals 128. Then, the 5-bit width display data outputted from the shift register B 123 to the display data latch 506 by the display data read signal 508 is transmitted to the output terminal of the display segment/digit signal output terminal 503 via the OR circuit 519 and the high voltage buffer 513. 503-4 to 503-
Output from 8.

Furthermore, the shift register B123 is cleared to "00" at the fall of the display data read signal 508 in preparation for the next data transfer. On the other hand, the timing counter 515 counts from the first digit, and when it counts up to the number of digits set in the number of digits setting circuit 518, that is, "11", the counter 511 is returned to the initial value by a match signal 520 from the number of digits setting circuit 518. , starts counting again from the first digit.

The display timing decoder 516 outputs a display digit signal from the display digit signal output terminal 501 via the high voltage buffer 514 in accordance with the output of the timing counter 515. In this case, the display digit signal is output terminal 501-
Display digit signals are output in the order of 1 → 501-2 → 501-3, and the display digit signal for the 9th digit is sent to the display timing decoder 5.
16 to the display segment/digit signal output terminal 503-1 via the OR circuit 519 and the high voltage buffer 513.
is output from. Display digit signals for the 10th and 11th digits are similarly output from output terminals 503-2 and 503-3.

Next, the display output timing of the first embodiment will be explained with reference to FIG. In FIG. 2, output terminals 501-1, 501-2, and 501-3 are outputs of the display digit signal output terminal 501. The display digit signal output terminal 501 is connected to the output terminal 501-1→5 while the timing counter 515 counts up by the number of display digits.
An "H" active signal is output in the order of 01-2→501-3.

The address of the display memory 502 generated by the address generation circuit 510 is updated as the timing counter 515 counts up. As shown in the conventional example, the display memory 502 stores display data corresponding to the next digit of the active digit signal output.
generate an address for. Therefore, when the output terminal 501-2 is active, the address of the display memory 502 storing the display data that must be output when the output terminal 501-3 is active is generated.

Reading of display data to shift register A121 is performed when display data read signal 508 is at "H" level. Shift clock mask signal 130
The shift clock signal 127 whose clock has been masked for a predetermined period is further masked by a shift correction circuit, and is sent to the shift register A12 as a corrected shift clock signal 128.
1 and shift register B123, the contents of shift register A121 are transferred to shift register B123 as serial data signal 122 in synchronization with the rising edge of corrected shift clock signal 128, and the fifth falling edge of corrected shift clock signal 128 to end the transfer.

Reading of display data from the shift register B 123 to the display data latch 506 is executed when the display data read signal 508 is at "H" level, and at the same time, the display segment/digit signal is output via the high voltage buffer 513. The contents are output from the terminal 503.

In order to make the operation easier to understand, FIG.
The display data part and the display digit part of the first embodiment are extracted. In FIG. 3, the bit positions correspond to each other in the vertical direction, and data is sent from the top to the bottom.

The number of digits to be displayed is preset by the number of digits setting circuit 518, and the number of digits to be displayed by the display timing decoder 516 is also determined by this. This also uniquely determines the number of clocks of the corrected shift clock signal 128 output from the shift correction circuit 126. The display data is serially transferred to the shift register B123, which is cleared to "00" at the falling edge of the display data read signal 508 (in FIG. 3, the display data is shifted from the left side of the shift register B123), and the transferred display data is The data is stored in display data latch 506. As a result, the OR circuit 519 outputs the display data latch 506 and the display timing decoder 5.
The logical sum of the 16 outputs is taken, and among the bits corresponding to the display segment/digit signal output terminal 503, the bits that are not designated as display digit signal output are used as display data output terminals.

FIG. 4 is a block diagram showing the essential parts of a second embodiment of the present invention, showing a fluorescent display tube controller section. The microcomputer 500b of the second embodiment is the same as the first embodiment shown in FIG. 1 to which a general-purpose port latch 400 is added. In the first embodiment, the number of clocks of the corrected shift clock signal 128 is uniquely determined according to the set number of display digits, so when the number of display segments is small,
Data other than the display data to be displayed at that timing in the display memory 502 is also output from the display segment/digit signal output terminal 503. By using this to write data to be output into the display memory 502, it can be output at the timing when the digit signal corresponding to that address becomes active. However, in this case, the output timing is determined depending on the count timing of the timing counter 515. In the second embodiment, by adding a general-purpose port latch 400, it is possible to output from the display segment/digit signal output terminal 503 at any time without depending on the count timing of the timing counter 515.

The data bus 50 is connected to the general-purpose port latch 400.
When you write the data you want to output through 5, the OR circuit 5
19 and a high-voltage buffer 513, the signal is outputted from the display segment/digit signal output terminal 503.

In order to make the operation easier to understand, FIG.
The display data portion and display digit portion of the second embodiment are extracted. In FIG. 5, the bit positions correspond to each other in the vertical direction, and data is sent from the top to the bottom.

The number of digits to be displayed is preset by the number of digits setting circuit 518, and the number of digits to be displayed by the display timing decoder 516 is also determined by this. This also uniquely determines the number of clocks of the corrected shift clock signal 128 output from the shift correction circuit 126. The display data is serially transferred to the shift register B123 (in FIG. 5, the shift register B123 is shifted from the left side), and the transferred display data is stored in the display data latch 506. As a result, in the OR circuit 519, the display data latch 50
6. As a result, the OR circuit 519 outputs the display data latch 506 output and the display timing decoder 516.
The logical sum of the outputs is taken, and among the bits corresponding to the display segment/digit signal output terminal 503, the bits that are not designated as display digit signal output are used as display data output terminals.

However, in the second embodiment, the data output from the display segment/digit signal output terminal 503 is simply ORed by the OR circuit 519.
In this case, of the data serially transferred to the shift register B 123, bits other than display data, that is, bits to be ORed with the output data bits of the general-purpose port latch 400, must be set to "0".

The operation timing of the entire circuit is the same as that shown in FIG. 2, which is the operation timing of the first embodiment.

[0048]

As described above, the present invention provides a microcomputer incorporating a conventional display controller with a first shift register, a serial data signal, a second shift register, a clock signal, a shift clock generation circuit,
By including a shift correction circuit, a shift clock signal, a corrected shift clock signal, a digit number data signal, and a shift clock mask signal, the serial data signal line 1 can transfer data from the memory where display data is stored to the display data latch. book, and serial clock signal line 1
Since this is possible with a total of two wires, it is possible to prevent an increase in the number of wires due to an increase in the number of display segments, and as a result, the chip area of the microcomputer can be reduced. Further, there is an effect that restrictions on the arrangement inside the microcomputer can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing main parts of a first embodiment of the present invention.

FIG. 2 is a display timing diagram.

FIG. 3 is an explanatory diagram of its operation.

FIG. 4 is a block configuration diagram showing main parts of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of its operation.

FIG. 6 is a block configuration diagram showing main parts of a conventional example.

FIG. 7 is a display timing diagram.

[Explanation of symbols]

121 Shift register A 122 Serial data signal 123 Shift register B 124 Clock signal 125 Shift clock generation circuit 126 Shift correction circuit 127 Shift clock signal 128 Correction shift clock signal 129 Number of digits data signal 130 Shift clock mask signal 400 General-purpose port latch 500, 500a , 500b Microcomputer 501 (501-1 to 501-n) Display digit signal output terminal 502 Display memory 503 (503-1 to 503-m) Display segment/digit signal output terminal 504 Address selector 505 Data bus 506 Display data latch 507 Memory write signal 508 Display data read signal 509 Address bus 510 Address generation circuit 511 Counter 512 Count clock signal 513, 514 High voltage buffer 515 Timing counter 516 Display timing decoder 517 Memory read signal 518 Number of digits setting circuit 519 OR circuit (OR) 520 match signal

Claims (3)

[Claims] [Claim 1] A display memory that stores display data;
a digit number setting circuit that can specify the number of display digits; a display timing decoder that outputs a display digit signal; a display data latch that latches and outputs display data read from the display memory; In a microcomputer equipped with a display controller that includes a plurality of display segments and a digit signal output terminal that outputs the output of a display data latch to the outside, a plurality of bits that read and store display data in the display memory and serially output it. a first shift register, a multi-bit second shift register that stores display data output from the first shift register and outputs the display data in parallel to the display data latch; A shift clock generation circuit that generates a shift clock signal for shifting the shift register, and a shift correction circuit that controls the generated shift clock signal according to the value of the digit number setting circuit. microcomputer. 2. The microcomputer according to claim 1, wherein the display controller is a fluorescent display tube controller. 3. The microcomputer according to claim 1, wherein the display controller is an LCD controller.