JPH04316161A - Multiinput arithmetic circuit - Google Patents

Abstract

PURPOSE:To increase the operating speed and to miniaturize the circuit scale and size of such a multiinput arithmetic circuit that processes the added results of multiinput adding circuits with a logic circuit. CONSTITUTION:This multiinput arithmetic circuit is provided with plural multiinput adding circuits 1A-1D, a simple logic circuit 10 which produces plural processed results by performing prescribed operation on the added results of the circuits 1A-1D, and multiinput adding circuits 17 and 7 which add the plural processed results to each other. Then the added results of the circuits 1A-ID in the prestage are supplied to the circuit 10 in a redundant expression composed of summed outputs and carried outputs and the circuit 10 supplies the plural processed results to the circuits 17 and 7 in its post stage in a redundant expression. The circuits 17 and 7 output the added results in an ordinary binary expression.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-input arithmetic circuit suitable for application to, for example, a circuit system in which a multi-input adder circuit and a logic arithmetic circuit with a simple configuration coexist.

0002

[Prior Art] As an example of a multi-input arithmetic circuit in which a multi-input adder circuit and a logic arithmetic circuit with a simple configuration are mixed,
A circuit as shown in FIG. 4 is known. In FIG. 4, 1A to 1D each indicate an adder circuit with redundant expression of 4 inputs, and the adder circuit 1A adds four input data A to D and outputs the addition result as a sum output and a carry output. The data is supplied to the subsequent carry adder 2A in a redundant expression (described later), and the other adder circuits 1B, 1C, and 1D each add the four input data E~H, I~L, and M~P, and add the four pieces of input data E~H, I~L, and M~P. The addition results are supplied in redundant expressions to the carry adders 2B to 2D, respectively. Each of these carry adders 2A to 2D converts the addition result input in redundant representation into an addition result in normal binary representation.

Reference numeral 3 indicates a simple logic circuit. In this simple logic circuit 3, the output data of carry adders 2A and 2B are supplied to one input section and the other input section of a data selector 4A, respectively, and the output data of carry adder 2C is supplied. Double output data circuit 5
A and the data selector 4 through the quadruple circuit 5B.
B, and carry adder 2D.
The output data is supplied to one and the other input section of the data selector 4C via the 8x circuit 5C and the 16x circuit 5D, respectively. The 2x circuits 5A to 16x circuits 5D can be easily constructed by simply shifting the input data wiring and the output data wiring, respectively.

Reference numeral 6 indicates a multi-input adder circuit with redundant expression following the simple logic circuit 3, and this adder circuit 6 adds the data output from the data selectors 4A to 4C of the simple logic circuit 3, The addition result is supplied to a carry adder 7 in a redundant representation consisting of a sum output and a carry output, and the carry adder 7 converts the addition result in the redundant representation into a normal binary representation. That is, the simple logic circuit 3 outputs the output data of the adder 2A or 2B, the data obtained by multiplying the output data of the adder 2C by 2 times or 4 times, and the data obtained by multiplying the output data of the adder 2D by 8 times or 16 times. The adder circuit 6 is a circuit that adds these three types of data.

Referring to FIG. 5, a specific example of the configuration of a multi-input adder consisting of an adder circuit 1A with redundant expression and a carry adder 2A in the circuit of FIG. 4 will be described. Each of the data A to D is
It is expressed as a binary number of bits (n is an integer of 2 or more). A=(An-1, An-2,..., A1, A0) B=(
Bn-1, Bn-2,..., B1, B0)C=(Cn-
1,Cn-2,...,C1,C0)D=(Dn-1,D
n-2,...,D1,D0)

[0006] In this expression, An-1 to Dn-1 are the maximum digits (MSB), respectively.
This multi-input adder is a circuit that obtains the addition result of (A+B+C+D) in binary representation. First, the adder circuit 1A includes n full adders (FA) 8-0 to 8-0 in the first stage.
8-(n-1) and second stage n full adders 9-0 to 9
-(n-1). The full adder 8-0 in the first stage stores three bits A0, B0 and C0.
Similarly, full adders 8-1 to 8-(n-1) each add three bits A1, B1, C1 to An-1, Bn.
-1 and Cn-1 are added. These full adders 8-0 to 8
-(n-1) sum output and carry output, (A+B
+C) is expressed. This method of expressing a numerical value by storing carry output every few bits (in the example of FIG. 5, every 1 bit) is called the carry-save adder method.

Further, the full adder 9-0 in the second stage is “
0", the sum output of the full adder 8-0, and the bit D0 of the input data D, and the total adder 9-i (i=1,..., n-
1) adds the carry output of full adder 8-(i-1), the sum output of full adder 8-i, and bit Di of input data D, respectively. The sum output and carry output from these full adders 9-0 to 9-(n-1) result in (A+B+C
+D) is expressed using the carry-save adder method. Furthermore, each time the number of addition targets increases by one in addition to A to D, a circuit system consisting of n full adders is added to the adder circuit 1A, thereby expressing the entire addition result in a carry-save adder method. be able to. When the addition result is expressed using the carry-save adder method in this way, the time for the carry to gradually propagate to the higher digits can be saved, so that the calculation speed can be increased.

The addition result expressed by the carry-save adder method outputted from the adder circuit 1A is supplied to a carry adder 2A. This carry adder 2A is configured by connecting n full adders such that, for example, a lower carry output terminal and an upper carry input terminal are connected. The result of addition (A+B+C+D) is output as n-bit data in normal binary format. Such a carry adder 2A can also be considered to be a two-input adder. In the case where n full adders are simply connected in this manner, the calculation speed becomes slow because it takes time for the carry to propagate to the higher-order digits. On the other hand, by configuring the carry adder 2A using a carry look-ahead circuit or a carry select adder circuit, the calculation speed can be increased, but the circuit scale will be increased.

Furthermore, in the circuit of FIG. 4, the redundant expression multi-input addition circuit 6 and carry adder 7 can be configured similarly to the addition circuit 1A and carry adder 2A of FIG. 5, respectively.

0010

[Problem to be solved by the invention] Figure 4 summarizes the above
In the conventional multi-input arithmetic circuit, adder circuits 1A to 1D are provided, each of which adds four pieces of input data (for example, A to D) at high speed using a carry-save adder method, and these adder circuits 1A to 1D At the subsequent stage, carry adders 2A to 2D are provided for converting the addition results of redundant representations into normal binary representations. However, in order to make the calculation speed of these carry adders 2A to 2D as fast as those of the adder circuits 1A to 1D, it is necessary to configure these two-input carry adders 2A to 2D using a carry look-ahead circuit or the like. There is. However, since four such carry adders 2A to 2D are provided in the example of FIG. 4, there is a disadvantage that the overall circuit scale becomes large.

[0011] In view of the above, the present invention is designed to increase the calculation speed and reduce the circuit scale in a multi-input arithmetic circuit in which the simple logic circuit 3 processes the addition results of the multi-input adder circuits 1A to 1D. The purpose is to

0012

[Means for Solving the Problems] A multi-input arithmetic circuit according to the present invention, as shown in FIG. It has a logic operation circuit (10) that performs a predetermined operation on the result to generate a plurality of processing results, and a multi-input addition circuit (17, 7) in the subsequent stage that adds the plurality of processing results,
The addition result of the multi-input adder circuit (1A to 1D) at the previous stage is supplied to the logic operation circuit (10) in a redundant expression consisting of a sum output and a carry output, and the logic operation circuit (10)
supplies these multiple processing results in a redundant representation to the multi-input addition circuit (17, 7) in the subsequent stage, and the multi-input addition circuit (17, 7) in the subsequent stage expresses the addition results in a normal representation (e.g. It is designed to output in normal binary representation).

[0013]

[Operation] According to the present invention, the addition results of the multi-input adder circuits (1A to 1D) in the preceding stage are supplied to the logic operation circuit (10) with redundant expressions, and the addition results are supplied to the logic operation circuit (10). The processing result obtained by 10) is supplied as a redundant representation to the multi-input adder circuit (17, 7) at the subsequent stage, and the conversion from the redundant representation to the normal representation is carried out by the multi-input adder circuit (17, 7) at the subsequent stage. 17, 7). Therefore, the conversion circuit to normal representation, which requires a large circuit scale to perform high-speed calculations, is replaced by a multi-input adder circuit (17,
7), the circuit scale is small even though the overall calculation speed is high.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multi-input arithmetic circuit according to the present invention will be described below with reference to FIG. This example is a circuit that executes the same calculation as the conventional multi-input calculation circuit shown in FIG. 4, and the parts in FIG. 1 corresponding to those in FIG. 4 are given the same reference numerals and detailed explanation thereof will be omitted. In FIG. 1, A~
Each P is a binary number of n bits (n is an integer of 2 or more), and each adder circuit 1A, 1B has a redundant representation with 4 inputs.
, 1C and 1D respectively (A+B+C+D), (
E+F+G+H), (I+J+K+L) and (M+N+
The addition result of 0+P) is output in a redundant expression consisting of a sum output and a carry output. In FIG. 1, the adder circuit 1A
The number of output terminals derived from ~1D is two, but in reality, each output terminal is n as shown in adder circuit 1A in FIG.
A pair of output terminals are derived.

Reference numeral 10 indicates a simple logic circuit, and this simple logic circuit 10 is supplied with the addition results of redundant expressions from the adder circuits 1A to 1D. Execute operations with redundant expressions. This simple logic circuit 10 is divided into circuit systems 11 to 13. In the circuit system 11, the sum output and carry output of the adder circuit 1A are supplied to one input section of the data selectors 14A and 14B, respectively, and the sum output and carry output of the adder circuit 1B are supplied to the other input part of the data selectors 14A and 14B, respectively. Supplied to the input section of Actually data selector 14A
and 14B are provided in n pairs, each of which selects one of the data in conjunction with the other.

In the circuit system 12, the carry output of the adder circuit 1C is supplied to two input sections of the data selector 16A via the doubling circuit 15A and the quadrupling circuit 15B, and the sum output of the adder circuit 1C is Double circuit 15C and quadruple circuit 15D
The data is supplied to two inputs of the data selector 16B via. There are also n pairs of data selectors 16A and 16B, each of which selects any data in conjunction with each other. In addition, in the circuit system 13, the carry output of the adder circuit 1D is supplied to the two input sections of the data selector 16C via the 8x circuit 15E and the 16x circuit 15F, and
The sum output of D is supplied to two input sections of a data selector 16D via an 8x circuit 15G and a 16x circuit 15H. There are also n pairs of data selectors 16C and 16D, each of which selects any data in conjunction with each other.

Reference numeral 17 indicates a multi-input adder circuit with redundant expression, and data selectors 14A and 14B are connected to this adder circuit 17.
, output data of data selectors 16A and 16B, and output data of data selectors 16C and 16D. That is, the addition circuit 17 contains the addition result of the addition circuit 1A or 1B, a value obtained by doubling or quadrupling the addition result of the addition circuit 1C, and a value obtained by multiplying the addition result of the addition circuit 1D by 8 or 16. Each numerical value is supplied in a redundant representation consisting of a sum output and a carry output, and the addition result of these numerical values is supplied in a redundant representation to a carry adder 7 at the final stage, and from this adder 7 a normal 2 Data in hexadecimal representation is output. The data output from this carry adder 7 is the same as the data output from the carry adder 7 in the example of FIG.

Comparing the example in FIG. 1 and the example in FIG. 4, the simple logic circuit 10 in FIG. The circuit scale will be approximately doubled. Furthermore, the output of the simple logic circuit 10 is also a redundant expression, and the number of inputs to the adder circuit 17 in the subsequent stage is twice the number of inputs to the adder circuit 6 in the example in FIG. The scale will be larger than the conventional example. However, in this example, the carry adders 2A to 2D in the conventional example of FIG. There is an advantage that the overall circuit scale of the input arithmetic circuit can be made smaller than that of the conventional example. Furthermore, by configuring the adder circuit 17 in a pipelined manner, the overall circuit scale can be further reduced.

Note that the redundant multi-input adder circuits 1A to 1D and 17 in the example of FIG. 1 can be replaced by redundant accumulators that sequentially add input data in a time-sharing manner. In addition, in the circuit configuration of the example shown in FIG. 1, the multi-input adder circuits 1A to 1D, the simple logic circuit 10, and the multi-input adder circuit 17 are connected in cascade. Later, a logic circuit with a simple configuration of redundant expression and a multi-input adder circuit with redundant expression may be sequentially connected. In addition, in FIG. 1, the processing result output from the simple logic circuit 10 in a redundant expression is held in a register as it is, and the value held in this register is stored in the redundant expression multi-input adder circuits 1A to 1A. The present invention is also applicable to the case of feeding back to the input side of 1D.

Next, other embodiments of the present invention will be described with reference to FIGS. 2, 3 and 6. In this example, the present invention is applied to an interpolation circuit using a cubic function. cubic function Q(x)
is a function defined as follows using an arbitrary constant α. A feature of this cubic function is that it is always normalized regardless of the value of the constant α.

[Math. 1] Q(x)={(α+2)|x|−(α+3)}|x|2
+1 (|x|≦1), Q(x)=α[{(|x|
-5)+8}|x|-4] (1<|x|≦2), Q
(x)=0 (2<|x|)

Normally, when used as a complement function, α=-1, so the cubic function Q(x) is used in the following format.

[Math. 2] Q(x)=|x|3 −2|x|2 +1
= (|x|-1) (|x|2 -|x|-1)
(|x|≦1), Q(x)=-|x|3 +5|x|2
-8|x|+4 =-(|x|-1)
(|x|-2)2 (1<|x|≦2)Q(x
)=0 (2<|x|)

[0022] Then, if a series of discrete sampling data on the time axis t are I(i), I(i+1), ..., then the interpolation value I(x)' at any time x is as follows. It can be expressed as

[Math 3] I(x)'=Σ Q(x-i)・I(i)

[
In Equation 3, Σ represents the sum with respect to i. Furthermore, since Q(x) is 0 when 2<|x|, there are only four valid data I(i) in the number 3. Therefore, assuming 0<x<1, I(-
1)=C, I(0)=A, I(1)=B, I(2)=D
Assuming that, the number 3 can be expressed as follows.

[Math. 4] I(x)'=Q(x)・A+Q(1-x)・B+Q
(1+x)・C +Q(2
-x)・D (0<x<1)
= [(1-x)A+xB] +(x-x2) {[
(1-x)A+xB]-[(1-x)C+xD]}

0
[024] Also, the latter half of the transformation in Equation 4 has Q(x
), etc., are used.

[Formula 5] Q(x)=(x-1)(x2-x-1),Q
(1-x)=-x(x2-x-1), Q(1+x)=
-x(x-1)2 , Q(2-x)=x2 (x-1)

For example, when using a value of 1/8 step as x, [(1-x)A+x
The value of B] is as follows.

[Table 1] x [(1-x)A+xB]1
/8 A/8+B/8+A/4+A
/22/8 A/8+A/8+B/
4+A/23/8 A/8+B/8
+B/4+A/24/8 A/8+
A/8+A/4+B/25/8 A
/8+B/8+A/4+B/26/8
A/8+A/8+B/4+B/27/8
A/8+B/8+B/4+B/2

0026
] In the operations in Table 1, the operations (1/8), (1/4), and (1/2) can be easily executed by shifting the data by 3 bits, 2 bits, and 1 bit, respectively. can. Also, in the latter half of Equation 4, [(1-
x)C+xD] is the same as the value of [(1-x)A+xB]. Furthermore, the value of (x-x2) in the latter half of Equation 4 changes as follows in response to the value of x.

[Table 2] x (x-x2)1
/8 7/64= 1/8-1/
642/8 12/64=1/4-
1/163/8 15/64=1/
4-1/644/8 16/64=
1/2-1/45/8 15/64
=1/4-1/646/8 12/
64=1/4-1/167/8 7
/64= 1/8-1/64

These Table 1
Using the relationships in Table 2, it can be seen that I(x)' in Equation 4 can be executed by a shift operation circuit and an addition/subtraction circuit. Using the relationships in Tables 1 and 2 above, I(x)' in equation 4
FIG. 6 shows an example of a conventional configuration of an interpolation circuit for calculating . In this FIG. 6, input data A is passed through an adder circuit 2 through a 1/8 circuit 19A that converts the input data to 1/8.
0, and this input data A is sent to the data selector 18A.
-18C, input data B is supplied to the other input part of data selectors 18A-18C, and the output data of these data selectors 18A, 18B, and 18C is input to 1/8 circuit 19B, and input data B is supplied to one input part of data selectors 18A-18C. 1/4
The input data is supplied to an adder circuit 20 for redundant expression with 4 inputs via a 4-input circuit 19C and a 1/2 circuit 19D that halves the input data, and from this adder circuit 20, the input data is redundantly expressed by a sum output and a carry output. The added result is supplied to the carry adder 21. From this carry adder 21, [(1-x)A of Table 1]
+xB] is output in binary format.

Similarly, the input data C is sent to the 1/8 circuit 23A.
The input data A is supplied to one input section of the data selectors 22A to 22C, and the input data D is supplied to the other input section of the data selectors 22A to 22C. 22A, 22
The output data of B and 22C is transferred to 1/8 circuit 23B, 1/4
The signal is supplied to the redundant expression addition/subtraction circuit 24 via the circuit 23C and the 1/2 circuit 23D. This addition/subtraction circuit 24 subtracts the output values of the circuit systems 23A to 23D from the addition result of the addition circuit 21, and supplies this subtraction result to the carry adder 25 in a redundant expression using a sum output and a carry output. . From this carry adder 25, [(1-x)A+xB] in number 4
- The calculation result of [(1-x)C+xD] is output in binary format.

The output data of this carry adder 25 is
2 circuits 27A, 1/4 circuits 27B and 1/8 circuits 27C
is supplied to the input section of the 3-input data selector 28A via the
4 circuits 27D, 1/16 circuits 27E and 1/64 circuits 2
7F to the input part of a three-input data selector 28B, the output data of these data selectors 28A and 28B is supplied to the input part of the adder/subtractor circuit 26, and the output data of the carry adder 21 is supplied to the adder/subtracter 26. Supplied to the input section of The addition/subtraction circuit 26 adds the output data of the data selector 28A to the output data of the carry adder 21,
The output data of the data selector 28B is subtracted from this addition result, and the result obtained thereby is supplied to the carry adder 29 in a redundant representation.

Circuit system 27A to 27F and addition/subtraction circuit 26
Since (x-x2) in Table 2 is calculated, the carry adder 29 outputs I(x)' of Equation 4 in a normal binary format. An interpolation circuit constructed by applying the present invention to the interpolation circuit shown in FIG. 6 is an interpolation circuit based on a cubic function shown in FIG. In FIG. 2, in which parts corresponding to FIG. The result is supplied as is, and in parallel, the circuit system 23 is supplied to this addition/subtraction circuit 30.
Four output data A to 23D are supplied. This addition/subtraction circuit 30 calculates the sum of the circuit system 23A from the addition result of the addition circuit 20.
The four output data of ~23D are subtracted, and the result obtained is output in a redundant expression consisting of a sum output and a carry output.

The sum output of the addition/subtraction circuit 30 is supplied to the input section of a three-input data selector 33A via a 1/2 circuit 32A, a 1/4 circuit 32B, and a 1/8 circuit 32C, and the sum output is supplied in parallel. 1/4 circuit 32D, 1/16 circuit 3
2E and 1/64 circuit 32F to the input part of a 3-input data selector 33C, and the output data of these data selectors 33A and 33C is supplied to the input part of a 6-input redundant expression adder/subtracter circuit 34 to perform addition. The addition result of the circuit 20 is supplied to the input section of the addition/subtraction circuit 34 in its redundant representation. Also, the carry output of the addition/subtraction circuit 30 is set to 1
/2 circuit 31A, 1/4 circuit 31B and 1/8 circuit 31
C to the input section of the 3-input data selector 33B, and in parallel, the carry output is supplied to the 1/4 circuit 31D, 1
It is supplied to the input section of a three-input data selector 33D via the /16 circuit 31E and the 1/64 circuit 31F, and the output data of these data selectors 33B and 33D is supplied to the input section of the addition/subtraction circuit 34.

The addition/subtraction circuit 34 adds the output data of the data selectors 33A and 33B to the output data of the addition circuit 20, and subtracts the output data of the data selectors 33C and 33D from this addition result, thereby obtaining the result. is supplied to the carry adder 29 in a redundant representation. This carry adder 29 outputs interpolated data I (
x)' is output in normal binary format. In the interpolation circuit in FIG. 2, the carry adders 21 and 25, which are larger in circuit scale than in the interpolation circuit in FIG. 6, are omitted, so the overall circuit scale is reduced compared to the example in FIG. be able to.

An example in which the interpolation circuit shown in FIG. 2 is constructed using a time division processing method will be described with reference to FIG. 3. This figure 3
Input data A, B, C, and D are supplied to the input section of a four-input data selector 35, and the data selector 3
5 is supplied to the barrel shifter 36. This barrel shifter 36 is a circuit that shifts input data by n bits to the lower digit side and outputs the resultant data.This output data is directly transmitted and the two input data is transmitted through a two's complementer 37 that multiplies the input data by -1. The output data of this data selector 38 is supplied to the input part of the selector 38 and
supply to. This accumulator 39 outputs the accumulation result in a redundant expression consisting of a sum output and a carry output.

The sum output of the accumulator 39 is supplied to the first and third input parts of a four-input data selector 41 via data holding registers 40A and 40C, and the carry output of the accumulator 39 is supplied to the register 40B. and 40D to the second and fourth inputs of the data selector 41. Numeral 42 denotes a barrel shifter that shifts the input data by n bits to the lower digit side in the same way as the barrel shifter 36, and outputs the output data of the data selector 41 through the barrel shifter 42 to one input section of the two-input data selector 44 and is supplied to the complementer 43 of
The output data of this two's complementer 43 is supplied to the other input section of the data selector 44, and the data selector 44
The output data of is supplied to the accumulator 45. This accumulator 45 also supplies a sum output and a carry output, and an accumulation result expressed more redundantly, to a carry adder 46.

To explain the operation of the example shown in FIG. 3, by controlling the 4-input data selector 35, the barrel shifter 36, and the 2-input data selector 38 from the outside, the accumulator 39 receives A/8, A/4, and A/8. 2,B/8,B
/4 or B/2 is sequentially supplied and integrated. Since the accumulator 39 calculates [(1-x)A+xB] shown in Table 1, this value is held in the registers 40A and 40B. Following that, data selectors 35 and 38,
By controlling the barrel shifter 36 and the two's complementer 37 from the outside, the accumulator 39 is sequentially supplied with -C/
8, -C/4, -C/2, -D/8, -D/4 or -D
/2, and this accumulator 39 supplies {[(1-x
)A+xB]-[(1-x)C+xD]},
This calculation result is held in registers 40C and 40D.

Next, the data held in the registers 40A and 40C, [(1-x)A+xB], is transferred to the accumulator 45.
By externally controlling the 4-input data selector 41, barrel shifter 42, 2's complementer 43, and 2-input data selector 44, the accumulator 45 converts (x-x2) {[(1-x )A+xB]-[
(1-x)C+xD]} is added. Therefore, the carry adder 46 at the final stage outputs the interpolated data I(x)' of Equation 4 in a normal binary format. The example shown in FIG. 3 has the advantage that the circuit scale can be extremely miniaturized.

It should be noted that the present invention is not limited to the above-described embodiments, but can of course take various configurations without departing from the gist of the present invention.

[0038]

Effects of the Invention According to the present invention, there is no need to connect a carry adder with a large circuit scale between a multi-input adder circuit and a logic operation circuit, so the overall operation speed is increased and the circuit size is reduced. There is an advantage that it can be downsized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a multi-input arithmetic circuit according to the present invention.

FIG. 2 is a block diagram showing the configuration of an interpolation circuit using a cubic function, which is another embodiment of the present invention.

FIG. 3 is a block diagram showing a modification of the example in FIG. 2;

FIG. 4 is a block diagram showing an example of a conventional other input calculation circuit.

FIG. 5 is a configuration diagram showing a multi-input adder in the example of FIG. 4;

FIG. 6 is a block diagram showing a conventional configuration example of an interpolation circuit using a cubic function.

[Explanation of symbols]

1A to 1D 4-input redundant expression addition circuit 10 Simple logic circuit 17 Multi-input redundant expression addition circuit 7 Carry adder 20 4-input redundant expression addition circuit 30 6-input redundant expression addition/subtraction circuit 29 Carry adder

Claims (1)

[Claims] 1. One or more multi-input adder circuits in the preceding stage, a logic operation circuit that performs predetermined operations on the addition results of the adder circuits to generate a plurality of processing results, and the plurality of processing results. and a rear-stage multi-input adder circuit that adds the above-mentioned logic operation circuit, and supplies the addition result of the previous-stage multi-input adder circuit to the logic operation circuit in a redundant expression consisting of a sum output and a carry output. The arithmetic circuit supplies the plurality of processing results in a redundant representation to the multi-input addition circuit in the subsequent stage, and the multi-input addition circuit in the latter stage outputs the addition results in a normal representation. Multi-input arithmetic circuit.