JPH04306876A - gate array integrated circuit - Google Patents

Abstract

PURPOSE:To provide a BiCMOS gate array integrated circuit enhanced in degree of integration and high in operation speed. CONSTITUTION:A bipolar transistor region isolated from an inner region is not provided, basic cells 4 composed of a CMOS transistor and an NPN bipolar transistor 3 whose base is formed in common with the source or the drain diffusion region of the PMOS transistor of the CMOS transistor are arranged spreading all over the inner gate region to serve as a BiCMOS gate array integrated circuit.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a gate array integrated circuit in which a transistor diffusion layer called a gate array is used as a common pattern, and various logics are realized by wiring patterns on the gate array.
Gate arrays (hereinafter referred to as CMOS transistors) and bipolar transistors arranged regularly (Sea
of Gate Array) This relates to integrated circuits.

0002

[Prior Art] In recent years, VLSIs, represented by memories and processors, have tended to become larger in scale.
MOS transistors are becoming mainstream. but,
In response to the demand for higher speed, MO
Even though the operating speed of S has improved, the current situation is that it cannot fully meet the demands. Normally, in the high-speed field, bipolar transistors, mainly ECL, are mainstream, but bipolar elements consume extremely high power, which is a major constraint on high integration.

[0003] Against this background, in order to realize high-speed, low-power consumption devices, BiCMOS technology is attracting attention because it combines the characteristics of high integration and low power consumption of CMOS transistors with the high-speed performance of bipolar transistors. It's coming.

FIG. 11 shows a gate array (hereinafter referred to as B) comprising conventional bipolar transistors and CMOS transistors.
(referred to as iCMOS gate array), 2 input NA
1 is a diagram showing an example of the structure of a basic cell of an ND gate, which is shown in, for example, Japanese Patent Laid-Open No. 165751/1983.

In FIG. 11, reference numeral 4 denotes a basic cell of a gate array, and inside the basic cell 4, a PMOS transistor 1, an NMOS transistor 2, bipolar transistors 14 and 15, and resistors 16 and 17 are formed. 28
is a gate electrode, 34 and 35 are isolation regions of bipolar transistors 14 and 15, respectively, and 36 is an N well.
In the N-well 36, there is a diffusion layer 32 as a channel region, source, and drain diffusion region of the PMOS transistor 1.
is formed. Further, 33 is a diffusion layer serving as a channel region, source, and drain diffusion region of the NMOS transistor 2.

When a gate array is constructed from such basic cells 4, all gate electrodes 28 do not need to be BiCMOS gates, so there are many bipolar transistors 14 and 15 separated from CMOS transistors. Therefore, a problem arises in that the degree of integration becomes low.

In order to solve this problem and use the area as effectively as possible, IE developed a basic cell structure with one bipolar transistor for multiple CMOS transistors. Custom Integrated Circuits Conference 1989 8.5.1 - 8.5.4 pages (I
EEE CICC 1989 P. P. 8.5.1
-8.5.4), which is shown in FIG. In addition, FIG. 13 shows BiCMO using the basic cell of FIG.
FIG. 2 is a plan view showing a basic cell pattern layout showing a concept when configuring an S logic gate. In these figures, the same reference numerals as in FIG. 11 indicate the same or corresponding parts, and 1
Reference numeral a indicates the gate of the PMOS transistor, numeral 37 indicates an N+ diffusion layer for obtaining a potential with the N well, and numeral 38 indicates a P+ diffusion layer for obtaining a potential with the P well. Further, 18 is a logic gate of a BiCMOS transistor composed of a PMOS transistor 1, an NMOS transistor 2, a resistor 17, and bipolar transistors 14 and 15.
Reference numeral 19 indicates the wiring area.

The BiCMOS gate array circuit shown in FIG. 12 in which the basic cells 4 are arranged on the same semiconductor substrate minimizes the number of separated bipolar transistors, and if necessary, the basic cells adjacent above and below can be connected to each other. Bipolar transistors are used. This results in one C
The number of bipolar transistors separated from the MOS transistors is one, which is half of the conventional number, and an increase in chip size is suppressed.

[0009]

[Problems to be Solved by the Invention] However, the basic cell 4 for the BiCMOS gate array shown in FIG.
The area of the bipolar portion is still quite large, and for example, with the same design rules, the cell area is about 2 to 3 times larger than that of a CMOS gate array, resulting in a considerable reduction in the degree of integration.

The present invention was made to solve the above-mentioned problems, and its purpose is to provide a BiCMOS gate array integrated circuit that can increase the degree of integration and speed up. do.

[0011]

[Means for Solving the Problems] A gate array integrated circuit according to the present invention provides a CMOS transistor, an NMOS transistor of a CMOS transistor, a PM
Two bipolar transistors formed so that the respective source or drain diffusion regions of the OS transistors are shared with their bases, or the source or drain diffusion regions of either an NMOS transistor or a PMOS transistor are formed so as to share their bases. Basic cells each having one bipolar transistor formed in the above manner are arranged in an internal gate region to form a BiCMOS gate array.

0012

[Operation] The gate array integrated circuit according to the present invention has a CM
OS transistor and PMOS of CMOS transistor
transistor, two bipolar transistors fused to each NMOS transistor, or PMO
Since the basic cell is constructed using only bipolar transistors fused to either the S transistor or the NMOS transistor, there is no independent bipolar transistor area separated from the internal area within the basic cell, and the area of the entire chip is reduced. It can be used effectively. Furthermore, since the wiring length is shortened, the load capacitance is reduced and the speed can be increased.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a basic cell structure of a gate array integrated circuit according to an embodiment of the present invention. In the figure, 1 is a PMOS transistor, 2 is an NMOS transistor, and 3 is an NPN bipolar transistor fused to the PMOS transistor 1, which makes the basic cell 4
It consists of In addition, 20 is a PMOS transistor 1
N-well potential fixing region and collector region of NPN bipolar transistor transistor 3, 21, 24, 2
6 is an isolation oxide film region, 22 is a P+ source/drain diffusion region, and a channel region of PMOS transistor 1;
23 is the base and emitter region of the NPN bipolar transistor 3, 25 is the N+ source/drain diffusion region and the channel region of the NMOS transistor 2, and 27 is the NM
This is the P-well potential fixing region of the OS transistor, and 28
is the gate electrode.

In addition, in FIG. 2, only the pull-up side is BiCMO.
2 shows a circuit diagram of a pull-up BiCMOS type 2-input NAND gate, denoted by S. In FIG. PM formed as a base
NPN bipolar transistor integrated into the OS transistor, 5 is a power supply terminal, 6 is a terminal that supplies ground potential, 7 and 8 are both input pins connected to the gate of NMOS transistor 2, 9 is an output pin, 10 is a PMOS transistor 1 is a base charge extraction resistor of a bipolar transistor 3 fused to 1, which consists of a PMOS transistor whose gate is connected to ground 6.

FIG. 3 shows an example of a layout pattern of a gate array integrated circuit according to an embodiment of the present invention corresponding to FIG. 2, and FIG. 4 shows a cross-sectional view taken along line IV-IV' in FIG. Figure 3,
In FIG. 4, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding parts, 1a is the gate of the PMOS transistor 1, 1b is the source or drain region of the PMOS transistor, and 11 is an aluminum wiring. Also,
1c is the N-well of the PMOS transistor, 3a, 3b,
3c shows the emitter region, base region, and collector region of the bipolar transistor 3 integrated into a PMOS transistor, 12 is an isolation oxide film, and 30 is a PMOS transistor.
type semiconductor substrate, 31 is an N+ semiconductor layer.

In FIG. 2, bipolar transistor 3
The base charge extraction resistor 10 uses the ON resistance of a PMOS transistor instead of a built-in resistor. Further, the collector 3c of the bipolar transistor 3 is always connected to the power supply potential 5. Therefore, as shown in FIG. 4, the collector 3c of the bipolar transistor 3 is set to P
It is possible to share the well 1c of the MOS transistor 1. Therefore, the source of the PMOS transistor
The base 3b of the bipolar transistor 3 is made in contact with the drain 1b, and the emitter 3a can be made therein.

FIG. 1 shows the layout pattern of the cell created in this manner. In FIG. 1, the basic cell 4 is P
MOS transistor 1, NMOS transistor 2 and PM
It is composed of an NPN bipolar transistor 3 integrated with an OS transistor 1. A gate separation method is used to separate the MOS transistors, and a gate separation method is also used to separate the bipolar transistors 3 formed in the source/drain 1a of the PMOS transistor 1. Therefore, the bipolar transistor 3 can be arranged at the same spacing as the MOS transistors 1 and 2. Further, since the base region 3b of the bipolar transistor 3 is connected to the drain region of the PMOS transistor 1, wiring for this is not necessary, and the degree of integration can be greatly increased. Furthermore, since no wiring is required, the load capacity can be reduced and the speed can be increased.

In this way, in this embodiment, a bipolar transistor separated from the internal region is not used, and the PMO
Since the bipolar transistor 3 combined with the S transistor 1 is used, all of them are arranged at the same spacing as the MOS transistors, so there is no waste in the circuit arrangement, and high integration is achieved even though bipolar transistors are used. , high speed can be achieved.

Furthermore, FIG. 6 shows a state in which the basic cells 4 shown in FIG. 1 are arranged in a gate array integrated circuit. It is something that In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. Y like this
When a gate array integrated circuit is configured with a folded arrangement, the unused portion can be treated as a wiring area. Further, according to such an arrangement, since the well potential fixing regions 20 and 27 of the PMOS transistor 1 and the NMOS transistor 2 can be shared in common in adjacent basic cells, the area of the potential fixing region can be halved.
Integration can be achieved. Furthermore, when mounting a large-scale integrated circuit, it is possible to easily change the position of the wiring area according to the logic gate used, and the layout wiring is short and a highly integrated circuit can be constructed. Can be done. Furthermore, since the wiring length can be shortened, the load capacity can be reduced and the speed can be increased.

[0020] Furthermore, the Pull-up Bi shown in FIG.
CMOS types include CMOS, BiCMOS (Push-
(PullBiCMOS type), it is faster within the range of load capacitance required from most fan-outs and wiring capacitances. However, if it is necessary to compensate for the lack of drive ability of the NMOS transistor 2, the gate length of the NMOS transistor 2 may be made smaller than that of the PMOS transistor 1, or the NMOS transistors 1 may be connected in parallel. A speed increase similar to that achieved when bipolar transistors are used (Push-Pull BiCMOS type) can be expected. Figure 5 shows the Pull
-upBi A state in which NMOS transistors 2 are connected in parallel in a CMOS type 2-input NAND gate circuit is shown.

A basic cell of a gate array integrated circuit according to another embodiment of the present invention will be described below with reference to FIG. In FIG. 7, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. The basic cell 4 consists of one PMOS transistor 1, two NMOS transistors 2 and one NPN bipolar transistor 3 integrated into the PMOS transistor 1. In this embodiment, the number of NMOS transistors 2 is increased to two, which is twice as large as that in the above embodiment, but this is similar to the circuit shown in FIG. 5 above, that is, when two NMOS transistors 2 are connected in parallel. To, PM
This is very effective when the number of NMOS transistors 2 is greater than the number of OS transistors 1.

Even when the number of NMOS transistors 2 increases in this way, the MOS
Since the gate separation method is used to separate the transistors and the bipolar transistors 3, the bipolar transistors 3 can be arranged at the same spacing as the MOS transistors 1 and 2, and they can be laid out without waste, making it possible to integrate them. You can increase the degree. Also,
Since the wiring length can be shortened, the load capacity can be reduced and the speed can be increased.

Regarding the basic cell 4 according to the present embodiment shown in FIG. 7, when a gate array integrated circuit is constructed using this, the basic cell 4 is arranged by being folded back only in the Y direction, and its internal area is It is preferable to spread them all over the place, and by doing so, the same effect as in the above embodiment can be expected. Further, a layout pattern of this embodiment corresponding to FIG. 5 is shown in FIG.

Furthermore, FIG. 9 is a diagram showing a basic cell of a gate array integrated circuit according to still another embodiment of the present invention. In the figure, the same reference numerals as those in FIG. It is something. Therefore, higher integration is possible than in the above embodiments. Further, FIG. 10 is a diagram showing the arrangement of the basic cells 4 shown in FIG. 9, which is similar to the above embodiment, in which the basic cells 4 are folded back only in the Y direction and the internal area is covered. .

As mentioned above, although the present invention has been specifically explained based on several embodiments, the present invention is not limited to the above-mentioned embodiments.

That is, in the above embodiment, an example was shown in which an NPN bipolar transistor combined with a PMOS transistor was used as one bipolar transistor in the basic cell, but this also applies to a PNP bipolar transistor combined with an NMOS transistor. In this case as well, the same effects as in the above embodiment can be achieved.

Furthermore, in the above embodiment, the basic cell was constructed of an NPN bipolar transistor combined with a CMOS transistor and a PMOS transistor, but a single bipolar transistor could be similarly combined with the NMOS transistor to form a PNP bipolar transistor. , may be included in the basic cell.

[0028]

As described above, the gate array integrated circuit according to the present invention has a basic cell that is composed of a CMOS transistor and one or two of the CMOS transistors.
Since the structure is composed of two MOS transistors and a bipolar transistor fused, it is possible to eliminate the bipolar transistor region separated from the internal gate region within the basic cell, thereby reducing the basic cell area.
This has the effect that the entire area of the chip can be used effectively and the degree of integration can be increased. Furthermore, since the wiring length can be shortened, the load capacity can be reduced, which is also useful for speeding up the process.

[Brief explanation of drawings]

1 shows a pull-up BiCMOS type basic cell in a gate array integrated circuit according to an embodiment of the invention; FIG.

[Figure 2] 2-input NAND gate (Pull-up BiC
FIG. 3 is a diagram showing a circuit diagram of a MOS type.

FIG. 3 is a diagram showing a layout pattern of basic cells of a gate array integrated circuit according to an embodiment of the present invention, corresponding to FIG. 2;

FIG. 4 is a diagram showing a cross section taken along IV-IV' in FIG. 3;

[Figure 5] 2-input NAND gate (Pull-up BiC
2 is a diagram showing a circuit in which NMOS transistors are connected in parallel in a MOS type.

FIG. 6 is a diagram showing the arrangement of the basic cells shown in FIG. 1 in a gate array integrated circuit.

FIG. 7: Pull-up according to another embodiment of the present invention
1 is a diagram showing a basic cell of BiCMOS type; FIG.

FIG. 8 is a diagram showing a layout pattern of basic cells of a gate array integrated circuit according to another embodiment of the present invention, corresponding to FIG. 5;

FIG. 9: Pull-
2 is a diagram showing a basic cell of up BiCMOS type; FIG.

10 is a diagram showing the arrangement of the basic cells shown in FIG. 9 in a gate array integrated circuit; FIG.

FIG. 11 is a diagram showing a basic cell for a conventional BiCMOS gate array.

FIG. 12 is a diagram showing a basic cell for a conventional BiCMOS gate array.

13 is a pattern plan view showing the concept of configuring a BiCMOS logic gate using the basic cell of FIG. 12; FIG.

[Explanation of symbols]

1 PMOS transistor 1a
PMOS transistor well 2
NMOS transistor 3
Bipolar transistor fused to a PMOS transistor 3a Emitter of a bipolar transistor fused to a PMOS transistor 3b Base of a bipolar transistor fused to a PMOS transistor 3c Collector of a bipolar transistor fused to a PMOS transistor 4 Basic cell 5 Power supply terminal 6 Ground 7 , 8 Input pin 9 Output pin 10 Base charge extraction resistor 11 of bipolar transistor Aluminum wiring 12 Oxide film 13 Built-in resistor 20 N-well potential fixing region of PMOS transistor and collector region 21, 24, 26 of NPN bipolar transistor transistor Isolation oxide film Region 22 P+ Source/drain diffusion region and channel region of PMOS transistor 23 NPN bipolar transistor 3
base and emitter region 25 N+ source/drain diffusion region and channel region of the NMOS transistor 27 P-well potential fixing region of the NMOS transistor 28 gate electrode 29 P+ diffusion region 30 P-type semiconductor substrate 31 N+ diffusion region

Claims (1)

[Claims] 1. A gate array integrated circuit comprising basic cells including complementary transistors and bipolar transistors arranged regularly on the same semiconductor substrate, wherein the basic cells include at least one complementary transistor and bipolar transistors. , two bipolar transistors formed so that the source or drain diffusion region of each of the first conductivity type transistor and the second conductivity type transistor constituting the complementary transistor is shared with the base thereof, or
and one bipolar transistor formed so that the source or drain diffusion region of either the first conductivity type transistor or the second conductivity type transistor is shared with its base. circuit.