JPH04280346A - Block read control system - Google Patents

Abstract

PURPOSE:To efficiently use a common bus without arising logical contradiction and to connect even I/O whose overrun allowance time is short on the block read control system of an information processor. CONSTITUTION:Suppression means 17A suppressing the access of other processors 1 and 2 when the memory reading of the processors 1 and 2 is mishit and during the block reading from a memory 8, priority means 17B which take priority over a request when there is the memory access request from a channel device 5 during block reading, and invalidity means 11A invalidating data which is address-set when a memory write address from the channel device 5 at that time hits the caches 3 and 4 of the processors 1 and 2 are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block read control method for an information processing apparatus having a plurality of processors each having a cache and a channel device. In many information processing devices, cache is employed as a means of increasing speed.

By the way, when there is a read mishit in the cache, a plurality of words are usually read in blocks from the memory and taken into the cache. On the other hand, channel devices also use a common bus to transfer data from I/O to memory. Therefore, it is desired to use the common bus efficiently and without causing logical contradictions.

0003

[Prior Art and Problems to be Solved by the Invention] One of the methods of exclusive control between multiple processors is Test.
and Set. This reads the semaphore area of the shared area and sets the semaphore bit in one access. When acquiring exclusive rights to the shared area of memory, processor 1 performs Test and Set
and the semaphore bit of the read data is “0”
If so, you can start accessing that shared area. (At this time, the semaphore bit in the semaphore area has already become “1”) After that, processor 2 performs Test and
Even if Set is performed, the read data is "1", so exclusive rights cannot be obtained and access cannot be made.

After processor 1 completes its access and writes "0" to the semaphore bit, processor 2's Tes
When t and Set is performed, the semaphore bit read by processor 2 is "0", so processor 2 can start accessing. In this way, Test a
In exclusive control using nd Set, while processor 1 holds the exclusive right, processor 2
I had to hold it while repeating and Set.

[0005] Moreover, the Test and Se
For memory read at time t, a cache cannot be used and the memory must be read directly. In this case, if the semaphore bit is "1" in the first Test and Set, from the second time onward, instead of performing a Test and Set that occupies the memory bus, a normal read is performed to take the semaphore area into the cache, and the data on the cache is One possible method is to repeatedly read data so that the semaphore bit becomes "0".

That is, if processor 1 writes "0" to the semaphore bit while repeatedly reading the cache, the cache is invalidated.
The processor 2 shifts control to read data on the memory, and can read the semaphore bit that has become "0". After this, Test and Set is performed to obtain exclusive rights. This method tests the common bus
There is no need to waste money by repeating Set.

However, this method causes a contradiction in the following case. That is, the processor 2 performs Test and
Because the semaphore bit is already “1” after performing Set,
When performing a normal memory read and reading block data as a miss-read, the semaphore bit is cleared by processor 1 immediately after reading the first word in which the semaphore bit exists, and the semaphore bit becomes "0" in the memory. However, the processor 2 does not notice this and reads the second, third, and fourth words and writes the tag.

Then, the semaphore bit on the memory becomes “0”
Despite this, the data semaphore bit on the cache remains "1". This inconsistency arises because invalidation is not performed while data is being fetched into the cache. Therefore, conventionally, during exclusive control, Test and Set could only always read the semaphore bits from memory.

On the other hand, in such a case, the memory access request of the processor performing the block read is given the highest priority, and other processors or channel devices are prohibited from interrupting and accessing the memory while the block is being read. There are other methods that can be considered, but if the overrun tolerance time of the I/O connected to the channel device is short, the common bus will be occupied by the processor reading the block and the memory cannot be accessed, causing an overrun. .

[0010] Therefore, a problem arises in a system using this method in that I/Os with a short allowable overrun time cannot be connected. The present invention has been made in view of these conventional problems, and is capable of efficiently using a common bus without causing logical contradictions, and also connects I/O with a short allowable overrun time. The purpose of this paper is to provide a block read control method that can perform the following tasks.

[0011]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, 1 and 2 are a plurality of processors having caches 3 and 4, 5 is a channel device, 8 is a memory accessed via a common bus 7, and 17A is a memory read miss of the processors 1 and 2. During block read from memory 8, other processors 1,
17B is a priority means for prioritizing a memory access request from the channel device 5 during a block read;
A is an invalidation means that invalidates the data set in the address when the memory write address from the channel device 5 hits the caches 3 and 4 of the processors 1 and 2 at that time.

0012

In the present invention, when there is a mishit in memory read by processor 1, access by other processors 2 is inhibited during block read from memory 8. As a result, while processor 1 is reading a block, the semaphore bit is not cleared by processor 2's memory write.

Therefore, even when the processor 1 performs a block read of the semaphore area, the consistency between the contents of the cache 3 and the contents of the memory 8 is guaranteed. If there is a memory access request from the channel device 5 during block read,
Priority is given to that request, and if the memory write address from the channel device 5 at that time hits the cache 3 of the processor 1, the data for which the address was hit is invalidated.

[0014] Therefore, the processor 1 can read the data in the memory 8 again since the cache 3 will have a miss on the next access to the same area. In this way, the common bus 7 can be used efficiently without causing logical contradictions, and I/Os with a short allowable overrun time can also be connected.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. 2 to 4 are diagrams showing a first embodiment of the present invention. In FIG. 2, 1 and 2 are processors, and the processors 1 and 2 have built-in caches 3 and 4, respectively. 5 is a channel device, and an input/output device (I/O) 6 is connected to the channel device 5.

Processors 1, 2 and channel device 5 access memory 8 via common bus 7. Here, in FIG. 2, REQ1 is a memory access request signal of processor 1, REQ2 is a memory access request signal of processor 2, REQC is a memory access request signal of channel device 5, and LOCK is a memory access request signal of other processors 1 and 2. This is a signal to be suppressed.

When processor 1 reads a block, REQ
1 is output continuously to perform memory access, and at the same time, a LOCK signal is output to the processor 2. Even if processor 2 outputs memory access request REQ2 during block read from processor 1,
Since the OCK signal is input, memory access is inhibited.

Therefore, while processor 1 is reading a block, the semaphore bit is not cleared by memory write by processor 2. Therefore, even if the processor 1 performs a block read of the semaphore area, the consistency between the contents of the cache and the contents of the memory is guaranteed. On the other hand, since the LOCK signal is not input to the channel device 5, the channel device 5
When REQC is output from the processor 1, the memory access of the channel device 5 is performed in the middle even when the processor 1 is reading a block.

[0019] Since the memory access request of the channel device is always prioritized in this way, even I/Os 6 with short allowable overrun times can be connected. In addition, exclusive control between the channel device 5 and the processors 1 and 2 does not use a semaphore area, so the problem unlike the exclusive control between the processors 1 and 2 does not occur. That is, the channel device 5 connects the I/O 6 to the memory 8.
The memory area for data transfer to processors 1 and 2 is always
It is impossible to write to the semaphore area because it is limited to the area specified by the control program (operating system).

However, if the area written by the channel device 5 hits the caches 3 and 4 of each of the processors 1 and 2, the caches 3 and 4 must of course be invalidated. Naturally, the invalidation area at this time is a different area from the area where the block is being read. Next, the processor 1,
The internal configuration of 2 is shown in FIG. In FIG. 3, 11 is a main memory interface controller, and 12 is a monitoring directory (WatchingD) that monitors writes by other processors 1, 2 or DMA to main memory areas registered in the directories of its own caches 3, 4.
irectory).

13 is an address bus in the main memory interface, 14 is a data bus in the main memory interface, 15 is the directory memory (tag memory) of the own caches 3 and 4, and 16 is the cache 3
, 4 are buffer memories, 17 is an MPU, 18 is an address register, 19 is a data register, 20 is an address bus, 21 is a data bus, 22 is a hit signal, 23 is a hit number holding register, and the contents of the first stage are is the second
What is held in the stage, 24 is a register for holding the buffer memory address, and the contents of the first stage are stored in the second stage.
It is something that is held on stage.

The address of the address register 18 is stored in the buffer memory address holding register 24 and the tag memory 1.
5 and main memory interface controller 11
and if there is a read hit, cache 3
, 4 is stored in the data register 19. Also, in case of a mis-hit,
A miss signal is applied from the tag memory 15 to the main memory interface controller 11, and then data is stored in the data register 19 from the memory 8 via the data bus 14.

Furthermore, when the memory write address from the channel device 5 hits the caches 3 and 4 of the processors 1 and 2, an invalidation signal (INVL) is sent to the tag memory 15 from the monitoring directory 12 of the main memory interface controller 1. The output and address-set data are invalidated. The MPU 17 is a processor 1,
2 is a miss, and during the block read from the memory 8, there is a memory access request from the channel device 5 during the inhibiting means 17A for suppressing access by other processors 1 and 2, and during the block read. It has a function as a priority means 17B that prioritizes the request.

The main memory interface controller 11 also functions as an invalidating means 11A for invalidating the data set in the address when the memory write address from the channel device 5 hits the caches 3 and 4 of the processors 1 and 2. have Next, the operation will be explained.

FIG. 4 is a time chart for explaining the operation. In FIG. 4, CLK is a synchronization clock that synchronizes the entire system, REQ1, 2, REQC, LOC.
K and INVL are the aforementioned signals, TAGW is the tag write timing signal for caches 3 and 4, MAB, MDB
are each of the aforementioned buses, A1-1 is the address of the first read when processor 1 reads a block, A1-2 is the address of the second read when processor 1 reads block, and A1-3 is the address of processor 1 when reading the block. A1-4 is the address of the fourth read when processor 1 reads a block, A2 is the write address of processor 2, and AC is the write address of channel device 5. .

D1-1 is the first read data of the block read by the processor 1, D1-2 is the second read data of the block read by the processor 1, D1-3
is the third read data of the block read by processor 1, D1-4 is the fourth read data of the block read by processor 1, DC is the write data of channel device 5, and D2-1 is the write data of processor 2. be.

Here, the processor 1 transmits the LOCK signal to τ
By sending the data to the processor 2 for a period of 2 to τ5, the processor 2 is prevented from interrupting and accessing the memory. However, overrun of the I/O 6 is prevented by allowing the channel device 5 to access the memory at τ4. Further, at τ4, an INVL signal is sent to the tag memory 15, and the data for which the address has been set is invalidated. Therefore, the next cache read of the same area will result in a miss, and the processor 1 can read the data in the memory 8 again.

In this way, the common bus 7 can be used efficiently without causing logical contradictions, and I/Os 6 with a short allowable overrun time can also be connected. Next, FIGS. 5 and 6 are diagrams showing a second embodiment of the present invention. In FIG. 5, the MPU 17 has caches 3 and 4.
setting means 17C for setting the tag write timing when reading the first word of a block read;
Alternatively, when there is a memory access request from the channel device 5, it functions as a priority means 17D that gives priority to the request.

Furthermore, when a memory write address from another processor 1, 2 or channel device 5 hits the cache 3, 4 during a block read, the main memory interface controller 11 invalidates the data set in the address. It has a function as means 11B. Note that in this embodiment, processors 1 and 2
The LOCK signal within is not used.

Next, the operation will be explained using the time chart shown in FIG. The symbols in FIG. 6 have the same meanings as in the previous embodiment. The TAGW signal is set by the MPU 17 to be turned on when reading the first word of a block read. By timing the tag write when reading a block at the same time as sending the address of the first read, even if the memory area from which the block was read is written in the next cycle by processor 2's memory write, the write will be performed immediately. By performing validation, the data read from subsequent blocks can be invalidated, and the next cache read from the same area will result in a miss, and the first data in memory 8, that is, the processor 2
The data written by can be read.

In this way, cache 3 and memory 8
Data inconsistency can be prevented. In other words, by performing tag write using τ2, processor 2 writes using τ3.
Even if the block read area of processor 1 is hit by a memory write of , an invalidation (IN
VL=1) invalidates the block read cache 3, so the next time the processor 1 accesses the same area, there will be a miss in the cache 3, so it will read the data in the memory 8 again. By (τ
9 to τ12), does not cause logical contradiction.

[0032] In this embodiment as well, the same effects as in the previous embodiment can be obtained. Next, FIGS. 7 and 8 are diagrams showing a third embodiment of the present invention. In FIG. 7, MPU
In addition to the second embodiment, reference numeral 17 has a function as a stop means 17E for stopping reading of the remaining words of the block read when the data for which the address has been set is invalidated.

Next, FIG. 8 shows a time chart of this embodiment. The symbols in FIG. 8 have the same meanings as in the previous embodiment. During a block read by processor 1, if the address written by processor 2 hits the block being read by processor 1, that block is invalidated and the remaining words of the subsequent block read by processor 1 are invalidated. Abort and move on to the next operation.

If the block read area is a semaphore area, the semaphore bit is "1" at the first read, so the same area is read again, but the address transmission for this is not performed after the previous block read is stopped. , immediately after τ5. That is, since invalidation was performed at τ3, block reading after τ5 is stopped, and a new block read is started again from τ6.

[0035] In this embodiment as well, the same effects as in the previous embodiment can be obtained.

[0036]

As described above, according to the present invention, a common bus can be used efficiently without causing logical contradictions, and system performance can be improved. Furthermore, I/Os with a short allowable overrun time can also be connected, and system applicability can be improved.

[Brief explanation of the drawing]

[Fig. 1] Diagram explaining the principle of the present invention

FIG. 2 is a diagram showing an information processing device according to the first embodiment of the present invention.

[Figure 3] Internal configuration diagram of processor

[Figure 4] Time chart for explaining operation

[Figure 5]
A diagram showing a processor according to a second embodiment of the present invention

[Figure 6]
Time chart to explain operation

FIG. 7 is a diagram showing a processor according to a third embodiment of the present invention.

[Figure 8] Time chart for explaining operation

[Explanation of symbols]

1, 2: Processor 3, 4: Cache 5: Channel device 6: Input/output device (I/O) 7: Common bus 8: Memory 11: Main memory interface controller 11A
, 11B: Invalidation means 12: Monitoring directory 13: Address bus 14: Data bus 15: Directory memory (tag memory) 16: Buffer memory 17: MPU 17A: Suppression means 17B, 17D: Priority means 17C: Setting means 17E: Cancellation means 18: Address register 19: Data register 20: Address bus 21: Data bus 22: Hit signal 23: Register for holding hit number

Claims (3)

[Claims] Claim 1: Information processing in which a plurality of processors (1), (2) having caches (3), (4) and a channel device (5) access a memory (8) via a common bus (7). In the apparatus, the processors (1), (2)
A suppressing means (17A) for suppressing access by other processors (1) and (2) during a block read from the memory (8) when the memory read of the block is a mishit, 5) Priority means for giving priority to memory access requests from
17B) and invalidation means for invalidating the data set in the address when the memory write address from the channel device (5) at that time hits the caches (3) and (4) of the processors (1) and (2). A block read control method characterized by providing (11A) and performing block read. Claim 2: Information processing in which a plurality of processors (1), (2) having caches (3), (4) and a channel device (5) access a memory (8) via a common bus (7). In the device, the caches (3) and (4)
a setting means (17C) for setting the tag write timing when reading the first word of a block read; and a setting means (17C) for setting the timing of the tag write from the memory (8) when the memory read of the processors (1) and (2) is a miss. while the other processors (1), (2) or the channel device (5)
A priority means (17D) for prioritizing a memory access request when there is a memory access request from the other processor (17D);
1), (2) or the cache (3) where the memory write address from the channel device (5) is being read from the block.
(4) A block read control method characterized in that when a hit occurs, an invalidation means (11B) is provided to invalidate the data set in the address, and the block read is performed. 3. A stop means (17E) is provided for stopping the reading of the remaining words of the block read when the data set in the address is invalidated, so that the block read of the same area is performed again after the block read is stopped. The block read control method according to claim 2, characterized in that: