JPH04259026A - Disk array controller - Google Patents

Abstract

PURPOSE:To improve the data transfer efficiency of a disk array controller containing a check function by attaining the parallel transfer of data between a host computer and the disk drives. CONSTITUTION:The write data transferred from a host computer 1 or the data react out of the disk drives D0-D2 are stored in the buffer memories BM0-BM2. If these data are necessary for generation of the check data, the check flags are set to the flag registers FR0-FR2. Meanwhile the user flags are set to the registers FR0-FR2 with the user data. A host I/F 7 or the disks I/F 8a-8c transfer the data stored in the memories BM0-BM2 based on the user flags and also transfer the check data to a check disk drive D3 or the computer 1 based on the check flags.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array control device having a function of checking data recorded on a plurality of disk drives.

0002

2. Description of the Related Art Conventionally, a disk array device includes a plurality of disk drives D0 to D3 (four in this example) and a shared controller 2, as shown in FIG. The controller 2 controls each disk drive D0 to D3.
, and constitutes an interface between each disk drive D0 to D3 and the host computer.

By the way, a normal disk array device is
One of the plurality of disk drives D0 to D3 is used as a check disk drive D3, and has an error check function (ECC function) using check data such as parity data or checksum data. The controller 2 generates check data using write data or read data (hereinafter collectively referred to as user data) other than the check data CD.

As shown in FIG. 5, logical sector addresses 0-11 are set for each recording medium of each disk drive D0-D2 for user data, in addition to physical sectors 0-3. The controller 2 generates check data corresponding to each data in the same physical sector written to each disk drive D0 to D2, and stores it in the same physical sector of the check disk drive D3. Specifically, for example, each disk drive D0 to D2 in physical sector 0
The total sum of each data (3 bytes) in the same byte position is calculated, and this checksum data (CD012) is stored as check data CD in the same byte position in the same physical sector of the drive D3. By using this check data CD, when one of the disk drives D0 to D2 fails, it is possible to restore the data recorded in the failed drive.

By the way, the controller 2 includes a DMA controller for transferring user data and check data to the host computer or each disk drive. This DMA controller executes the transfer of user data to and from the host computer and the transfer of user data and check data to each disk drive.

[0006]

In a conventional disk array device, a DMA controller executes the transfer of user data to and from a host computer and the transfer of user data and check data to each disk drive. In this case, if the transfer of new user data from the host computer and the transfer of user data and check data to each disk drive can be executed in parallel, it is possible to improve the efficiency of data transfer. However, simply controlling data transfer using a DMA controller may cause inconveniences such as, for example, if the check data to each disk drive is transferred before the data transfer from the host computer, the check data written to the disk drive becomes invalid. Occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a disk array control device that is capable of parallelizing each data transfer between a host computer and a disk drive in a disk array device having a check function, and is capable of improving data transfer efficiency. It is about providing.

[0008]

[Means for Solving the Problems] The present invention provides a disk array control device for controlling each of a check disk drive for storing check data and a plurality of disk drives for storing write data such as user data. Buffer memory means for storing each write data transferred from the computer or data read from each disk drive for each disk drive, and check data generation means for generating check data based on each data stored in the buffer memory means. , stores a check flag that is set when each data necessary for check data generation processing by the check data generation means is stored in the buffer memory means, and stores write data or read data for each disk drive in the buffer memory means. a flag storage means for storing a user flag that is set when the user's flag is set; and data stored in the buffer memory means is transferred to each disk drive or host computer based on the user flag stored in the flag storage means; The apparatus includes data transfer control means for transferring check data generated by check data generation means to a check disk drive or host computer based on check flags stored in flag storage means.

[0009]

[Operation] In the present invention, when write data transferred from the host computer or data read from each disk drive is stored in the buffer memory means, if the data is necessary for check data generation processing,
A check flag is set in the flag storage means. Further, in the case of other user data, a user flag is set in the flag storage means. The data transfer control means transfers the data stored in the buffer memory means to each disk drive or host computer based on the user flag stored in the flag storage means, and based on the check flag stored in the flag storage means. The check data generated by the check data generation means is transferred to the check disk drive or host computer.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a disk array system according to an embodiment of the present invention. This system includes a host computer 1, a controller 12, and a plurality of disk drives (four in this case) D0 to D.
Consists of 3. The disk drives D0 to D3 include a check disk drive D3 for storing check data CD and disk drives D0 to D2 for storing user data UD other than check data.

The controller 12 has a data bus 9;
Through this data bus 9, the disk interface (
I/F) 8a to 8d. Each disk I/
F8a to 8d are connected to the corresponding disk drives D0 to D3, respectively, and each disk drive D0
This is a circuit for transmitting commands etc. to ~D3 and receiving status etc.

The data bus 9 includes a plurality of transceivers (
Data transmitting/receiving devices T) 5a to 5e are connected. Each transceiver 5a to 5e transfers data between the data bus 9, buffer memories BM0 to BMn-1, and host interface (I/F) 7, respectively. The host I/F 7 is an interface with the host computer 1, and is a circuit for receiving commands and the like from the host computer 1 and transmitting status and the like.

Each buffer memory BM0 to BMn-1 stores write data transferred from the host computer 1 through the host I/F 7. In addition, each buffer memory BM0 to BMn-1 is connected to each disk I/F8a to BMn-1.
8d to store read data transferred from each disk drive D0 to D3. However, in this embodiment, since it is assumed that there are four disk drives D0 to D3, a description of the case where the buffer memory BMn-1 and the transceiver 5e are used will be omitted.

Furthermore, the controller 12 of the same embodiment has the following features:
It has a plurality of flag registers FR0 to FRn-1 corresponding to each buffer memory BM0 to BMn-1, respectively. Each flag register FR0 to FR2 is a register for storing a check flag CF and a user flag UF. As with the buffer memory BMn-1, the flag register FRn-1 is not used in this embodiment. Each flag register FR0 to FR2 is connected to a flag bus 10.

The controller 12 also has a check data generation circuit 6. The check data generation circuit 6 includes each buffer memory BM0 to BM2 (buffer memory BMn).
Check data is generated based on each data stored in (excluding -1).

The controller 12 includes a CPU 8 and a memory 11 for controlling the entire controller 12. The memory 11 consists of RAM and ROM, and the CPU
8 programs and various control data are stored.

Here, each disk I/F 8a to 8d is connected to a flag bus 10, and data transfer to each disk drive D0 to D3 is performed based on flag information stored in each corresponding flag register FR0 to FR2. It has a control function (DMA controller). Further, the host I/F 7 is connected to the flag bus 10, and has a function (DMA controller) for controlling data transfer to the host computer 1 based on flag information stored in each flag register FR0 to FR2.

Next, the operation of this embodiment will be explained.

First, write data (user data) transferred in response to a write command from the host computer 1 is stored in each of the buffer memories BM0 to BM2. Furthermore, read data (user data) read from each of the disk drives D0 to D2 by the read command is also stored in each of the buffer memories BM0 to BM2. Such user data is stored in the host I/F 7 or each disk I/F.
DMA is performed independently by each DMA controller of 8a to 8d.
be transferred.

[0021] Host I/F 7 and each disk I/F 8
a to 8d are flag registers FR0 to FR2, respectively.
The flag information stored in the buffer memories BM0 to BM2 is checked, and DMA transfer is executed based on the data state (write or read) of each buffer memory BM0 to BM2. That is, when data is stored in each buffer memory BM0-BM2, flag information (check flag CF and user flag UF) is set (logic level "1") in each flag register FR0-FR2. On the other hand, each buffer memory BM0
~ When data is read from BM2, the flag information is reset (logic level "0"). In other words, when the flag information is set, the data write operation to each buffer memory BM0 to BM2 is in a standby state, and after the flag information is reset, data is stored in each buffer memory BM0 to BM2. .

[0022] In such basic operations, various operation modes will be specifically explained.

When the host computer 1 simultaneously writes data to consecutive data sectors (logical sector addresses) of three disk drives D0 to D2,
Each buffer memory BM0-BM2 is allocated to each disk drive D0-D2. That is, FIG. 2(A)
As shown in FIG. 2, when the write data of each data sector (n-1 to n+1) is simultaneously transferred from the host computer 1, it is stored in each buffer memory BM0 to BM2 corresponding to each disk drive D0 to D2. This results in
Write data of disk drive D0 (sector n-1)
is stored in the buffer memory BM0, the write data (sector n) of the drive D1 is stored in the buffer memory BM1, and the write data (sector n+1) of the drive D2 is stored in the buffer memory BM0.
) is stored in the buffer memory BM2.

[0024] Here, when the write command is transferred from the host computer 1, the CPU 8
A write command for each disk drive D0-D2 is output to ~8d. At this time, the CPU 8 uses the host I/F
7 and each disk I/F 8a to 8d, pointers and the like in the DMA transfer operation are initialized. Host I/F7
When write data is transferred from the host computer 1, each buffer memory BM is transferred as shown in FIG. 2(A).
Store write data in 0 to BM2. At this time, if the user flag UF of each flag register FR0 to FR2 is set, the data write operation to each buffer memory BM0 to BM2 is in a standby state.

The host I/F 7 sends the user flag U to each flag register FR0 to FR2 via the flag bus 10.
Set F. Furthermore, since the write data is used for check data generation processing, the host I/F 7 sets a check flag CF in each of the flag registers FR0 to FR2. Such an operation is executed, for example, every time one word of write data is transferred.

[0026] Each disk I/F 8a to 8c controls the state of the user flag UF in each flag register FR0 to FR2 (
set), each buffer memory BM0 to BM2
The write data is read from and transferred to each corresponding disk drive D0 to D2 (see FIG. 2(B)).
. When each disk I/F 8a to 8c transfers data to each disk drive D0 to D2, each flag register F
Reset the user flags UF of R0 to FR2.

On the other hand, the disk I/F 8d monitors the check flag CF of each flag register FR0 to FR2, and when all the flags CF are set, the write data is transferred from each buffer memory BM0 to BM2 to the check data generation circuit. 6 (see FIG. 2(C)). The check data generation circuit 6 includes each buffer memory BM0 to BM2.
Generate check data based on each data stored in . The disk I/F 8d transfers the check data CD from the check data generation circuit 6 to the check disk drive D3, and resets the check flag CF of each flag register FR0 to FR2. At this time, during the check data generation process, each transceiver 5a to 5d connected to the data bus 9 is all turned off.

Next, when data is updated only for one sector, it is necessary to generate new check data CD necessary for that sector. For example, Figure 3
As shown in (D), when only the sector of the disk drive D1 is updated, the host I/F 7 transfers the write data from the host computer 1 to the buffer memory BM1.
Store in. At this time, the host I/F 7 sends the user flag U to the flag register FR1 via the flag bus 10.
F and check flag CF are set. If the user flag UF of the flag register FR1 is already set, the data write operation to the buffer memory BM1 is in a standby state.

[0029] The disk I/F 8b has a flag register F.
Based on the state (set) of the user flag UF of R1, write data is read from the buffer memory BM1 and transferred to the corresponding disk drive D1 (see FIG. 3(E)). As a result of this transfer, the disk I/F 8b resets the user flag UF in the flag register FR1.

On the other hand, the disk I/F 8a reads old data from the disk drive D0 and stores it in the buffer memory BM.
Store at 0. This old data is the write data of the old sector (n-1) which is the same physical sector as the updated sector (new n) and forms the check data group. Since the old data stored in this buffer memory BM0 is used for the check data generation process, the disk I/F8
a sets the check flag CF in the flag register FR0. Further, the disk I/F 8d reads the old check data CD corresponding to the sector to be updated from the check disk drive D3, and reads out the old check data CD corresponding to the sector to be updated from the check disk drive D3, and
Store in. At this time, the disk I/F 8d sets a check flag CF in the flag register FR2. Here, check flag CF of flag register FR2
If has already been set, the data write operation to the buffer memory BM2 will be in a standby state.

The disk I/F 8d monitors the check flags CF of each flag register FR0 to FR2, and when all flags CF are set, each buffer memory BM
Data from 0 to BM2 is output to the check data generation circuit 6 (see FIG. 3(F)). The check data generation circuit 6 generates check data based on each data stored in each buffer memory BM0 to BM2. In this case, for example, in the case of a parity check method, the check data generation circuit 6 may perform an exclusive OR operation on each data. The disk I/F 8d transfers the new check data CD from the check data generation circuit 6 to the check disk drive D3, and registers each flag register FR0 to F.
Reset check flag CF of R2.

In this embodiment, the check data group is a write data group belonging to a data sector (logical sector) corresponding to the same physical sector of each disk drive D0 to D2. That is, a check operation (for example, a parity operation) is performed based on each write data (logical sectors 0 to 2) corresponding to physical sector 0, and the check data CD0
Generate 12. Similarly, as shown in FIG.
901 is generated. Each generated check data is written to the same physical sector of the check disk drive D3 corresponding to the group.

Next, when a read command is transferred from the host computer 1, the CPU 8 uses each disk I/F 8a to
8d and the host I/F 7 to prepare for a DMA transfer operation. At this time, each transceiver 5a to 5d
are all enabled. Each disk I/F8a~
8c transfers the data of the logical sector address specified by the host computer 1 to each corresponding disk drive D0.
~D2 and stored in each buffer memory BM0~BM2 (see FIG. 4(G)). Each disk I/F8a
-8c sets a user flag UF in each flag register FR0-FR2 via the flag bus 10 when DMA transfer is performed to each buffer memory BM0-BM2. Here, if the user flag UF of each flag register FR0 to FR2 is set, each buffer memory BM
The write operation of read data to 0 to BM2 is in a standby state.

[0034] The host I/F 7 has each flag register FR.
Based on user flags UF 0 to FR2, read data is read from each buffer memory BM0 to BM2 and transferred to the host computer 1 in the order of logical sector addresses (see FIG. 4(H)). When the host I/F7 transfers read data by DMA, each flag register FR0 to F
Reset the user flag UF of R2.

Here, if an error occurs during execution of a read command, the CPU 8 transfers all read data of the same check data group to each corresponding disk drive D0.
~Execute control to read from D2. As a result, each disk I/F 8a to 8c reads data at the specified logical sector address from each corresponding disk drive D0 to D2, and stores it in each buffer memory BM0 to BM2 (see FIG. 4(I)). . At this time, each buffer memory B
Each read data stored in M0 to BM2 is used for check data generation processing, so each disk I/F8
A to 8c set a check flag CF in each flag register FR0 to FR2.

[0036] The host I/F 7 has each flag register FR.
When all the check flags CF of 0 to FR2 are set, each read data is outputted from each buffer memory BM0 to BM2 to the check data generation circuit 6 (FIG. 4(J)
). The check data generation circuit 6 generates check data based on each data stored in each buffer memory BM0 to BM2. The host I/F 7 transfers the check data from the check data generation circuit 6 to the host computer 1.

In this way, buffer memories BM0 to BM2 are provided for each disk drive belonging to the check data group (same logical sector), and flag registers FR0 to FR0 corresponding to each buffer memory BM0 to BM2 are provided.
FR2 is provided. Each of these buffer memories BM0 to BM2
By using the flag registers FR0 to FR2, it is possible to transfer effective data to the host computer 1 or each of the disk drives D0 to D2 in parallel. That is, based on the user flag UF, write data or read data is transferred from each buffer memory BM0 to BM2 to the host computer 1 or each disk drive D0 to D2. Further, check data is generated from the data stored in each buffer memory BM0 to BM2 based on the check flag CF. Therefore, for example, when data is updated, it is possible to reliably prevent a situation where invalid check data is generated and transferred.

[0038]

As described in detail above, according to the present invention, in a disk array control device having a function of generating check data from user data, new user data can be transferred from a host computer, and user data can be transferred to each disk drive. Transfer of data and check data can be executed in parallel. Furthermore, it is possible to reliably prevent a situation where invalid data is transferred. Therefore, data transfer efficiency can be improved without reducing reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a disk array control device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram for explaining the operation of the embodiment.

FIG. 3 is a conceptual diagram for explaining the operation of the embodiment.

FIG. 4 is a conceptual diagram for explaining the operation of the embodiment.

FIG. 5 is a block diagram for explaining a conventional disk array device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...Host computer, 6...Check data generation circuit, 12...Controller, BM0-BM2...Buffer memory, FR0-FR2...Flag register, D0-D3...Disk drive.

Claims (2)

[Claims] 1. A disk array control device that controls a plurality of disk drives and controls data transfer between each disk drive and a host computer, comprising:
A check disk drive for storing check data of each write data recorded in each disk drive among the plurality of disk drives, and each write data transferred from the host computer or read from each disk drive. buffer memory means for storing data stored in each disk drive; check data generation means for generating the check data based on the data stored in the buffer memory means; and check data generated by the check data generation means. A check flag is stored when each data necessary for generation processing is stored in the buffer memory means, and is set when write data or read data for each disk drive is stored in the buffer memory means. a flag storage means for storing a user flag stored in the flag storage means; and transmitting data stored in the buffer memory means to each of the disk drives or the host computer based on the user flag stored in the flag storage means; and data transfer control means for transferring the check data generated by the check data generation means to the check disk drive or the host computer based on the check flag stored in the flag storage means. Characteristic disk array control device. 2. A disk array control device that controls a plurality of disk drives and controls data transfer between each disk drive and a host computer, comprising:
A check disk drive for storing check data of each write data recorded in each disk drive among the plurality of disk drives, and each write data transferred from the host computer or read from each disk drive. buffer memory means for storing data stored in each disk drive; check data generation means for generating the check data based on the data stored in the buffer memory means; and check data generated by the check data generation means. A check flag is stored when each data necessary for generation processing is stored in the buffer memory means, and is set when write data or read data for each disk drive is stored in the buffer memory means. a flag storage means for storing a user flag stored in the flag storage means; and transmitting data stored in the buffer memory means to each of the disk drives or the host computer based on the user flag stored in the flag storage means; At the time of this transfer, the user flag of the flag storage means is reset, and the check data generated by the check data generation means based on the check flag stored in the flag storage means is transferred to the check disk drive. or data transfer control means for transferring data to the host computer and resetting the check flag in the flag storage means at the time of the data transfer.