JPH04255008A - Power supply circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of oscillation in the case of driving an LCD by constituting this power supply circuit so as to obtain a required through rate even when large load capacity is applied to an output. CONSTITUTION:The power supply circuit is constituted of an operational amplifier 7a connecting its non-inverted input to an input terminal 9a, an operational amplifier 7b connecting its non-inverted input to an input terminal 9b, inverters 6a, 6b for respectively inputting the outputs of the amplifiers 7a, 7b, and transistors(TRs) Q4, Q5. In the steady states of input voltages V1, V2 and an output voltage V0, V1>V0>V2 is formed. In this case, the outputs of the amplifiers 7a, 7b are respectively low and high levels and both the TRs 4, 5 are cut off. In respect to DC, current consumption is only an idling current flowing into the amplifiers 7a, 7b.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to power supply circuits, and in particular to L
The present invention relates to a power supply circuit for a CD drive.

0002

[Prior Art] A conventional power supply circuit, as shown in FIG.
The operational amplifier 7C is used as a voltage follower, and when the input impedance of the input terminal 9C is high, the operational amplifier 7C converts the impedance so that the output terminal 3 can be driven with low impedance.

The operational amplifier 7C has its (+) input connected to the input terminal 9C, and its (-) input connected to the output terminal 3.

0004

[Problems to be Solved by the Invention] In the conventional power supply circuit described above, when a large load capacity is attached to the output, for example,
When driving a CD, oscillation is likely to occur, and in order to prevent this, the phase compensation capacitor 8 must be made larger, resulting in a deterioration of the slew rate.

That is, in order to obtain the desired slew rate,
There was a drawback that the idling current of the operational amplifier 7C had to be increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply circuit which solves the above-mentioned drawbacks and allows a desired slew rate to be obtained without increasing the idling current.

[0007]

[Means for Solving the Problems] The configuration of the power supply circuit of the present invention includes a first operational amplifier having a first input terminal connected to a non-inverting input, and a first operational amplifier having a second input terminal connected to a non-inverting input. 2
an operational amplifier, a series body of first and second transistors, an output terminal connected to a common connection point of the series body, and an output terminal of the first operational amplifier and a gate of the second transistor. a first inverter connected between the output terminal of the second operational amplifier and a second inverter connected between the output terminal of the second operational amplifier and the gate of the first transistor; It is characterized in that it is connected to the inverting input of the second operational amplifier.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing a power supply circuit according to an embodiment of the present invention. In FIG. 1, the power supply circuit of this embodiment includes a first operational amplifier 7a whose first input terminal 9a is connected to a non-inverting (+) input, and a first operational amplifier 7a whose second input terminal 9b is connected to a non-inverting input. a first inverter 6a that receives the output of the first operational amplifier 7a; a second inverter 6b that receives the output of the second operational amplifier 7b; An N-channel transistor 5 has a gate connected to the output of the inverter 6a and a source connected to the first power supply terminal 2, and an N-channel transistor 5 whose gate has the output of the second inverter 6b connected to the second power supply terminal 1. and a P-channel transistor whose source is connected to the
The drains of the P and N channel transistors 4 and 5 and the inversion of the first and second operational amplifiers 7a and 7b (
-) characterized in that the input is connected to the output terminal 3;

Non-inverting (+) input terminal 9 of operational amplifier 7a
The input voltage of a is set to V1, and the non-inverting (+
) The input voltage at the input terminal 9b is set to V2, the output voltage at the output terminal 3 is set to V0, and ΔV=V1-V2.

In the steady state, the relationship V1>V0>V2 is established, the output of the operational amplifier 7a is low level, the output of the operational amplifier 7b is high level, and both the Pch transistor 4 and the Nch transistor 5 are cut off. are doing. From a direct current perspective, the current consumption is the operational amplifier 7a,
Only the idling current flows through 7b.

Next, regarding the stability of the operation of this embodiment,
As shown in FIG. 2, the delay time of the operational amplifier 7b is tpd
1. When the delay time of the inverter 6b is tpd2, it can be guaranteed as long as the relationship t1-t2>tpd1+tpd2 is satisfied. Also, an offset voltage is generated at the output terminal 3 by the maximum ΔV, but t1-t2>>tpd1+
With tpd2, ΔV can be made small, and the offset voltage can be kept small.

0012

As described above, the present invention has the advantage that even when a large load capacity is attached to the output, a desired slew rate can be obtained without increasing current consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a power supply circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the operating state of FIG. 1;

FIG. 3 is a circuit diagram showing a conventional power supply circuit.

[Explanation of symbols]

1, 2 Power terminal 3 Output terminal 4 Pch transistor 5 Nch transistor 6a, 6b Inverter 7a, 7b, 7c Operational amplifier 8 Capacitor 9a, 9b, 9c Input terminal

Claims (1)

[Claims] Claim 1: A first operational amplifier having a first input terminal connected to a non-inverting input, a second operational amplifier having a second input terminal connected to a non-inverting input, and first and second transistors. a series body, an output terminal connected to a common connection point of the series body, a first inverter connected between the output of the first operational amplifier and the gate of the second transistor, and the a second inverter connected between the output of the second operational amplifier and the gate of the first transistor, the output terminal being connected to the inverting inputs of the first and second operational amplifiers; A power supply circuit featuring: