JPH04236537A - Data communication system - Google Patents

Abstract

PURPOSE:To attain economical data communication by connecting a master and a slave equipment with a couple of data and address buses in parallel and designating and selecting the slave equipment and a data address from the address bus for the communication. CONSTITUTION:A bus from a CPU is selected by a transmission data selection circuit 11 and a transmission data is sent to a reception data selection circuit 12 via a bi-directional buffer 21, a bus is selected and the data is sent to the CPU. An FF circuit 31 and an 8-bit counter 32 generate a control signal and an address. An output Q1 of the counter 32 masks a change point of a selection signal and an address signal. An output Q2 of the counter 32 is a read/write signal. Outputs Q3-Q5 of the counter 32 select one of slave equipments 21-28. Outputs Q6-Q8 of the counter 32 designate a data address. Thus, the equipments 21-28 in parallel bus connection are sequentially selected by a selection signal and transmission reception is implemented by the designation by the address signal, then the slave equipment is connected to a master equipment 1 by a couple of signal lines.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system. Specifically, the present invention relates to a data communication method in which a master device is connected to a plurality of slave devices, and the master device sequentially selects the plurality of slave devices to exchange information.

For example, when a master device exchanges information with a plurality of slave devices, the number of signal lines connecting the master device and the plurality of slave devices increases. As the number of connectors increases, the scale of the master device increases.

On the other hand, from the viewpoint of power saving and space saving, there is a demand for miniaturization of the device.

0004

2. Description of the Related Art FIG. 5 is a block diagram illustrating a conventional example, in which 1a indicates a master device, and 21a to 2Na indicate slave devices.

In the conventional connection between the master device 1a and the slave devices 21a to 2Na, a pair of address buses and data buses are assigned to each of the slave devices 21a to 2Na.

[0006] The master device 1a is connected to the slave devices 21a~
Select one of the 2Na, specify the address, and exchange information.

[0007]

In the conventional example described above, the master device 1a has slave devices 21a to 2N.
As many address buses and data buses as the number of slave devices 21a to 2Na are connected, as the number of slave devices 21a to 2Na increases, the number of signal lines increases, and the number of connectors for connecting them also increases. Therefore, the scale of the master device 1a increases. Also, depending on the type of LSI used in the input/output section, there is a limit to the number of signal lines that can be accommodated, and if the number of signal lines from the slave devices 21a to 2Na exceeds the limit, information exchange This results in a slave device that cannot be used.

The present invention aims to realize an economical data communication system by reducing the number of signal lines connected to a master device and realizing a small and inexpensive master device.

[0009]

Means for Solving the Problems FIG. 1 is a block diagram illustrating the principle of the present invention. 10 in the figure is a data selection means for selecting one of the plurality of buses connected to the processing device in order to communicate with the plurality of slave devices 21 to 2N, and 20 is the data selection means 10 and the plurality of buses. It is a data input/output means that controls the input/output of data between the slave devices 21 to 2N, and 30 is a device address that designates one of the plurality of slave devices 21 to 2N to communicate with, and data to be sent and received. The master device 1 and a plurality of slave devices 21 to 2N are connected in parallel via a bus, and the control signal generation means 30 is a control signal generation means for generating data addresses and control signals in the device. An economical data communication method can be obtained by performing data communication by specifying a device address that specifies one of the slave devices 21 to 2N and its data address.

0010

[Operation] Master device 1 and multiple slave devices 21 to 2
N in parallel with a pair of data buses and address buses.

The control signal generating means 30 generates a device address for selecting one of the plurality of slave devices 21 to 2N for data communication, specifies the slave device for data communication by the device address, and further controls the slave device. By transmitting and receiving data in the area specified by the data address generated by the signal generating means 30, it is possible to realize an economical data communication system.

0012

Embodiment FIG. 2 is a diagram illustrating a master device according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a system configuration according to an embodiment of the present invention.

The embodiment shown in FIG. 2 includes a transmission data selection circuit 11 and a reception data selection circuit 12 as the data selection means 10 explained in FIG. 1, a bidirectional buffer 21 as the data input/output means 20, and a control signal generation means. As 30,
This example is composed of a flip-flop circuit (hereinafter referred to as FF circuit) 31 and an 8-bit counter 32.

1 in FIG. 3 is a master device, 21 to 28 are slave devices, and the slave devices are an example of eight devices. Slave devices 21 to 28 are connected in parallel to a data bus and an address bus. The transmission data is selected by the transmission data selection circuit 11 from a bus connected to the CPU (not shown) and is transmitted through the bidirectional buffer 21, and the reception data is sent to the reception data selection circuit 12 through the bidirectional buffer 21 and connected to the bus. Select and send the received data to the CPU.

FIG. 4 is a time chart of an embodiment of the present invention, showing the operation of generating control signals and addresses by the FF circuit 31 and the 8-bit counter 32. ■Indicates the master clock.

(2) This is a signal outputted from the 21 frequency-divided output Q1 of the 8-bit counter using the inverted output of the master clock, and is an enable signal for masking the change points of the selection signal and address signal.

■ 22 frequency divided output Q2 of the 8-bit counter, read/write signal (shown as R/W signal in the figure) ■ 23, 24, 25 frequency divided outputs Q3, Q4, Q5 of the 8 bit counter be.

(2) A selection signal for selecting one of the slave devices 21 to 28 generated from Q3, Q4, and Q5. ■ 8-bit counter 26, 27, 2
8 divided outputs Q6, Q7, and Q8.

(2) This is an address signal that specifies a data address generated from Q6, Q7, and Q8. Through the above operation, the slave devices 21 to 2 connected in parallel with the bus
By sequentially selecting N with the selection signal ■ and transmitting/receiving the data address of the selected slave device by specifying the address signal ■, the number of signal lines connected to the master device 1 is reduced to only one pair of data bus and address bus. It can be done.

In this embodiment, the data address is 8 from 0 to 7.
However, if the data address is 9 or more, this can be easily handled by increasing the number of bits of the 8-bit counter 32.

Furthermore, the amount of data transmitted from the slave devices 21 to 28 is not constant and generally varies depending on the device. Therefore, the address must have a number of bits that can specify the data area of the slave device with the largest amount of data.

[0022] At this time, if there is a slave device whose data amount is less than half of the maximum address, when that device transmits data, it ignores the most significant bit of the address bit, thereby reducing the number of data transmissions by 2. For example, when fault information is being sent and received, it becomes possible to quickly detect the occurrence of a fault.

[0023]

According to the present invention, a master device and a plurality of slave devices are connected in parallel using a pair of data buses and address buses, and slave devices and data addresses for information exchange are designated and selected from the address bus. An economical data communication method can be obtained by performing communication using the following methods.

[Brief explanation of the drawing]

[Figure 1] Block diagram explaining the principle of the present invention

[Figure 2
] A diagram illustrating a master device according to an embodiment of the present invention.

[Figure 3
] Diagram explaining the system configuration of an embodiment of the present invention

[Figure 4] Time chart of the embodiment of the present invention

[Figure 5]
Block diagram explaining conventional example

[Explanation of symbols]

1, 1a Master device 21 to 28, 21 a to 2N a Slave device 10 Data selection means 11 Transmission data selection circuit 12 Reception data selection circuit 20 Data input/output means 21 Bidirectional buffer 30 Control signal generation means
31 FF circuit 32 8-bit counter

Claims (2)

[Claims] 1. A communication method when a master device (1) performs data communication with a plurality of slave devices (21 to 2N), wherein the plurality of slave devices (21 to 2N)
) data selection means (10) for selecting one of a plurality of buses connected to the processing device; and said data selection means (10) and said plurality of slave devices (
21 to 2N), a device address for specifying one of the plurality of slave devices (21 to 2N) for communication, and a data input/output means (20) for controlling data input/output between the slave devices (21 to 2N), and a device address for specifying one of the plurality of slave devices (21 to 2N) for communication; control signal generating means (30) for generating data addresses and control signals in the data device;
), the master device (1) and the plurality of slave devices (21 to 2N) are connected in parallel via a bus, and the plurality of slave devices (21 to 2N) perform data communication by the control signal generating means (30). A data communication method characterized in that communication is performed by specifying a device address that specifies one of .about.2N) and its data address. 2. The plurality of slave devices (21 to 2
N) If the number of addresses in the area that stores data is less than half of the area that can be specified by data addresses, the number of data transmissions can be doubled by ignoring the most significant bit of the data address. The data communication system according to claim 1, characterized in that: