JPH04234161A - Semiconductor device provided with doubly doped channel stop layer its manufacture - Google Patents

Abstract

PURPOSE: To reduce a substrate resistance and to improve latch-up resistance, by providing a second channel stop layer where a first impurity is doped higher than the first impurity concentration of a first channel stop layer in a semicon ductor substrate in contact with the lower surface of a field oxide film layer away from an element formation region in side direction by a certain distance. CONSTITUTION: A highly concentrated P<++> second channel stop layer 8 is formed in a semiconductor substrate 1 in contact with the lower surface of a field oxide film 3 in the element separation region of an NMOS semiconductor device, where the second channel stop layer 8 is formed away from the element region by a specific distance, for example, approximately 2-4μm. Also the impurity concentration of the second channel stop layer 8 is at least approximately 10<2> times larger than the impurity concentration of the first channel stop layer 2 of P<+> .

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a double-doped channel stop layer and a method for manufacturing the same.

0002

2. Description of the Related Art In recent years, semiconductor memory chips, such as DRAM devices, have entered the mega era with the progress of fine semiconductor manufacturing technology. 4M DRAM devices have entered the mass production stage.
The 16M DRAM element has also completed its research stage and is now in production trial production, and 64M and 256M DRAM elements are also being actively researched.

[0003] The DRAM elements of this mega era are MOS
This has been achieved through transistor miniaturization technology. M.O.
Although the size of the element is rapidly being reduced by miniaturization technology for S transistors, the electric field strength inside the element is increasing because the power supply voltage is constant. This increase in field strength has an adverse effect on the bias characteristics of the device, posing various problems. That is, a decrease in threshold voltage, a punchthrough phenomenon, and a hot carrier (
hot carrier) effect and a decrease in latch-up strength.

In an NMOS semiconductor device, carriers in the channel of a MOS transistor are accelerated by a high voltage near the drain, and when the energy exceeds the energy barrier between silicon and the gate oxide film, they become hot carriers, and these hot carriers have an impact Ionization generates new electron-hole pairs, and most of the newly generated electrons are sucked into the drain by the drain's electric field, but some become hot electrons (an avalanche) and are injected into the gate oxide film. Change the threshold voltage or reduce the transconductance. On the other hand, holes flow within the substrate to form a substrate current, and this substrate current lowers the drain breakdown voltage.

In a CMOS semiconductor device, a parasitic pnpn thyristor circuit is inevitably formed.
With the miniaturization of S semiconductor devices, latch-up has become a major problem, and the distance between the NMOS and PMOS transistors that exist across the well boundary is shrinking as the size of the well boundary decreases. Alternatively, a technology that increases latch-up resistance is required.

In order to understand the present invention, conventional NMOS and CMOS semiconductor devices will be explained with reference to FIGS. 1 and 2.

FIG. 1 shows a conventional single doped locos (lo
cos) is a schematic cross-sectional view of an NMOS semiconductor device having a channel stop layer formed by element isolation. In FIG. 1, the NMOS semiconductor device has an element formation region A, an element isolation region I, and a substrate contact region C in a silicon semiconductor substrate 1 doped with a first impurity, that is, a P-type impurity. A thick field oxide film layer 3 is provided on the semiconductor substrate 1 in the element isolation region I, and a P+ first channel stop layer 2 is provided in the semiconductor substrate 1 in contact with the lower surface of the field oxide film layer 3. The semiconductor substrate 1 in the element formation region or active region A has an N+ source diffusion layer 4b and a drain diffusion layer 4a, and these drain and source diffusion layers 4
A gate electrode layer 5 made of polycrystalline silicon, metal silicide, or a laminated structure thereof is provided on the channel region 4c between the gate electrodes 4b and 4b, and is electrically insulated from the channel region 4c by a gate oxide film. The substrate contact region C has a P++ ohmic contact diffusion layer 6 in the semiconductor substrate 1. Usually, the semiconductor substrate 1 is 1015 to 1016/c
The first channel stop layer 2 contains P-type impurities at a concentration of m3, and the surface peak concentration of the P-type impurities is about 10 times higher than the impurity concentration of the semiconductor substrate 1 at a depth of about 1 μm.
It has a P-type impurity concentration of about 16 to 1017/cm3.

In such an NMOS semiconductor device, the ground voltage Vss is connected to the source diffusion layer 4b, and the drain voltage VD from the ground voltage Vss to the supply voltage Vcc is applied to the drain diffusion layer 4a depending on the operating state, thereby establishing a substrate ohmic contact. A ground voltage or substrate bias voltage VBB is applied to the diffusion layer 6 . Normally, in a DRAM chip, a negative substrate bias voltage VBB of about -2V is applied, and a gate voltage VG between 0V and Vcc is applied to the gate electrode layer 5.

When the drain voltage VD is applied and maintained at a high voltage, the depletion region 7 shown in FIG. 1 is formed, and hot carriers are generated by the high electric field in the depletion region 7 near the drain diffusion layer 4a, causing substrate ohmic A substrate current IB flows through the contact diffusion layer 6. As the gate voltage VG increases, this substrate current IB initially increases due to the increase in channel current, but after a certain point it approaches triode operation, the electric field near the drain weakens, and the impact ionization rate decreases. Therefore, the substrate current IB no longer increases. Therefore, the substrate current IB reaches its maximum when the gate voltage VG becomes approximately 1/2 VD of the drain voltage VD. The resistance of channel stop layer 2 is R
2 and the resistance of the substrate 1 is R1, the substrate current IB is (
1) Determined from Eq.

0010

[Math 1]

That is, the voltage VN at node N is VN=VBB
When the substrate current IB becomes +RB·IB and the substrate current IB increases under a high operating voltage, RB·IB increases and a case where VN>0 occurs. As a result, the N+P diode between the source diffusion layer 4b of the MOS transistor and the substrate 1 is biased in the forward direction, so that electrons are injected from the ground into the semiconductor substrate 1. This phenomenon of electron injection into the semiconductor substrate 1 deteriorates cell refresh characteristics of a DRAM chip. On the other hand, when the voltage VN at node N becomes higher than the substrate bias voltage VBB during chip operation, N
The threshold voltage of the MOS transistor is lowered and the overall circuit operating characteristics are changed, resulting in malfunction.

Therefore, in the MOS transistor, the substrate current I
Even if B occurs, the voltage drop RB can be reduced by reducing the bulk resistance RB up to the substrate ohmic contact diffusion layer 6.
Since IB can be reduced, the malfunction can be prevented and device performance can be significantly improved.

Conventionally, in order to reduce the bulk resistance RB, the P-type impurity concentration of the semiconductor substrate 1 is increased, the P-type impurity concentration of the first channel stop layer 2 is increased, or the semiconductor substrate 1 is A method has been proposed in which a low concentration P-type epitaxial layer with a thickness of about 3 to 6 μm is grown and used on a high concentration wafer of approximately 10 19 /cm 3 or more. This epitaxial growth method requires advanced epitaxial growth technology, which has the disadvantage of increasing manufacturing costs, and when increasing the concentration of the semiconductor substrate, there is a body effect that causes threshold voltage fluctuations due to changes in bulk voltage.
If the concentration of the channel stop layer becomes large and the concentration of the channel stop layer increases, the breakdown of the NMOS transistor may occur.
Disadvantages have been pointed out, such as lowering the voltage and causing deterioration of operating characteristics due to an increase in the voltage of the element.

Next, FIG. 2 shows the conventional single doped Locos (
locos) is a schematic cross-sectional view of a CMOS semiconductor device having a channel stop layer formed by element isolation. This CMOS semiconductor device has 1014 to 1016/
An N-type well 11 doped with a second impurity of about 1016 to 1017/cm3 is formed in a P-type semiconductor substrate 10 doped with a first impurity of about cm3, and a thick field is formed on the semiconductor substrate 10 in the element isolation region. The semiconductor substrate 10 has an oxide film layer 13, a P-type first channel stop layer 12a is provided in the semiconductor substrate 10 in contact with the lower surface of the field oxide film layer 13, and an N-type channel stop layer 12b is provided in the N-type well 11.
has.

There is NM in the semiconductor substrate 10 in the element formation region.
Drain and source diffusion layer 14a of OS transistor
, 14b, and on the channel region 14c between these drain and source diffusion layers 14a and 14b, there is a polycrystalline silicon or metal silicide electrically insulated from the channel region 14c by a gate oxide film, or a layer of these. The gate electrode layer 16 has a laminated structure. In addition, drain and source diffusion layers 15a and 15b of PMOS transistors are provided in the N-type well 11 in the element formation region.
and these drain and source diffusion layers 15a,
A gate electrode layer 17 made of polycrystalline silicon, metal silicide, or a laminated structure thereof is provided on the channel region 15c between the channel region 15b and the gate oxide film. A P++ substrate ohmic contact diffusion layer 18 is provided in the semiconductor substrate 10 in the substrate contact region, and an N++ well ohmic contact diffusion layer 19 is provided in the N type well 11 in the well contact region.

The inverter circuit of such a CMOS semiconductor device usually connects the drain diffusion layers 14a and 15a of the NMOS and PMOS transistors in common to generate the output voltage Vo.
ut and input voltage Vi to the gate electrode layers 16 and 17.
n is applied in common. Then, a supply voltage Vcc is commonly applied to the source diffusion layer 15b of the PMOS transistor and the N++ well ohmic contact diffusion layer 19 in the N-type well 11.
b is connected to the ground voltage Vss. In addition, the P++ substrate ohmic contact diffusion layer 18 of the semiconductor substrate 10 has −2
A negative voltage of about V or a substrate bias voltage VBB of 0 V is applied.

Such a CMOS inverter circuit structure has a parasitic thyristor circuit as shown in FIG. 2, and the sustaining current IH of this parasitic thyristor circuit is
It can be expressed as in equation (2) using the NP transistor and the horizontal NPN transistor current amplification factors βp and βn, the substrate resistance RB, and the well resistance RW.

[0018]

[Math 2]

As shown in equation (2), it is effective to lower the current amplification factor of the parasitic bipolar transistor and to lower the substrate resistance and well resistance in order to increase the latch-up resistance. However, simple element size scaling increases these values and reduces latch-up strength.

Therefore, in conventional CMOS semiconductor devices, the double well method is used to reduce the substrate resistance RB in order to improve latch-up resistance, and the junction capacitance and substrate bias effect are affected by increasing the concentration deep from the well surface. A high-acceleration ion implantation method, an epitaxial wafer method, a trench isolation method, and the like have been disclosed to lower the well resistance without changing the concentration near the surface, which affects the well resistance. However, the double-well method only reduces substrate resistance and has a limit in improving latch-up resistance, while the high-acceleration ion implantation method only reduces well resistance and requires high-acceleration ion implantation. The epitaxial wafer method has the disadvantage of increasing costs, and the epitaxial wafer method has the disadvantage of increasing wafer costs.
The trench isolation method requires a complicated trench formation process, and it has been pointed out that there are problems such as defects occurring in the silicon substrate during trench formation, and leakage current caused by the defects.

[0021]

SUMMARY OF THE INVENTION In order to solve the problems of the prior art as described above, the present invention provides an NMOS semiconductor device having a double-doped channel stop layer for reducing substrate resistance. It is.

Another object of the present invention is to provide a CMOS semiconductor device having a double-doped channel stop layer to improve latch-up resistance.

Another object of the present invention is to provide an optimal manufacturing method for manufacturing the semiconductor device.

[0024]

[Means for Solving the Problems] The above object is to form a thick field oxide film layer as an element isolation region for defining an element formation region and a substrate contact region on a semiconductor substrate doped with a first impurity. on the semiconductor substrate;
a first channel stop layer doped with a first impurity higher than the first impurity concentration of the semiconductor substrate in the semiconductor substrate in contact with the lower surface of the field oxide film layer; A second channel stop layer doped with a first impurity at a higher concentration than the first impurity concentration of the first channel stop layer is provided in the semiconductor substrate at a distance and in contact with the lower surface of the field oxide layer. This is achieved by a semiconductor device characterized by comprising a double-doped channel stop layer for reducing bulk resistance within the semiconductor substrate.

Further, in the present invention, the certain distance between the second channel stop layer and the element formation region is such a distance that the depression region formed in the element formation region does not reach the second channel stop layer. This is a semiconductor device characterized by the following.

Further, the present invention is a semiconductor device characterized in that the impurity concentration of the second channel stop layer is about 10 2 to 10 4 times the impurity concentration of the first channel stop layer.

[0027] In the present invention, the semiconductor substrate has 1015 to 10
The first channel stop layer is a P-type silicon substrate having an impurity concentration of about 17/cm3, the first channel stop layer has an impurity concentration three times or more that of the silicon substrate, and the second channel stop layer has an impurity concentration of about 17/cm3. A semiconductor device characterized in that the semiconductor substrate has an impurity concentration of about 1015 to 1017/cm3, and the first channel stop layer is an N-type silicon substrate having an impurity concentration of about 1015 to 1017/cm3. The semiconductor device is characterized in that the second channel stop layer has an impurity concentration three times or more higher than that of the substrate, and the second channel stop layer has an impurity concentration ten times or more higher than that of the first channel stop layer.

Furthermore, the above object is to form a well (Wel) of a second conductivity type doped with a second impurity different from the first impurity in a semiconductor substrate of the first conductivity type doped with a first impurity.
l), an element isolation region for defining an element formation region and a substrate contact region in the semiconductor substrate, and a thick film which is an element isolation region for defining an element formation region and a well contact region in the well. - a field oxide film layer on the semiconductor substrate of the first conductivity type and on the well of the second conductivity type in the semiconductor substrate; a first channel stop layer of a first conductivity type doped with a first impurity at a higher concentration than the first impurity concentration of the semiconductor substrate; In a semiconductor device having a first channel stop layer of a second conductivity type doped with a second impurity higher than a second impurity concentration of the well in a shaped well, a first conductivity type portion of the semiconductor substrate is A first impurity concentration higher than the first impurity concentration of the first channel stop layer of the first conductivity type is formed in the semiconductor substrate at a certain distance laterally from the element formation region and in contact with the lower surface of the field oxide film layer. a doped second channel stop layer of the first conductivity type; and a lower surface of the field oxide film layer on the well, spaced a certain distance laterally from the element formation region of the well of the second conductivity type; further comprising a second channel stop layer of a second conductivity type doped with a second impurity higher than the second impurity concentration of the first channel stop layer of the second conductivity type in the well in contact with the well; This is achieved by a semiconductor device characterized in that it comprises a double-doped channel stop layer for reducing the bulk resistance in the semiconductor substrate and the well resistance of the well.

Further, the present invention provides a semiconductor substrate doped with the first impurity with a thick field oxide film layer as an element isolation region for defining an element formation region and a substrate contact region. a first channel stop layer doped with a first impurity higher than the first impurity concentration of the semiconductor substrate in the semiconductor substrate in contact with the lower surface of the field oxide layer; a second channel doped with a first impurity at a higher concentration than the first impurity concentration of the first channel stop layer in the semiconductor substrate, spaced a certain distance laterally from the region and in contact with the lower surface of the field oxide layer; In a method of manufacturing a semiconductor device having a stop layer and a double-doped channel stop layer for reducing bulk resistance in the semiconductor substrate, a pad is provided on the semiconductor substrate doped with the first impurity. A pad nitride film is sequentially laminated on the oxide film, the pad nitride film is etched to form a pad nitride film pattern, and the pad nitride film pattern is used as a mask to form a pattern on the semiconductor substrate in the element isolation region. A first layer for forming the first channel stop layer on the inner surface of the cloth.
a step of implanting impurity ions, then, after the ion implantation step, a step of growing a pad oxide film in the element isolation region by thermal oxidation to form the field oxide film layer; and a step of forming the field oxide film layer. After that, the pad nitride film pattern
covering the device formation region and a portion of the adjacent field oxide layer with photoresist, and using the photoresist as a mask to form a mask in the semiconductor substrate under the field oxide layer and in the substrate contact region. a step of implanting first impurity ions for forming the second channel stop layer into the semiconductor substrate; after the ion implantation step, activating the second channel stop layer and forming a normal MOS transistor in the element formation region; A semiconductor device characterized by comprising a step of forming an element using a manufacturing method.

[0030]

[Operation] The semiconductor device of the present invention has a silicon substrate resistance and a P+
Since the resistance of the highly doped second channel stop layer is connected in parallel with the resistance of the first channel stop layer, the bulk resistance can be reduced. This can prevent malfunctions of the NMOS semiconductor device due to hot carrier effects and strengthen the latch-up resistance of the CMOS semiconductor device.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

The present invention will be described with reference to FIGS. 3 to 9.

Example 1 An NMOS semiconductor device according to an example of the present invention shown in FIG.
Semiconductor substrate 1 in contact with the lower surface of field oxide film layer 3 in the element isolation region in the conventional NMOS semiconductor device of FIG.
There is another high-concentration P++ second channel stop layer 8 therein. This second channel stop layer 8 is formed at a predetermined distance, for example, about 2 to 4 μm, from the element formation region. This predetermined distance is such a distance that the depletion region does not reach the second channel stop layer when a reverse bias is applied to the NMOS transistor. That is,
It is sufficient to maintain a distance that does not reduce the breakdown voltage of the NMOS transistor. Other structures are shown in Figure 1.
Since it is the same as the conventional semiconductor device, it will be treated with the same reference numeral.

When the impurity concentration of the P+ first channel stop layer 2 is 1016 to 1017/cm3, the impurity concentration of the high concentration second channel stop layer 8 is about 102 times or more, preferably about 102 to 104 times. (peak concentration 1018-1021/cm3).

Therefore, the bulk resistance RB is significantly reduced because the resistance of the highly doped second channel stop layer is connected in parallel with the parallel resistance of the silicon substrate resistance and the resistance of the P+ first channel stop layer. Ru.

Embodiment 2 An NMOS semiconductor device according to another embodiment of the present invention shown in FIG. 4 has a second channel stop layer 8a of high concentration P++ in the substrate contact region, as compared with the semiconductor device of Embodiment 1 shown in FIG. The difference is that the structure is directly connected to the substrate ohmic contact diffusion layer 6. The other structures are the same as those of the semiconductor devices in FIGS. 1 and 3, and therefore are designated by the same reference numerals.

Embodiment 3 The manufacturing process of the semiconductor device of Embodiment 2 shown in FIG. 4 will be described with reference to FIGS. 5 to 8.

First, referring to FIG. 5, 1015 to 101
7/cm3 of P-type impurities, such as boron ions (B+
) on a doped silicon substrate 1 with a thickness of about 20-50 mm
A pad oxide film 20 with a thickness of about 100 nm is thermally grown in an oxygen atmosphere, and a nitride film Si3N4 is deposited on top of it by a normal CVD method.
A pad nitride film pattern 21 for defining device isolation regions is formed by depositing Si3N4 to a thickness of about 100 to 150 nm and etching the Si3N4 using a conventional photolithography method. Next, using the pad nitride film pattern 21 as a mask, about 30 to 35K is applied near the surface of the semiconductor substrate in the element isolation region.
Boron ions (B+) of 1017 to 1019/cm3 are implanted at an energy of eV.

Referring to FIG. 9, after the ion implantation process, a thermal oxide film having a thickness of about 300 to 500 nm is formed on the pad oxide film 20 at a temperature of about 900 to 1000°C. Then, a field oxide film layer 3 is formed on the semiconductor substrate 1 in the element isolation region, and the implanted ions are activated in the semiconductor substrate in contact with the lower surface of the field oxide film layer 3, and the first channel stop layer 2 is formed. It is formed. Then, the pad nitride film pattern 21 is removed by a conventional wet strip method or selective etching using CDE. This process is based on the so-called LOCOS element separation method.

Next, referring to FIG. 7, the present invention applies a photoresist 22 to a device forming area by a conventional photolithography method.
Boron ions of approximately 1014 to 1016/cm2 (
By ion-implanting B+), an ion-implanted layer for forming a high concentration second channel stop layer 8a having a peak concentration of 1018 to 1021/cm3 is formed in the semiconductor substrate 1 under the field oxide film layer 3. be done. At this time, the ion implantation layer formed in the semiconductor substrate in the substrate contact region is formed deeper than the ion implantation layer formed in the semiconductor substrate 1 under the field oxide film 3 in the element isolation region.

Referring to FIG. 8, after activating the ion implantation layer to form a highly doped second channel stop layer 8a, an NMOS transistor is formed in the element formation region using a normal NMOS semiconductor manufacturing process, and the substrate is A substrate ohmic contact diffusion layer 6 is formed in the semiconductor substrate 1 in the contact region to complete the process.

In this NMOS semiconductor manufacturing process, the breakdown voltage of the source and drain of the NMOS transistor depends on the impurity concentration of the semiconductor substrate 1 and the channel stop layer 2.
impurity concentration, drain and source diffusion layers 4a, 4b
Since these concentrations can be optimized, the highly doped second channel stop layer is determined by the impurity concentration profile of It is sufficient to maintain a sufficient distance between the highly doped second channel stop layer 8a and the drain and source diffusion layers 4a and 4b in the element formation region, to the extent that the second channel stop layer 8a does not reach the second channel stop layer 8a. For example, in a semiconductor device having a 1.0 μm design rule, the impurity concentration of the first channel stop layer 2 is 1016
~1017/cm3, the width of the depletion region is about 1.5 μm or less under the reverse bias condition of about 10V, so the high concentration second channel stop layer 8a and the drain and source diffusion layers 4a and 4b in the element formation region are If the spacing is maintained at 2 μm or more, the breakdown voltage and basic device characteristics of the NMOS transistor will not be affected at all by forming the highly doped second channel stop layer 8a. Therefore, most of the element isolation region that occupies a wide area of the semiconductor device is covered with the highly doped second channel stop layer 8.
When connected to each other, the bulk resistance RB can be reduced by about 1/10 to 1/100 compared to the conventional semiconductor device shown in FIG.

Embodiment 4 In the above embodiments, an NMOS semiconductor device has been described, but the second channel stop layer can be formed in a similar manner in a PMOS semiconductor device.

That is, in a PMOS semiconductor device, 300
In the case of a field oxide film layer with a thickness of about nm, phosphorus ions (P+) are generated at high energy of about 300 KeV or more.
In actual processes, the double charge ion implantation method of phosphorus ions, which is commonly used, may be used to implant the phosphorus ions at an acceleration voltage of about 150 KeV. If the field oxide film is thicker than this, or if high-energy ion implantation is not performed, a highly concentrated second channel stop layer is formed using a photoresist using a conventional photolithography method before forming the field oxide film layer. After performing ion implantation, a field oxide film layer may be formed.

Example 5 FIG. 9 is a schematic cross-sectional structural diagram of a CMOS semiconductor device having a double-doped channel stop layer according to the present invention.

The CMOS semiconductor device of FIG. 9 according to the present invention is the conventional CMOS semiconductor device of FIG.
This device differs from the S semiconductor device in that it further includes second channel stop layers 30a and 30b of the first and second conductivity types with high concentration. The rest of the structure is the same as in FIG. 2, so the same reference numerals are used.

A P++ second channel stop layer 30a is formed in the P type semiconductor substrate 10, and an N++ second channel stop layer 30b is formed in the N well 11. Therefore, since the substrate resistance RB and the well resistance RW can be reduced at the same time, the latch-up resistance can be greatly improved.

In FIG. 9, the highly doped second channel stop layer 3
0a and 30b are P++ and N++ layers, respectively, which form reverse biased diodes, so if the spacing between them is narrow, the high concentration P++ layer and N++ layer will be adjacent to each other, and the gap between the well and the substrate will be reduced. Breakdown voltage is lower. Therefore, the second channel stop layers 30a, 3 with high concentration
0b is also preferably maintained at a distance greater than a certain distance.

[0049]

As described above, the CMOS semiconductor device according to the present invention can be manufactured by adding a high concentration ion implantation process for a P++ second channel stop layer and an N++ second channel stop layer to the normal CMOS manufacturing process. .

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional structural diagram of an NMOS semiconductor device with a conventional single-doped channel stop layer.

FIG. 2 is a schematic cross-sectional structural diagram of a CMOS semiconductor device having a conventional single-doped channel stop layer.

FIG. 3 is a schematic cross-sectional structural diagram of an NMOS semiconductor device of Example 1 having a double-doped channel stop layer according to the present invention.

FIG. 4 is a schematic cross-sectional structural diagram of an NMOS semiconductor device of Example 2 having a double-doped channel stop layer according to the present invention.

FIG. 5 is a first schematic cross-sectional structure diagram showing the sequence of manufacturing steps of an NMOS semiconductor device of Example 3 having a double-doped channel stop layer according to the present invention.

FIG. 6 is a second schematic cross-sectional structure diagram showing the sequence of manufacturing steps of the NMOS semiconductor device of Example 3 having a double-doped channel stop layer according to the present invention.

FIG. 7 is a third schematic cross-sectional structure diagram showing the sequence of manufacturing steps of an NMOS semiconductor device of Example 3 having a double-doped channel stop layer according to the present invention.

FIG. 8 is a third schematic cross-sectional structure diagram showing the sequence of manufacturing steps of an NMOS semiconductor device of Example 3 having a double-doped channel stop layer according to the present invention.

FIG. 9 is a schematic cross-sectional structural diagram of a CMOS semiconductor device of Example 5 having a double-doped channel stop layer according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 10... Silicon semiconductor substrate, 2... First channel stop layer, 3, 13... Field oxide film layer, 4a, 14a, 15a... Drain diffusion layer, 4b, 1
4b, 15b...source diffusion layer, 4c, 14c, 15
c... Channel region, 5, 16, 17... Gate electrode layer, 6, 18... Substrate ohmic contact diffusion layer, 7.
...Depression region, 8,8a...Second channel stop layer, 11...Well, 12a...First channel stop layer of first conductivity type, 1
2b...first channel stop layer of second conductivity type, 19
...well ohmic contact diffusion layer, 20...
Pad oxide film, 21... Pad nitride film pattern, 22... Photoresist, 30a... Second channel stop layer of first conductivity type, 3
0b... Second channel stop layer of second conductivity type, A.
...Element formation region, I...Element isolation region, C...Substrate contact region.

Claims (13)

[Claims] 1. A semiconductor substrate doped with a first impurity, having on the semiconductor substrate a thick field oxide film layer serving as an element isolation region for defining an element formation region and a substrate contact region; A semiconductor device including a first channel stop layer doped with a first impurity higher than a first impurity concentration of the semiconductor substrate in the semiconductor substrate in contact with a lower surface of the field oxide film layer. The semiconductor device includes a first impurity containing a first impurity concentration higher than a first impurity concentration of the first channel stop layer in the semiconductor substrate, which is a certain distance laterally from the element formation region and in contact with the lower surface of the field oxide film layer. A semiconductor device comprising a double-doped channel stop layer for reducing bulk resistance within the semiconductor substrate, further comprising a second doped channel stop layer. 2. The certain distance between the second channel stop layer and the element formation region is such a distance that a depression region formed in the element formation region does not reach the second channel stop layer. The semiconductor device according to claim 1, characterized in that: 3. The semiconductor device according to claim 2, wherein the certain distance between the second channel stop layer and the element formation region is approximately 2 μm to 4 μm. 4. The impurity concentration of the second channel stop layer is 102 to 1 of the impurity concentration of the first channel stop layer.
2. The semiconductor device according to claim 1, wherein the semiconductor device is about 0.04 times as large. 5. The semiconductor substrate has a thickness of 1015 to 1017/cm.
It is a P-type silicon substrate with an impurity concentration of about 3,
Claim: wherein the first channel stop layer has an impurity concentration three times or more that of the silicon substrate, and the second channel stop layer has an impurity concentration ten times or more than the first channel stop layer. 1. The semiconductor device according to 1. 6. The semiconductor substrate has a thickness of 1015 to 1017/cm.
It is an N-type silicon substrate with an impurity concentration of about 3,
Claim: wherein the first channel stop layer has an impurity concentration three times or more that of the silicon substrate, and the second channel stop layer has an impurity concentration ten times or more than the first channel stop layer. 1. The semiconductor device according to 1. 7. The semiconductor device according to claim 1, wherein the second channel stop layer is formed continuously within the semiconductor substrate up to the substrate contact region. 8. A semiconductor substrate of a first conductivity type doped with a first impurity includes a well of a second conductivity type doped with a second impurity different from the first impurity. , an element isolation region for defining an element formation region and a substrate contact region in the semiconductor substrate, and a thick field oxide film layer serving as an element isolation region for defining an element formation region and a well contact region in the well. The first conductive layer is provided on the first conductive type semiconductor substrate and on the second conductive type well in the semiconductor substrate, and is in contact with the lower surface of the field oxide film layer.
a first channel stop layer of a first conductivity type doped with a first impurity at a higher concentration than the first impurity concentration of the semiconductor substrate; The first well of the second conductivity type is doped with a second impurity at a higher concentration than the second impurity concentration of the well.
In a semiconductor device having a channel stop layer, a channel stop layer is formed in the semiconductor substrate at a certain distance laterally from the element formation region of the first conductivity type portion of the semiconductor substrate and in contact with the lower surface of the field oxide layer. a second channel stop layer of the first conductivity type doped with a first impurity higher than the first impurity concentration of the first channel stop layer of the first conductivity type; and from the element forming region of the well of the second conductivity type. A second impurity dope having a higher concentration than the second impurity concentration of the first channel stop layer of the second conductivity type is formed in the well at a certain distance in the lateral direction and in contact with the lower surface of the field oxide film layer on the well. The method further includes a double-doped channel stop layer of a second conductivity type to reduce the bulk resistance in the semiconductor substrate and the well resistance of the well. Characteristic semiconductor devices. 9. The semiconductor substrate has a thickness of 1014 to 1016/cm.
It is a P-type silicon substrate with an impurity concentration of about 3,
Claim 8, wherein the well is an N-type well having an impurity concentration of about 1016 to 1017/cm3.
The semiconductor device described in . 10. A semiconductor substrate doped with a first impurity, having a thick field oxide film layer on the semiconductor substrate as an element isolation region for defining an element formation region and a substrate contact region, A first channel stop layer doped with a first impurity higher than the first impurity concentration of the semiconductor substrate is provided in the semiconductor substrate in contact with the lower surface of the field oxide film layer, and the first channel stop layer is doped with a first impurity at a concentration higher than that of the semiconductor substrate, and A second channel stop layer doped with a first impurity at a higher concentration than the first impurity concentration of the first channel stop layer is provided in the semiconductor substrate at a certain distance in the direction and in contact with the lower surface of the field oxide layer. Equipped with
In the method of manufacturing a semiconductor device having a double-doped channel stop layer for reducing bulk resistance in the semiconductor substrate, a pad oxide film is formed on the first impurity-doped semiconductor substrate, and a pad oxide film is formed on the semiconductor substrate doped with the first impurity. Nitride films are sequentially stacked, the pad nitride film is etched to form a pad nitride film pattern, and the pad nitride film pattern is used as a mask to form a pattern near the surface of the semiconductor substrate in the element isolation region. a step of implanting first impurity ions for forming a first channel stop layer, and after the ion implantation step, growing a pad oxide film in the element isolation region by thermal oxidation to form the field oxide film layer. Step: After forming the field oxide layer, removing the pad nitride pattern, covering the device forming area and a part of the adjacent field oxide layer with a photoresist, and using the photoresist as a mask. a step of implanting first impurity ions for forming the second channel stop layer into the semiconductor substrate under the field oxide film layer and into the semiconductor substrate in the substrate contact region; 1. A method for manufacturing a semiconductor device, comprising the steps of activating a second channel stop layer and forming an element in the element formation region by a normal MOS transistor manufacturing method. 11. The ion implantation step for forming the first channel stop layer includes implanting boron ions (B+) at an energy of about 30 to 35 keV to form the first channel stop layer.
11. The method of manufacturing a semiconductor device according to claim 10, wherein an impurity concentration of about 1017/cm3 is maintained. 12. The ion implantation step for forming the second channel stop layer includes implanting boron ions (B+) at an energy of about 140 keV or more to form the second channel stop layer.
12. The method of manufacturing a semiconductor device according to claim 11, wherein a peak impurity concentration of about 1021/cm3 is maintained. 13. The width of the field oxide film layer adjacent to the device formation region covered with the photoresist is about 2 to 4 μm.
13. The method of manufacturing a semiconductor device according to claim 12, wherein