JPH04212776A - Test circuit of semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor memory device, and more particularly to a circuit built into a semiconductor memory device to test whether the semiconductor memory device is normal or not. .

0002

2. Description of the Related Art Dynamic random access memories (hereinafter referred to as DRAMs) have been increasing in density at a rate of four times every three years. Currently, 4 Mbit DRAM is in mass production, and 16 Mbit and even 64 Mbit DRAM are under development. On the other hand, D.R.A.
As the storage capacity of M increases, the time required to test whether the DRAM is normal or not increases significantly, and the resulting increase in product costs has become impossible to ignore. Therefore, bit information is simultaneously written into multiple memory cells of DRAM, the written multiple bit information is read simultaneously, a logical operation is performed on the read bit information at the same time, and the result of the logical operation is output. Semiconductor memory devices now include test circuits that test whether data can be written and read correctly based on values. By using this test circuit, a plurality of memory cells can be tested simultaneously, so the test time can be significantly shortened.

[0003] A DRA with a built-in test circuit as described above
An example of M is shown in FIG. The DRAM shown in FIG. 12 is shown in U.S. Patent No. 4,860,259.
When operating in normal mode, test enable signals TE and /TE are set to L level and H level, respectively, and when operating in test mode, test enable signal T is set to L level and H level, respectively.
Let E and /TE be at H level and L level, respectively.

Various methods have been proposed for switching to the test mode by setting the test enable signals TE and /TE to H level and L level, respectively. /RAS), the row address strobe signal /RAS and column address strobe signal /RAS are activated.
Some devices enter the test mode from the normal mode when the CAS or write enable signal /WE changes. That is, when column address strobe signal /CAS and write enable signal /WE are set to L level before row address strobe signal /RAS falls, the test mode is entered. Note that in the normal mode, both column address strobe signal /CAS and write enable signal /WE are not set to L level before row address strobe signal /RAS falls. At this time, the test enable signal TE output from the clock generator 14 is high.
At the same time, the test enable signal /TE becomes L level.

On the other hand, CBR (/CA) as shown in FIG.
When the row address strobe signal /RAS and column address strobe signal /CAS change at a timing called S before /RAS), the test mode returns to the normal mode. In other words, the write enable signal /WE
is at H level, the row address strobe signal /R
Column address strobe signal /C before AS falls
When AS is set to the L level, the test enable signal TE output from the clock generator 14 becomes the L level, and the test enable signal /TE becomes the H level.

Next, the operation of the semiconductor memory device shown in FIG. 12 will be explained.

(1) Operation in normal mode In the semiconductor memory device shown in FIG. 12, reading and writing are performed in the normal mode as follows.

First, at the time of reading, the address signal Add(
(including row address signals and column address signals) are applied to decoder 1. The decoder 1 decodes, for example, the most significant bit of the row address signal and the most significant bit of the column address signal of the applied address signal Add, and outputs, for example, four on/off control signals. These on/off control signals are transmitted through transistors 4a to 4a.
4d, and these transistors 4a to 4d.
4d is turned on. On the other hand, decoder 1 decodes the remaining row address signals and column address signals and supplies the decoded output to memory cell array 5. Memory cell array 5 includes a plurality of memory cells arranged in a matrix. The memory cell array 5 is divided into a plurality of subarrays, four subarrays 5a to 5d in FIG. 12. Bit information is read out from the corresponding memory cells of each subarray 5a-5d by the decoded output of decoder 1, and is applied to read amplifiers 6a-6d, respectively. As aforementioned,
Only one of the transistors 4a to 4d is in an on state. Therefore, only one of the four bit information read from each subarray 5a-5d is transmitted to node N6 via one of read amplifiers 6a-6d. In the normal mode, as mentioned above, the test enable signal /TE is at H level and the test enable signal T
Since E is at L level, transistor 8 is in the on state.
Transistor 9 is in an off state. Therefore, node N
The bit information transmitted to 6 is outputted to external output pin DO UT via output buffer 7 .

[0009] During writing, the 4 output from decoder 1
Only one of the transistors 2a to 2d is turned on by the two on/off control signals (outputted by decoding the most significant bit of the row address signal and the most significant bit of the column address signal). At this time, since the test enable signal TE is at L level, the transistor 3a
~3d are all off. Therefore, the bit information input from the external input pin DI N is transferred to the input buffer 10 activated by the signal W which becomes H level at the time of writing.
is supplied to one of the subarrays 5a to 5d. On the other hand, in each subarray 5a to 5d, decoder 1
One corresponding memory cell is selected by the decode output supplied from each. Therefore, the bit information is written into the selected memory cell of the sub-array to which the bit information is supplied.

(2) Operation in test mode Furthermore, the semiconductor memory device shown in FIG. 12 operates as follows in test mode.

First, when writing in the test mode, the test enable signal TE goes to H level, so all the transistors 3a to 3d are turned on. Therefore, bit information input from external input pin DI N is supplied to all subarrays 5a to 5d via input buffer 10. In each subarray 5a to 5d, decoder 1
The bit information supplied above is simultaneously written into the memory cells selected by the decoded outputs, that is, the four corresponding memory cells.

At the time of reading, bit information stored in four corresponding memory cells of each sub-array 5a to 5d selected by the decode output of decoder 1 is read out simultaneously. The bit information read from the selected memory cells of each sub-array 5a to 5d is transmitted to a read amplifier 6a.
6d to one input terminal of exclusive OR gates 12a to 12d. The 4-bit information read at this time is information written simultaneously to the corresponding memory cells of each subarray 5a to 5d. On the other hand, expected value data having the same logic as the write data when these 4 bits of information are written is input to the external input pin DI N . This expected value data is supplied to the other input terminal of each of the exclusive OR gates 12a to 12d via the input buffer 11 activated by the signal R which becomes H level during reading. Therefore, if the written information is correctly read, the outputs of exclusive OR gates 12a to 12d all become L level. Exclusive OR gates 12a-1
The output of 2d is further input to an OR gate 13. Therefore, if the written information is correctly read, the output of this OR gate 13 also goes to L level. Here, since the test enable signal /TE is at L level and the test enable signal TE is at H level, transistor 8 is in an off state and transistor 9 is in an on state. Therefore, the output of the OR gate 13 is the external output pin DO
Output to UT. In other words, when the semiconductor memory device is operating normally, the external output pin DOUT is low.
A level signal is output. If each subarray 5a~
If the data of even one of the corresponding memory cells 5d is inverted, the output of at least one of the exclusive OR gates 12a to 12d becomes H level, and the OR gate 1
The output of No. 3 also becomes H level. Therefore, when the semiconductor memory device malfunctions, an H level signal is output to the external output pin DOUT.

As described above, in the test mode, memory operations of multiple bits can be simultaneously tested by determining the level of the output signal of the external output pin DO UT .

However, in the test circuit shown in FIG. 12, only one of the corresponding memory cells in each subarray 5a to 5d is found to be abnormal, and it is difficult to determine which subarray's memory cell has the abnormality. The problem was that it was impossible to judge.

[0015] Therefore, a test circuit capable of solving the above-mentioned problems is disclosed in Japanese Patent Laid-Open No. 63-241791. In the test circuit shown in this publication, the outputs corresponding to the exclusive OR gates 12a to 12d shown in FIG. 12 are input in parallel to a shift register circuit,
The data is temporarily stored and held in each latch circuit that constitutes this shift register circuit. Thereafter, each latch circuit is connected in series and sequentially shifts the stored and held information. The serial output of the shift register circuit is supplied to an external output pin. Therefore, from the external output pin,
The outputs corresponding to the exclusive OR gates 12a to 12d in 2 are serially output.

[0016]

[Problem to be solved by the invention] JP-A-63-2417
In the test circuit disclosed in Japanese Patent No. 91, the test determination result of each subarray is serially outputted from an external output pin, so it is possible to know which subarray has an abnormality in a memory cell. However, in the test circuit disclosed in Japanese Patent Application Laid-Open No. 63-241791, the test judgment results of each subarray must be latched in each latch circuit of the shift register circuit, so the output of the test results is delayed by that amount. There was another problem: Furthermore, in the test circuit disclosed in Japanese Patent Application Laid-Open No. 63-241791, after each latch circuit forming the shift register circuit receives the test judgment result of each subarray, each latch circuit must be connected in series. Must be. Therefore, a switch circuit for switching the connection state must be provided at the input end of each latch circuit. Therefore, there are problems in that the configuration becomes complicated and the operation becomes complicated due to the control of each switch circuit.

Therefore, an object of the present invention is to be able to obtain more detailed test result data from a single output pin, to output test results at high speed, and to have a simple structure that allows complex control operations to be performed. An object of the present invention is to provide a test circuit for a semiconductor memory device that is not required.

[0018]

[Means for Solving the Problems] A test circuit for a semiconductor memory device according to the present invention is a circuit for testing a semiconductor memory device equipped with a memory cell array divided into a plurality of subarrays, and includes a writing means and a memory cell array. , a reading means, a logic operation means, a single output pin, a plurality of switch means, and a switch control means. The writing means writes bit information of the same logic into mutually corresponding memory cells of each subarray. The reading means reads stored information from the memory cells of each sub-array written by the writing means. The logical operation means performs a calculation on the stored information of the memory cells of each sub-array read out by the reading means.
Tests are performed by performing predetermined logical operations on each of them, and the test results are output as multiple-bit parallel data. A single output pin outputs the test result output of the logical operation means to the outside. Each switch means is inserted between each bit of output data of the logic operation means and a single output pin. The switch control means sequentially and selectively turns on each switch means to serially apply the parallel data outputs of the logic operation means to a single output pin.

[0019]

[Operation] In the present invention, each switch means is sequentially and selectively turned on by the switch control means, so that the parallel data output of multiple bits from the logic operation means is
Serially applied to a single output pin.

Therefore, from a single output pin,
It is possible to obtain more detailed test results than those obtained with the conventional semiconductor memory device shown in No. 2. Also,
The output of the logic operation means does not need to be latched by each latch circuit of the shift register circuit as in the test circuit shown in Japanese Patent Application Laid-Open No. 63-241791, so the test results can be output at high speed. It is possible. Further, since a switch circuit for switching the connection state of each latch circuit constituting the shift register circuit is not required, the configuration is simple and the control operation is also simplified.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. The configuration of the embodiment shown in FIG.
The configuration is the same as that of the conventional semiconductor memory device shown in FIG. 12 except for the following points, and corresponding parts are given the same reference numerals and their explanations will be omitted.

The embodiment shown in FIG. 1 differs from the conventional semiconductor memory device shown in FIG. 12 by controlling the on/off of transistors 18a to 18d by the output of the shift register 15 during reading in the test mode. The point is that the outputs of the exclusive OR gates 12a to 12d are serially output to the external output pin DOUT. The shift register 15 is connected to a shift register reset circuit 16.
Its operation is controlled by a shift clock generator 17. The shift register reset circuit 16 operates based on a column address strobe signal /CAS and a row address strobe signal /RAS input from the outside.
A reset signal SRR is generated and supplied to each latch circuit in the shift register 15. Shift clock generator 1
7 generates shift clock signals φ and /φ based on a column address strobe signal /CAS applied from the outside and a test enable signal TE applied from a clock generator 14, and supplies them to a shift register 15. Shift register 15 performs a shift operation in synchronization with shift clock signals φ and /φ applied from shift clock generator 17.

In the embodiment shown in FIG. 1, in the normal mode, the clock generator 14 receives the row address strobe signal/
Based on RAS, column address strobe signal /CAS, and write enable signal /WE, test enable signal TE is set to L level and test enable signal /TE is set to H level, and write and read operations are performed as described in FIG.
This is done in the same manner as in the conventional semiconductor memory device shown in FIG.

On the other hand, in the test mode, the clock generator 14 sets the test enable signal TE to H level based on the row address strobe signal /RAS, column address strobe signal /CAS, and write enable signal /WE. is the L level. At the time of writing in the test mode, each subarray 5a to
Bit information of the same logic is written to the corresponding memory cell of 5d.

The embodiment shown in FIG. 1 reads bit information from the corresponding memory cells of each subarray 5a to 5d during reading in the test mode, similar to the conventional semiconductor memory device shown in FIG. The match/mismatch between the bit information input from the external input pin DI N and the expected value information (information of the same logic as the bit information written to each memory cell selected at that time) is determined by each exclusive logic. The determination is made using the sum gates 12a to 12d. At this time, first, the first output N1 of the shift register 15 goes high.
level, thereby turning on the transistor 18a. Therefore, the output of exclusive OR gate 12a is supplied to transistor 9 via transistor 18a. Next, by a shift operation, the shift register 15
The second output N2 of the transistor 18b becomes H level, thereby turning on the transistor 18b. Therefore, the output of exclusive OR gate 12b is supplied to transistor 9 via transistor 18b. Thereafter, the outputs of the exclusive OR gates 12c and 12d are sequentially supplied to the transistor 9 in the same manner. In the test mode, the test enable signal TE is at H level, so the transistor 9 is in an on state. Therefore, the outputs of the exclusive OR gates 12a to 12d are serially outputted to the external output pin DOUT via the transistor 9.

The shift register 15 is configured as shown in FIG. 2, for example. As shown in FIG. 2, the shift register 15 includes eight ratio type latch circuits L1 to L8, and these latch circuits L1 to L8 are connected in series to each other via transistors 19 to 26. Among these transistors 19 to 26, transistor 19,
A shift clock signal φ is supplied from the shift clock generator 17 to each gate of transistors 21, 23, and 25, and a shift clock signal /φ is supplied from the shift clock generator 17 to each gate of transistors 20, 22, 24, and 26. be done. In addition, even numbered latch circuits L2, L4, L6, L8
The output of inverter IN1, IN2, IN3, IN4
The inverted values are the first to fourth shift registers 15.
As outputs N1 to N4 of transistor 1 in FIG.
It is supplied to gates 8a to 18d. In addition, on the input side of the odd-numbered latch circuits L1, L3, L5, and L7,
One conductive terminal of each of the transistors 40 to 43 to which the reset signal SRR from the shift register reset circuit 16 is supplied is connected to each gate. The other conductive terminal of the transistor 40 connected to the latch circuit L1 is grounded. The other conductive terminals of the transistors 41 to 43 connected to the other latch circuits L3, L5, and L7 are connected to the power supply voltage Vcc.

The shift register reset circuit 16 in FIG. 1 is configured as shown in FIG. 3, for example. As shown in FIG. 3, the shift register reset circuit 16
It includes a flip-flop 46 configured by cross-connecting D gates 44 and 45, AND gates 47 and 48, a delay circuit 49, and an inverter 50. A row address strobe signal /RAS and a column address strobe signal /CAS are input to the AND gate 48. The output of the AND gate 48 is directly applied to one input terminal of the NAND gate 45, and the output is directly applied to the delay circuit 49.
After being delayed by inverter 50, it is inverted by NANA
It is applied to one input terminal of the D gate 44. The output of the NAND gate 45 and the output of the AND gate 48 are applied to the AND gate 47 . The output of the AND gate 47 becomes the output of the shift register reset circuit 16.

In the shift register reset circuit shown in FIG. 3, the output of the NAND gate 44 is at L level, and the NAND
Let us consider the operation when both row address strobe signal /RAS and column address strobe signal /CAS go to H level while the output of ND gate 45 is at H level. In this case, the output of the AND gate 48 becomes H level and is input to the NAND gate 45. However, the H level output of the AND gate 48 is
9 to the inverter 50, the output of the inverter 50 remains at the H level at this time. Therefore, the output of the NAND gate 44 is at L level.
The output of NAND gate 45 remains at H level. Therefore, the AND gate 47 is supplied with H level signals from the NAND gate 45 and the AND gate 48, and the output of the AND gate 47 is at the H level. After that, the output of inverter 50 becomes L level. In response, the output of NAND gate 45 becomes L level, and as a result, the output of AND gate 47 becomes L level. Therefore, when row address strobe signal /RAS and column address strobe signal /CAS go to H level, the output of AND gate 47, that is, the output of shift register reset circuit 16 goes to H level for a predetermined period of time. That is, when row address strobe signal /RAS and column address strobe signal /CAS go to H level, reset signal SRR is activated for a predetermined period of time.

Shift clock generator 17 in FIG. 1 is configured as shown in FIG. 4, for example. The shift clock generator 17 shown in FIG. 4 has an inverter 51 and a NAND
It includes a gate 52 and an inverter 53. NAND
One input terminal of the gate 52 is supplied with a test enable signal TE from the clock generator 14 in FIG. The other input terminal of NAND gate 52 is supplied with an inverted signal of column address strobe signal /CAS from inverter 51 . The output of the NAND gate 52 is
It is supplied as a shift clock signal /φ to the shift register 15 shown in FIGS. 1 and 2. Further, the output of the NAND gate 52 is inverted by an inverter 53 and then supplied as a shift clock signal φ to the shift register 15 shown in FIGS. 1 and 2. In the test mode, the test enable signal TE is at H level, so when column address strobe signal /CAS is at H level, the output of NAND gate 52, that is, shift clock signal /φ goes to H level, and the output of inverter 53, that is, shift clock signal Signal φ becomes L level. Conversely, when column address strobe signal /CAS is at L level, shift clock signal /φ is at L level and shift clock signal φ is at H level.

FIG. 5 is a timing chart showing the operation of the embodiment shown in FIG. 1 in the test mode. FIG. 6 is a timing chart showing more detailed operation of the read operation (portion marked as READ in FIG. 5) in the test mode. Since the feature of the present invention is the read operation in the test mode, this operation will be explained in detail below with reference to the timing charts of FIGS. 5 and 6. As described above, when the column address strobe signal /CAS and the row address strobe signal /RAS both go to H level, the shift register reset circuit 16
The reset signal SRR is set to active level (H level) for a predetermined period of time. Furthermore, when the column address strobe signal /CAS is at the H level, the shift clock generator 17 sets the shift clock signal /φ to the H level and the shift clock signal φ to the L level.
When CAS is at L level, shift clock signal /φ is set to L level.
Assume that the shift clock signal φ is set to H level.

When row address strobe signal /RAS and column address strobe signal /CAS both go to H level, shift register reset circuit 16 sets reset signal SRR to active level (H level) as described above. The activated reset signal SRR is supplied to each gate of transistors 40 to 43 shown in FIG. 2. Therefore, the transistors 40 to 43 are turned on, and an L level signal is supplied to the input side of the latch circuit L1, and an H level signal is supplied to the input sides of the other latch circuits L3, L5, and L7. At this time, column address strobe signal /CAS is at H level, so shift clock signals φ and /φ generated from shift clock generator 17
are at L level and H level, respectively. Therefore, the transistors 20, 22, 24, 26 in FIG.
is in the on state. Therefore, latch circuit L2
, L4, L6, and L8 are latch circuits L1 and L, respectively.
The data held in 3, L5, and L7 is taken in. Therefore, the output of latch circuit L2 becomes L level, and the outputs of latch circuits L4, L6, and L8 become H level. Therefore, the output N1 of the inverter IN1 becomes H level, and the outputs N2 to N4 of the other inverters IN2 to IN4 become L level. Therefore, the transistor 18a in FIG. 1 is turned on.

Next, the row address strobe signal /RA
When S falls to the L level, the row address signal 27 (see FIGS. 5 and 6) is taken into the decoder 1, and when the column address strobe signal /CAS falls to the L level, the column address signal 28 (see FIG. 6) is taken into the decoder 1. 5, see Figure 6)
is taken in.

At this time, in response to the fall of column address strobe signal /CAS, shift clock signal φ goes to H level and /φ goes to L level. Therefore, transistors 19, 21, 23, and 25 in FIG. 2 are turned on, and transistors 20, 22, 24, and 26 are turned off. As a result, the inverted signal of the output of the latch circuit L8, that is, the L level signal, is sent to the output terminal of the latch circuit L1, and the inverted signal of the output of the latch circuit L2, that is, the H level signal is sent to the output terminal of the latch circuit L4. The inverted signal of the output of the latch circuit L, that is, the L level signal
An inverted signal of the output of the latch circuit L6, that is, an L level signal, is latched at the output terminal of the latch circuit L7. At this time, the transistors 20, 22,
Since 24 and 26 are in the off state, inverters IN1 to
There is no change in the outputs N1 to N4 of IN4.

Therefore, the output of the exclusive OR gate 12a, that is, the test judgment result of the selected memory cell in the sub-array 5a, is transmitted to the transistors 18a and 9 (which are turned on because the test enable signal TE is at H level). is output to the external output pin DO UT via the external output pin DOUT. At this time, the test judgment result output to the external output pin DO UT is shown in FIG.
It is designated by reference numeral 30 in FIG.

Next, the column address strobe signal /C
When AS rises to H level, shift clock signal φ
changes to L level and /φ changes to H level, transistors 20, 22, 24, and 26 turn on, and transistors 19, 21, 23, and 25 turn off. Therefore, the inverted signal of the output of the latch circuit L1, that is, the H level signal is applied to the output terminal of the latch circuit L2.
The inverted signal of the output of the latch circuit L5, that is, the L level signal, is sent to the output terminal of the latch circuit L4, the inverted signal of the output of the latch circuit L5, that is, the H level signal is sent to the output terminal of the latch circuit L6, and the inverted signal of the output of the latch circuit L7 is sent to the output terminal of the latch circuit L6. That is, the H level signal is latched at the output terminal of the latch circuit L8. As a result, the output N2 of the inverter IN2 becomes H level, and the outputs N1, N3, N4 of the other inverters IN1, IN3, IN4 become L level. In other words, the H level signal is shifted by one stage. As a result, transistors 18a, 18c, and 18d are turned off, and transistor 18b is turned on. the result,
The output of the exclusive OR gate 12b is output to an external output pin DO UT as indicated by reference numeral 31 in FIGS. 5 and 6. Similarly, each time the column address strobe signal /CAS rises to H level, the outputs of the exclusive OR gates 12c and 12d are sent to the external output pin DOU.
T (reference numerals 32 and 3 in FIGS. 5 and 6)
3).

FIG. 7 is a block diagram showing the configuration of a second embodiment of the present invention. The difference between this second embodiment and the first embodiment shown in FIG. 1 is that, as is clear from FIG. OR gate 12
By inputting the outputs of c and 12d to the OR gate 36, the test judgment results of subarrays 5a and 5b are reduced to one, and the test judgment results of subarrays 5c and 5d are reduced to one. . That is, if there is an abnormality in any memory cell in sub-array 5a or 5b, the output of OR gate 35 becomes H level, and if there is an abnormality in any memory cell in sub-array 5c or 5d,
The output of OR gate 36 becomes H level.

The outputs of the OR gates 35 and 36 connect the transistors 37 and 38 controlled by the outputs N7 and N8 of the shift register 34, the transistor 9 controlled by the test enable signal TE, and the output buffer 7. via the external output pin DO UT .

The shift register 34 in FIG. 7 uses, for example, a two-stage structure as shown in FIG. The rest of the configuration of the embodiment shown in FIG. 7 is the same as that of the embodiment shown in FIG. 1, and corresponding parts are given the same reference numerals and explanations thereof will be omitted.

FIG. 9 is a timing chart showing the read operation in the test mode of the embodiment shown in FIG. As is clear from FIG. 9, the embodiment shown in FIG.
This embodiment basically performs the same operation as the embodiment shown in FIG. 1, except that the number of stages of the shift register is reduced. In FIG. 9, a signal indicated by reference numeral 391 is the test determination result output of subarrays 5a and 5b, and a signal indicated by reference numeral 401
The signals indicated by are the test determination result outputs of subarrays 5c and 5d.

In the embodiment shown in FIG. 7, compared to the embodiment shown in FIG. It is shorter than the embodiment shown in FIG. 1 because the amount of information of the result data is reduced.

FIG. 10 is a block diagram showing the configuration of a third embodiment of the present invention. The embodiment shown in FIG. 10 differs from the embodiment shown in FIG. 1 in the following points. That is, in the embodiment shown in FIG. 10, the outputs of read amplifiers 6a and 6b, that is, the bit information read from subarrays 5a and 5b, are input to exclusive OR gate 135, and the outputs of read amplifiers 6c and 6d, that is, the bit information read from subarrays 5c and 5b, are input to exclusive OR gate 135. The bit information read from 5d is input to exclusive OR gate 136. That is, in the example shown in FIG.
The test is performed by determining whether the logics of the bit information read out at the same time match/mismatch with each other using exclusive OR gates 135 and 136, and no expected value data is used. The outputs of exclusive OR gates 135 and 136 are connected to external output pin DO via transistors 37 and 38 controlled by outputs N7 and N8 of shift register 34, transistor 9 controlled by test enable signal TE, and output buffer 7. UT is supplied. Note that the configuration of the shift register 34 is similar to the configuration of the shift register 34 in FIG. 7, and is configured as shown in FIG. 8, for example. The rest of the configuration of the embodiment shown in FIG. 10 is the same as that of the embodiment shown in FIG. 1, and corresponding parts are given the same reference numerals and their explanations will be omitted.

FIG. 11 is a timing chart showing the read operation in the test mode of the embodiment shown in FIG. As is clear from FIG. 11, the read operation in the test mode of the embodiment shown in FIG. 10 is exactly the same as that of the embodiment shown in FIG. 7, except that the expected value data is not input from the external input pin DI N. It is.

Similar to the embodiment shown in FIG. 7, the embodiment shown in FIG. 10 has a smaller amount of information in the test judgment result data taken out to the outside compared to the embodiment shown in FIG. The time required for reading is shorter than the embodiment shown in FIG. 1 by the amount of information of the test determination result data reduced. Furthermore, in the embodiment shown in FIG. 10, there is no need to input expected value data from the outside in the test mode, so the control in the test mode is simplified.

In the three embodiments described above, the memory cell array is divided into four subarrays, but the number of divisions is not limited to four and can be arbitrarily changed depending on the situation. Further, in each of the above embodiments, the present invention is applied to a DRAM.
The test was applied to, but is not limited to,
It is also applicable to testing semiconductor memory devices other than DRAM.

[0045]

As described above, according to the present invention, a predetermined logical operation is performed on storage information read from a selected memory cell of each sub-array, and the results of the logical operation are serially and serially processed. Since the signal is supplied to one output pin, more detailed test judgment result data can be obtained than in the conventional semiconductor memory device shown in FIG.

Further, in the present invention, when outputting the operation result of the logic operation means, that is, the test judgment result data, each switch means is sequentially and selectively controlled on/off, so that the data can be output directly to a single output pin. Compared to conventional test circuits in which the test judgment result data is once latched in a shift register circuit and then shifted out, the test judgment result data can be output faster and the configuration is simpler. A test circuit with easy control can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a more detailed configuration of the shift register in FIG. 1;

FIG. 3 is a circuit diagram showing a more detailed configuration of the shift register reset circuit in FIG. 1;

FIG. 4 is a circuit diagram showing a more detailed configuration of the shift clock generator in FIG. 1;

FIG. 5 is a timing chart showing the operation of the embodiment shown in FIG. 1 in a test mode.

FIG. 6 is a timing chart showing in more detail the read operation in the test mode of the embodiment shown in FIG. 1;

FIG. 7 is a block diagram showing the configuration of a second embodiment of the invention.

FIG. 8 is a circuit diagram showing a more detailed configuration of the shift register in FIG. 7;

9 is a timing chart showing in detail the read operation in the test mode of the embodiment shown in FIG. 7;

FIG. 10 is a block diagram showing the configuration of a third embodiment of the invention.

FIG. 11 is a timing chart showing in detail the read operation in the test mode of the embodiment shown in FIG. 10;

FIG. 12 is a block diagram showing an example of the configuration of a conventional semiconductor memory device incorporating a test circuit.

13 is a timing chart showing a switching operation from normal mode to test mode in the conventional semiconductor memory device shown in FIG. 12; FIG.

14 is a timing chart showing a switching operation from a test mode to a normal mode in the conventional semiconductor memory device shown in FIG. 12;

[Explanation of symbols]

1 is a decoder, 2a to 2d, 3a to 3d, 4a to 4d are transistors, 5 is a memory cell array, 5a to 5d are subarrays, 12a to 12d, 135, 136 are exclusive OR gates, 18a to 18d, 37, 38 15 and 34 are shift registers, and 17 is a shift clock generator.

Claims (3)

[Claims] 1. A circuit for testing a semiconductor memory device having a memory cell array divided into a plurality of subarrays, the circuit for testing a semiconductor memory device comprising a memory cell array divided into a plurality of subarrays, the circuit for testing a semiconductor memory device, wherein bit information of the same logic is written into mutually corresponding memory cells of each of the subarrays. reading means for reading out stored information from the memory cells of each of the sub-arrays written by the writing means; , a logic operation means for performing a test by performing a predetermined logic operation, and outputting the test result as parallel data of multiple bits, and a single output pin for outputting the test result output of the logic operation means to the outside. , a plurality of switch means interposed between each bit of output data of the logic operation means and the single output pin; and sequentially and selectively turning on each of the switch means, the logic operation means and switch control means for serially applying parallel data outputs of 1 to the single output pin. 2. A test circuit for a semiconductor memory device according to claim 1, wherein said logic operation means outputs said test result output for each of said subarrays. 3. The test circuit for a semiconductor memory device according to claim 1, wherein said logic operation means reduces said test result output to a plurality of numbers smaller than the number of said sub-arrays and outputs the result.