JPH04211998A - Production of semiconductor device and semiconductor device production device - Google Patents
Production of semiconductor device and semiconductor device production deviceInfo
- Publication number
- JPH04211998A JPH04211998A JP3019681A JP1968191A JPH04211998A JP H04211998 A JPH04211998 A JP H04211998A JP 3019681 A JP3019681 A JP 3019681A JP 1968191 A JP1968191 A JP 1968191A JP H04211998 A JPH04211998 A JP H04211998A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- adsorption layer
- magnetic
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75733—Magnetic holding means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Credit Cards Or The Like (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法及
び半導体装置製造装置に係り，特にＩＣチップを基板に
搭載しワイヤボンディング及び封止を行う方法とそのた
めの製造装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus, and more particularly to a method for mounting an IC chip on a substrate and performing wire bonding and sealing, and a manufacturing apparatus therefor.
【０００２】近年，例えばＩＣカード等のＩＣチップを
搭載した製品の普及が著しいなかで，そのコストダウン
が要求されており，そのために生産効率の向上及び不良
率の低減を図ることが必要となってきている。[0002] In recent years, with the rapid spread of products equipped with IC chips such as IC cards, there has been a demand for cost reduction, and for this purpose, it is necessary to improve production efficiency and reduce defective rates. It's coming.
【０００３】0003
【従来の技術】図４はＩＣチップと基板間のワイヤボン
ディングの従来例を示す側面図であり，１は基板，４は
ＩＣチップ，７はワイヤ，１４はテーブル，１５は真空
吸引パスを表す。[Prior Art] Fig. 4 is a side view showing a conventional example of wire bonding between an IC chip and a substrate, in which 1 represents a substrate, 4 represents an IC chip, 7 represents a wire, 14 represents a table, and 15 represents a vacuum suction path. .
【０００４】従来のワイヤボンダのテーブル１４におい
ては，ワイヤボンディングの際，真空吸引により，基板
１をテーブル１４に固定していた。基板１は，例えばパ
ッケージのセラミック基板あるいはプリント基板である
。In the conventional wire bonder table 14, the substrate 1 was fixed to the table 14 by vacuum suction during wire bonding. The substrate 1 is, for example, a ceramic substrate of a package or a printed circuit board.
【０００５】ＩＣチップ４を基板１に搭載するには，銀
ペースト等の接着剤を用いてＩＣチップ４を基板１のス
テージ部に接着した後，接着剤中に含まれている溶剤分
を加熱することにより除去させてＩＣチップ４を固定し
た後，ワイヤボンディング等の配線及び封止作業を行う
ようになっていた。In order to mount the IC chip 4 on the substrate 1, the IC chip 4 is bonded to the stage portion of the substrate 1 using an adhesive such as silver paste, and then the solvent contained in the adhesive is heated. After the IC chip 4 is removed and the IC chip 4 is fixed, wiring such as wire bonding and sealing work are performed.
【０００６】ところが，接着剤中に含まれている溶剤分
を除去して安定した接着力を得るためには十分なキュア
（固化）時間が必要であり，接着剤が完全に固化するま
では配線作業及び封止作業を行うことができず，生産効
率が低下するという問題があった。また，生産効率を向
上するためにキュア時間を短時間にすると，接着強度不
足になるばかりでなく，配線工程において接着剤中の溶
剤分がリードに付着してワイヤ７が接続できなくなった
り，封止工程において溶剤分がガスとなって封止剤に混
入し完全な封止ができなくなったりして，品質が低下す
るという問題があった。However, in order to remove the solvent contained in the adhesive and obtain stable adhesive strength, sufficient curing (hardening) time is required, and wiring cannot be performed until the adhesive is completely solidified. There was a problem in that it was not possible to perform the sealing work and the sealing work, resulting in a decrease in production efficiency. Furthermore, if the curing time is shortened to improve production efficiency, not only will the adhesive strength be insufficient, but the solvent in the adhesive will adhere to the leads during the wiring process, making it impossible to connect the wire 7 or sealing. During the sealing process, the solvent becomes a gas and mixes with the sealant, making it impossible to seal completely, resulting in a reduction in quality.
【０００７】[0007]
【発明が解決しようとする課題】本発明は上記の問題点
を解決するためになされたものであって，その目的は基
板に対してＩＣチップを瞬時に固定して，それに続く配
線及び封止作業を支障なく行うようにし，生産効率の向
上及び不良率の低減を図ることができる製造方法及び製
造装置を提供することにある。[Problems to be Solved by the Invention] The present invention has been made to solve the above problems, and its purpose is to instantly fix an IC chip to a substrate, and then perform wiring and sealing. It is an object of the present invention to provide a manufacturing method and a manufacturing device that allow work to be performed without any hindrance, improve production efficiency, and reduce defective rates.
【０００８】[0008]
【課題を解決するための手段】図１（ａ）， （ｂ）は
，第１の実施例を説明するための断面図であり，図２は
第２の実施例を説明するための断面図である。[Means for Solving the Problem] FIGS. 1(a) and 1(b) are sectional views for explaining a first embodiment, and FIG. 2 is a sectional view for explaining a second embodiment. It is.
【０００９】上記課題は，ＩＣチップ４裏面或いは該Ｉ
Ｃチップ４を搭載する基板１表面の少なくともいずれか
一方に磁性層２を形成し，他方に磁気吸着可能な吸着層
５を形成し，該磁性層２と該吸着層５を突き合わせて該
ＩＣチップ４を該基板１に磁力により固定した後，配線
及び封止を行う半導体装置の製造方法によって解決され
る。[0009] The above problem is that the back side of the IC chip 4 or the
A magnetic layer 2 is formed on at least one of the surfaces of the substrate 1 on which the C chip 4 is mounted, and an adsorption layer 5 capable of magnetic attraction is formed on the other side, and the magnetic layer 2 and the adsorption layer 5 are butted against each other to form the IC chip. The problem is solved by a method of manufacturing a semiconductor device in which wiring and sealing are performed after fixing the semiconductor device 4 to the substrate 1 by magnetic force.
【００１０】また，ＩＣチップ４裏面に磁気吸着可能な
チップ側吸着層１０を形成し， 該ＩＣチップ４を搭載
する基板１表面に磁気吸着可能な基板側吸着層１１を形
成し， 該チップ側吸着層１０と該基板側吸着層１１を
突き合わせて該基板１を電磁石を備えたテーブル１２上
に配置し， 該電磁石により該チップ側吸着層１０と該
基板側吸着層１１に磁力を供給して該ＩＣチップ４を該
基板１に磁力により固定した後，配線及び封止を行う半
導体装置の製造方法によって解決される。Furthermore, a chip-side adsorption layer 10 capable of magnetic attraction is formed on the back surface of the IC chip 4, and a substrate-side adsorption layer 11 capable of magnetic attraction is formed on the surface of the substrate 1 on which the IC chip 4 is mounted. The substrate 1 is placed on a table 12 equipped with an electromagnet with the adsorption layer 10 and the substrate side adsorption layer 11 abutted against each other, and the electromagnet supplies magnetic force to the chip side adsorption layer 10 and the substrate side adsorption layer 11. The problem is solved by a semiconductor device manufacturing method in which wiring and sealing are performed after the IC chip 4 is fixed to the substrate 1 by magnetic force.
【００１１】また，ＩＣチップ４を配置した基板１を搭
載しかつ該ＩＣチップ４に磁力を供給する電磁石を備え
たテーブル１２を有し， 該基板１に該ＩＣチップ４を
ワイヤボンディングする半導体装置製造装置であって，
該テーブル１２は，磁気吸着層１０の形成されたＩＣチ
ップ４と磁気吸着層１１の形成された基板１に磁力を供
給して，該ＩＣチップ４を該基板１に磁力により固定す
る半導体装置製造装置によって解決される。[0011] Furthermore, there is provided a semiconductor device for wire-bonding the IC chip 4 to the substrate 1, which has a table 12 on which a substrate 1 on which an IC chip 4 is arranged and is equipped with an electromagnet for supplying magnetic force to the IC chip 4. A manufacturing device,
The table 12 supplies magnetic force to the IC chip 4 on which the magnetic attraction layer 10 is formed and the substrate 1 on which the magnetic attraction layer 11 is formed, and fixes the IC chip 4 to the substrate 1 by magnetic force. Solved by the device.
【００１２】0012
【作用】ＩＣチップ４は磁力にて基板１に容易に固定さ
れる。即ち，磁力固定であるから，従来の接着剤による
接着法に比べて瞬時に固定される。そして，以後の配線
封止作業が支障なく行われる。[Operation] The IC chip 4 is easily fixed to the substrate 1 by magnetic force. That is, since it is fixed by magnetic force, it is fixed instantly compared to conventional bonding methods using adhesives. Then, the subsequent wiring sealing work can be performed without any problems.
【００１３】また，磁力固定を補強するために，電磁石
による磁力の供給を行い，チップ側吸着層１０と基板側
吸着層１１を強力に吸引させる。磁力の供給は，電磁石
を備えたテーブル１２により効果的に行うことができる
。Furthermore, in order to reinforce the fixation of the magnetic force, magnetic force is supplied by an electromagnet to strongly attract the chip-side adsorption layer 10 and the substrate-side adsorption layer 11. The magnetic force can be effectively supplied by a table 12 equipped with an electromagnet.
【００１４】[0014]
【実施例】以下，本発明を具体化した実施例について，
図面を参照しながら説明する。図３はＩＣチップを装着
した基板の斜視図で，ＣＯＢ（チップオンボード）タイ
プの基板１表面の所定位置にＩＣチップ４がワイヤによ
りボンディングリード６にボンディングされた状態を示
している。９は基板１上に設けられた外部端子である。[Examples] Hereinafter, examples embodying the present invention will be described.
This will be explained with reference to the drawings. FIG. 3 is a perspective view of a board on which an IC chip is mounted, and shows a state in which an IC chip 4 is bonded to a bonding lead 6 by a wire at a predetermined position on the surface of a COB (chip on board) type board 1. Reference numeral 9 denotes an external terminal provided on the substrate 1.
【００１５】図１（ａ）， （ｂ）は第１の実施例を説
明するための断面図で，（ａ） はＩＣチップ４が基板
１上に固定された状態，（ｂ） は配線及び封止後の状
態を示す。基板１の表面には磁石よりなる磁性層２が形
成され，その上に金メッキよりなるステージ部３が設け
られている。一方，ＩＣチップ４の裏面には磁気吸着可
能な金属よりなる吸着層５が形成されている。吸着層５
には鉄（Ｆｅ），ニッケル（Ｎｉ）等の磁性金属を使用
している。FIGS. 1(a) and 1(b) are cross-sectional views for explaining the first embodiment, in which (a) shows the state in which the IC chip 4 is fixed on the substrate 1, and (b) shows the state in which the wiring and The state after sealing is shown. A magnetic layer 2 made of a magnet is formed on the surface of the substrate 1, and a stage part 3 made of gold plating is provided thereon. On the other hand, an adsorption layer 5 made of metal capable of magnetic adsorption is formed on the back surface of the IC chip 4. Adsorption layer 5
Magnetic metals such as iron (Fe) and nickel (Ni) are used for this purpose.
【００１６】上記のように構成された基板１にＩＣチッ
プ４を搭載するには，ＩＣチップ４をステージ部３上に
置けば，ＩＣチップ４は磁性層２と吸着層５との磁気吸
引によりステージ部２に容易に固定される。磁性層２と
吸着層５との間に金メッキのステージ部３が介在するが
，薄いので磁気吸引を妨げない。In order to mount the IC chip 4 on the substrate 1 configured as described above, the IC chip 4 is placed on the stage section 3, and the IC chip 4 is attracted by the magnetic attraction between the magnetic layer 2 and the adsorption layer 5. It is easily fixed to the stage part 2. Although a gold-plated stage portion 3 is interposed between the magnetic layer 2 and the adsorption layer 5, it is thin and does not interfere with magnetic attraction.
【００１７】続いて，図１（ｂ） に示すようにワイヤ
ボンディングを行うことにより，ＩＣチップ４と基板１
上に設けられた金メッキよりなるボンディングリード６
とをワイヤ７により接続する。この後，ＩＣチップ４及
びボンディングリード６を覆うようにエポキシ樹脂等の
封止剤８を配置して加熱することにより封止剤８を固化
させれば搭載が完了する。なお，９は基板１上に設けら
れた外部端子である。Next, as shown in FIG. 1(b), wire bonding is performed to connect the IC chip 4 and the substrate 1.
Bonding lead 6 made of gold plating provided on the top
and are connected by wire 7. Thereafter, a sealant 8 such as an epoxy resin is placed so as to cover the IC chip 4 and the bonding leads 6, and the sealant 8 is solidified by heating to complete mounting. Note that 9 is an external terminal provided on the substrate 1.
【００１８】このように，本実施例ではＩＣチップ４裏
面に磁気吸着可能な吸着層５を形成するとともに，基板
１表面に磁石よりなる磁性層２を形成したので，従来の
接着剤による接着法に比べてＩＣチップ４を磁力にて瞬
時に固定でき，以後の配線及び封止作業を支障なく行う
ことができ，生産効率を向上することができる。As described above, in this embodiment, the adsorption layer 5 capable of magnetic attraction is formed on the back surface of the IC chip 4, and the magnetic layer 2 made of a magnet is formed on the surface of the substrate 1, so that the conventional bonding method using adhesive is not necessary. Compared to the conventional method, the IC chip 4 can be fixed instantly by magnetic force, and subsequent wiring and sealing work can be performed without any trouble, thereby improving production efficiency.
【００１９】また，本実施例ではＩＣチップ４を磁力に
て基板１に固定するようにしているので，従来の接着剤
による接着法のように配線工程において接着剤中の溶剤
分がリードに付着してワイヤが接続できなくなったり，
封止工程において溶剤分がガスとなって封止剤に混入し
て完全な封止ができなくなったりすることはなく，不良
率の低減を図ることができる。Furthermore, in this embodiment, since the IC chip 4 is fixed to the substrate 1 by magnetic force, the solvent in the adhesive does not adhere to the leads during the wiring process, unlike the conventional adhesive bonding method. or the wires cannot be connected.
In the sealing process, the solvent does not turn into gas and mix with the sealant, making it impossible to complete sealing, and it is possible to reduce the defective rate.
【００２０】なお，ＩＣチップ４裏面に磁性層２を形成
するとともに，基板１表面に吸着層５を形成してＩＣチ
ップ４を固定するようにしたり，ＩＣチップ４裏面及び
基板１表面に磁性層を設けてＩＣチップ４を固定するよ
うにしてもよい。In addition, the magnetic layer 2 is formed on the back surface of the IC chip 4, and an adsorption layer 5 is formed on the surface of the substrate 1 to fix the IC chip 4, or the magnetic layer 2 is formed on the back surface of the IC chip 4 and the surface of the substrate 1. The IC chip 4 may be fixed by providing a.
【００２１】また，ＩＣチップ４の裏面に磁力線を遮蔽
する銅（Ｃｕ）等のシールド部材を設けた後，吸着層５
を形成してもよい。図２は第２の実施例を説明するため
の断面図である。この例はＩＣチップ４を基板１にさら
に強固に固定する方法とそのための装置を示すもので，
第１の実施例における磁性層２の磁力が不十分で，ＩＣ
チップ４の基板１への固定が不安定になる場合の対策を
示す。Further, after providing a shielding member such as copper (Cu) for shielding magnetic lines of force on the back surface of the IC chip 4, an adsorption layer 5 is provided.
may be formed. FIG. 2 is a sectional view for explaining the second embodiment. This example shows a method and device for more firmly fixing the IC chip 4 to the substrate 1.
In the first embodiment, the magnetic force of the magnetic layer 2 is insufficient, and the IC
Measures to be taken when the fixation of the chip 4 to the substrate 1 becomes unstable will be shown.
【００２２】ワイヤボンダ本体につながるテーブル１２
に電磁石を装填し， 基板１を搭載するテーブル１２上
に磁力を供給する。電磁石の形成は，例えば，テーブル
１２内部にコイル１３を配置に外部からの電源（図示せ
ず）により電流を供給することにより行う。そして，Ｉ
Ｃチップ４裏面には磁気吸着可能なチップ側吸着層１０
，基板１表面には磁気吸着可能な基板側吸着層１１を形
成する。チップ側吸着層１０及び基板側吸着層１１の材
料としては，例えば，鉄（Ｆｅ），ニッケル（Ｎｉ）等
の磁性金属あるいはそれらの合金を使用する。基板側吸
着層１１上に金メッキのステージ部３を形成する。Table 12 connected to the wire bonder body
An electromagnet is loaded onto the table 12 to supply magnetic force onto the table 12 on which the board 1 is mounted. The electromagnet is formed, for example, by arranging the coil 13 inside the table 12 and supplying current from an external power source (not shown). And I
On the back side of the C chip 4, there is a chip-side adsorption layer 10 that can be magnetically adsorbed.
, a substrate-side adsorption layer 11 that can be magnetically adsorbed is formed on the surface of the substrate 1. As the material for the chip-side adsorption layer 10 and the substrate-side adsorption layer 11, for example, magnetic metals such as iron (Fe) and nickel (Ni) or alloys thereof are used. A gold-plated stage portion 3 is formed on the substrate-side adsorption layer 11.
【００２３】チップ側吸着層１０と基板側吸着層１１を
突き合わせた基板１をテーブル１２上に配置し，コイル
１３に電流を供給することにより，チップ側吸着層１０
と基板側吸着層１１に磁力を供給する。このようにして
，チップ側吸着層１０と基板側吸着層１１は磁力により
吸引し合い固定される。コイル１３に供給する電流を大
きくすることにより，固定強度を大きくすることができ
る。The substrate 1 with the chip-side adsorption layer 10 and the substrate-side adsorption layer 11 butted against each other is placed on the table 12, and by supplying current to the coil 13, the chip-side adsorption layer 10
and supplies magnetic force to the substrate-side adsorption layer 11. In this way, the chip-side adsorption layer 10 and the substrate-side adsorption layer 11 are attracted to each other by magnetic force and fixed. By increasing the current supplied to the coil 13, the fixing strength can be increased.
【００２４】この後の工程は，第１の実施例の図１（ｂ
） と同様である。即ち，ワイヤボンダにより，ＩＣチ
ップ４と基板１上に設けられた金メッキよりなるボンデ
ィングリード６とをワイヤ７により接続する。この後，
ＩＣチップ４及びボンディングリード６を覆うようにエ
ポキシ樹脂等の封止剤８を配置して加熱することにより
封止剤８を固化させれば搭載が完了する。The subsequent steps are shown in FIG. 1(b) of the first embodiment.
). That is, the IC chip 4 and the gold-plated bonding leads 6 provided on the substrate 1 are connected by wires 7 using a wire bonder. After this,
Mounting is completed by disposing a sealant 8 such as epoxy resin so as to cover the IC chip 4 and bonding leads 6 and solidifying the sealant 8 by heating.
【００２５】なお，基板１も基板側吸着層１１が電磁石
による磁力により吸引されるのでテーブル１２上に磁力
により固定されるが，真空吸引を併用して基板１のテー
ブル１２への固定を確実にすることができる。Note that the substrate 1 is also fixed on the table 12 by magnetic force since the substrate-side adsorption layer 11 is attracted by the magnetic force of the electromagnet. can do.
【００２６】[0026]
【発明の効果】以上説明したように，本発明によれば基
板１に対してＩＣチップ４を瞬時に固定して，それに続
く配線及び封止作業を支障なく行うことができ，生産効
率の向上及び不良率の低減を図ることができる。[Effects of the Invention] As explained above, according to the present invention, the IC chip 4 can be instantly fixed to the substrate 1, and the subsequent wiring and sealing work can be performed without any trouble, thereby improving production efficiency. It is also possible to reduce the defective rate.
【００２７】また，電磁石により磁力を強化することに
より基板１へのＩＣチップ４の固定を十分にして，安定
した配線及び封止作業を支障なく行うことができ，さら
に生産効率の向上及び不良率の低減を図ることができる
。In addition, by strengthening the magnetic force with the electromagnet, the IC chip 4 can be sufficiently fixed to the substrate 1, and stable wiring and sealing work can be performed without any problems. Furthermore, production efficiency can be improved and the defective rate can be reduced. It is possible to reduce the
【図１】第１の実施例を説明するための断面図で，（ａ
） はＩＣチップが基板上に固定された状態，（ｂ）
は配線及び封止後の状態である。[Fig. 1] A cross-sectional view for explaining a first embodiment.
) is the state in which the IC chip is fixed on the board, (b)
is the state after wiring and sealing.
【図２】第２の実施例を説明するための断面図である。FIG. 2 is a sectional view for explaining a second embodiment.
【図３】ＩＣチップを装着した基板の斜視図である。FIG. 3 is a perspective view of a board on which an IC chip is mounted.
【図４】ワイヤボンディングの従来例を示す側面図であ
る。FIG. 4 is a side view showing a conventional example of wire bonding.
１は基板
２は磁性層
３はステージ部
４はＩＣチップ
５は吸着層
６はボンディングリード
７はワイヤ
８は封止剤
９は外部端子
１０は磁気吸着層であってチップ側吸着層１１は磁気吸
着層であって基板側吸着層１２はテーブルであって電磁
石を備えたテーブル１３はコイル
１４はテーブルであって真空吸引パスを備えたテーブル
１５は真空吸引パス1 is a substrate 2 is a magnetic layer 3 is a stage part 4 is an IC chip 5 is an adsorption layer 6 is a bonding lead 7 is a wire 8 is a sealant 9 is an external terminal 10 is a magnetic adsorption layer, and an adsorption layer 11 on the chip side is a magnetic adsorption layer. The adsorption layer 12 on the substrate side is a table, the table 13 equipped with an electromagnet, the coil 14 is a table, and the table 15 equipped with a vacuum suction path is a vacuum suction path.
Claims (3)
チップ（４） を搭載する基板（１） 表面の少なくと
もいずれか一方に磁性層（２）を形成し，他方に磁気吸
着可能な吸着層（５） を形成し，該磁性層（２） と
該吸着層（５） を突き合わせて該ＩＣチップ（４）
を該基板（１） に磁力により固定した後，配線及び封
止を行うことを特徴とする半導体装置の製造方法。[Claim 1] IC chip (4) back surface or the IC
A magnetic layer (2) is formed on at least one of the surfaces of the substrate (1) on which the chip (4) is mounted, and an adsorption layer (5) capable of magnetic attraction is formed on the other surface, and the magnetic layer (2) and the magnetic layer (5) are formed on the other surface. The adsorption layer (5) is butted against the IC chip (4).
1. A method of manufacturing a semiconductor device, comprising: fixing the substrate (1) to the substrate (1) by magnetic force, and then performing wiring and sealing.
能なチップ側吸着層（１０）を形成し， 該ＩＣチップ
（４） を搭載する基板（１）表面に磁気吸着可能な基
板側吸着層（１１）を形成し， 該チップ側吸着層（１
０）と該基板側吸着層（１１）を突き合わせて該基板（
１） を電磁石を備えたテーブル（１２）上に配置し，
該電磁石により該チップ側吸着層（１０）と該基板側
吸着層（１１）に磁力を供給して該ＩＣチップ（４）
を該基板（１） に磁力により固定した後，配線及び封
止を行うことを特徴とする半導体装置の製造方法。[Claim 2] A chip-side adsorption layer (10) that can be magnetically adsorbed is formed on the back surface of the IC chip (4), and a substrate-side adsorption layer that can be magnetically adsorbed is formed on the surface of the substrate (1) on which the IC chip (4) is mounted. (11) and the chip side adsorption layer (1
0) and the substrate-side adsorption layer (11) and place the substrate (
1) Place on a table (12) equipped with an electromagnet,
The electromagnet supplies magnetic force to the chip side adsorption layer (10) and the substrate side adsorption layer (11) to attach the IC chip (4).
1. A method of manufacturing a semiconductor device, comprising: fixing the substrate (1) to the substrate (1) by magnetic force, and then performing wiring and sealing.
１） を搭載しかつ該ＩＣチップ（４） に磁力を供給
する電磁石を備えたテーブル（１２）を有し， 該基板
（１） に該ＩＣチップ（４） をワイヤボンディング
する半導体装置製造装置であって，該テーブル（１２）
は，磁気吸着層（１０）の形成されたＩＣチップ（４）
と磁気吸着層（１１）の形成された基板（１） に磁
力を供給して，該ＩＣチップ（４） を該基板（１）
に磁力により固定することを特徴とする半導体装置製造
装置。[Claim 3] A substrate (
1) A semiconductor device manufacturing apparatus for wire bonding the IC chip (4) to the substrate (1), the table (12) having an electromagnet that supplies magnetic force to the IC chip (4). Yes, the table (12)
is an IC chip (4) on which a magnetic adsorption layer (10) is formed.
By supplying magnetic force to the substrate (1) on which the magnetic adsorption layer (11) is formed, the IC chip (4) is attached to the substrate (1).
1. A semiconductor device manufacturing apparatus characterized in that semiconductor device manufacturing equipment is fixed by magnetic force.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019681A JPH04211998A (en) | 1990-02-14 | 1991-02-13 | Production of semiconductor device and semiconductor device production device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2-34181 | 1990-02-14 | ||
| JP3418190 | 1990-02-14 | ||
| JP3019681A JPH04211998A (en) | 1990-02-14 | 1991-02-13 | Production of semiconductor device and semiconductor device production device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04211998A true JPH04211998A (en) | 1992-08-03 |
Family
ID=26356526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3019681A Withdrawn JPH04211998A (en) | 1990-02-14 | 1991-02-13 | Production of semiconductor device and semiconductor device production device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04211998A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7397111B2 (en) * | 2003-06-04 | 2008-07-08 | Infineon Technologies, Ag | Semiconductor wafer, an electronic component, and a component carrier for producing the electronic component |
| JP2012013493A (en) * | 2010-06-30 | 2012-01-19 | Denso Corp | Manufacturing method for wafer level package structures |
-
1991
- 1991-02-13 JP JP3019681A patent/JPH04211998A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7397111B2 (en) * | 2003-06-04 | 2008-07-08 | Infineon Technologies, Ag | Semiconductor wafer, an electronic component, and a component carrier for producing the electronic component |
| JP2012013493A (en) * | 2010-06-30 | 2012-01-19 | Denso Corp | Manufacturing method for wafer level package structures |
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