JPH04211159A - Programmable device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a programmable device having programming area with reduced parasitic capacitance and stable characteristics. CONSTITUTION:An insulating film 18 with two thin window areas is formed between a lower electrode 12 and an upper electrode 15. When a voltage is applied between the upper and lower electrodes, programming areas 16 of the insulating film 18 are subjected to dielectric breakdown. The programming area is defined by a region where the upper and lower electrodes and the window overlap. The programming area can be smaller than the minimum size limited by process technology. Since the sum of the two programming areas is constant, characteristics of a programmable device are fairly stable even if mask registration is not perfect.

Description

[Detailed description of the invention]

[00011

TECHNICAL FIELD The present invention relates to a programmable element that can be electrically programmed and a method for manufacturing the same, and more particularly to a programmable element suitable for configuring a semiconductor integrated circuit and a method for manufacturing the same. [0002] [Prior Art] R with the content (data) desired by the user
Because OM (Read Only Memory) can be obtained immediately, PROM (PROM), which allows the user to electrically write data after purchase, is
rogrammable Read Only Memo
ry) is widely used as a semiconductor memory. [0003] Also, for the same reason, PLDs (PLDs) to which the user can electrically write the contents (functions) after purchase
Programmable Logic Device
) are also used as logic circuits. [0004] Such FROMs and PLDs are composed of programmable elements to which desired contents can be electrically written from the outside and the stored contents are retained even after the power is turned off. A conventional programmable element is disclosed, for example, in Japanese Patent Laid-Open No. 62-242336. [0005] A conventional programmable element will be described with reference to FIGS. 7 to 9. FIG. 7 shows a planar configuration of a conventional programmable element. As shown in the figure, P
A field insulating film 3 is selectively formed on a predetermined region (separation region) on the surface of a silicon substrate 1 of the type. On the surface of the silicon substrate 1, an N-type diffusion layer constituting the lower electrode 2 is formed in a region where the field insulating film 3 is not provided. Furthermore, on the silicon substrate 1,
An upper electrode 5 made of a polycrystalline silicon film is disposed with a field insulating film 3 interposed therebetween. The upper electrode 5 intersects the lower electrode 2 three-dimensionally at right angles. A region where the lower electrode 2 and the upper electrode 5 overlap each other (the region indicated by diagonal lines) constitutes a program region 6 . [0006] A FROM+PLD is a semiconductor device in which a large number of such programmable elements are integrated on the same silicon substrate. [0007] FIG. 8 is a sectional view taken along line CC in FIG. 7. As shown in FIG. 8, the upper surface of the lower electrode 2 is
It is covered with a thin program insulating film 7, and an upper electrode 5 is formed on the program insulating film 7. [0008] FIG. 9 is a sectional view taken along line DD in FIG. 7. As shown in FIG. 9, the upper surface of the lower electrode 2 is covered with a program insulating film 7, while the region of the silicon substrate 1 where the lower electrode 2 is not formed is covered with a field insulating film 3. That is, the upper surface (principal surface) of the silicon substrate 1 is completely covered with the program insulating film 7 and the field insulating film 3. Upper electrode 5 is electrically isolated from silicon substrate 1 by program insulating film 7 and field insulating film 3. [0009] In this programmable element, a voltage sufficiently higher than the dielectric strength voltage of the program insulating film 7 is applied between the upper electrode 5 and the lower electrode 2 to destroy the program insulating film 7 in the program area 6 and Electrode 5 and lower electrode 2
Programming or writing is performed by electrically connecting the two.

In the semiconductor integrated circuit having the programmable elements described above, polycrystalline silicon is used for electrodes (upper electrode 5) and wiring because it can withstand heat treatment at high temperatures and has excellent adhesion to the underlying insulating film. It is widely used as a material. Note that the electrodes of the semiconductor integrated circuit usually also serve as wirings that connect the electrodes of each programmable element integrated on the same semiconductor substrate, so the electrodes and wirings are hereinafter collectively referred to as "electrodes."

[0011] In general, the lower the resistance of an electrode, the better; therefore, when a polycrystalline silicon layer is used as an electrode, it is necessary to dope (diffuse) impurities into the polycrystalline silicon layer to lower its resistance. [0012] Even when an electrode having a laminated structure (polycide structure) of a polycrystalline silicon layer and a metal silicide layer is used instead of such an electrode made of a single polycrystalline silicon layer, the programmable element and the same Impurities are often doped into electrodes for purposes such as stabilizing the threshold voltage of MISFETs integrated on semiconductor substrates. [00131 Below, a conventional method for doping impurities into electrodes of a semiconductor integrated circuit will be described with reference to FIGS. 12(a) to 12(d). [0014] First, as shown in FIG. 12(a), in a predetermined region (separation region) on one plane of the P-type silicon substrate 101,
A field insulating film 102 is selectively formed, and the field insulating film 102 is
electrically isolates a plurality of regions where no Next, on the silicon substrate 101, a program insulating film 103 is formed on each region where the field insulating film 102 is not formed. At this time, silicon substrate 1
The thickness of the program insulating film 103 formed on the element formation region 104 of No. 01 and the thickness of the program insulating film 103 formed on the scribe line region 105 are usually approximately the same. [00151] Next, as shown in FIG. 12(b), a polycrystalline silicon film 106 is grown over the entire surface of the program insulating film 103 and the field insulating film 102. Furthermore, as shown in FIG. 12(c), 1×10 16 /cm 2 was added into the polycrystalline silicon film 106 by ion implantation.
Dope Chengpi with arsenic ions. [0016] Next, as shown in FIG. 12(d), the polycrystalline silicon film 6 is patterned into a desired shape by photoetching to form an upper electrode 107. [0017]

In such a conventional programmable element, the area to be programmed, that is, the area of the program area 6, is determined by the respective widths of the upper electrode 5 and the lower electrode 2 (FIG. 7). reference). The widths of the upper electrode 5 and the lower electrode 2 cannot be made very narrow from the viewpoint of reducing wiring resistance, so they are generally about 2 to 3 times the minimum processing dimension, and as a result, the area of the program area 6 cannot be made very narrow. In an actual semiconductor integrated circuit, there are several tens to tens of thousands of program areas 6, so the electrostatic capacitance of the unwritten program areas 6 as a whole is quite large as the parasitic capacitance of the semiconductor integrated circuit. become. Furthermore, in the conventional programmable element described above, since the lower electrode 2 is a high concentration impurity diffusion layer provided in the semiconductor substrate 1, a large parasitic capacitance is generated between the semiconductor substrate 1 and the lower electrode 2. In recent semiconductor integrated circuits, the layer thickness (the depth of the PN junction) of the highly concentrated impurity diffusion layer constituting the lower electrode 2 is usually thinner (shallow) than 0.3 μm, so the lower electrode 2 inevitably has a thickness of 40 μm. It has a high sheet resistance value of ~50Ω/mouth. [0018] As described above, conventional programmable elements have the drawback of reducing the operating speed of a semiconductor integrated circuit made up of the element. [0019] Furthermore, according to the conventional method of manufacturing a programmable element, during the ion implantation process, charges are accumulated in the polycrystalline silicon film 106 by the implanted ions.
The charges are discharged to the substrate 101 through the program insulating film 103 which is thinner than the field insulating film 102 . At this time, since the film thickness of the program insulating film 103 is almost the same regardless of the location, a discharge current flows with the same current density in any region. For this reason, the program insulating film 103 in the element formation region 4 may be destroyed, or even if it does not result in destruction, the dielectric breakdown voltage may deteriorate due to charge injection. In addition, the program insulating film 103 and the silicon substrate 101
Interfacial states are generated at the interface with. As a result, a problem arises in that the reliability of the device using the program insulating film 103 is reduced. [00201 The present invention solves the above-mentioned problems with the conventional device and its manufacturing method, and the area value of the program area is smaller than the limit determined by the minimum processing dimension in the manufacturing process, thereby reducing the parasitic effects of the program area. An object of the present invention is to provide a programmable element with reduced capacitance. [0021] Another object of the present invention is to provide a programmable element with stable programming characteristics, in which the area of a program region does not change due to mask misalignment during a lithography process. [0022] Still another object of the present invention is to provide a programmable element with high operating speed, and to reduce the signal delay time of a semiconductor integrated circuit made up of this programmable element. [00231] Still another object of the present invention is to provide a method for manufacturing a programmable element in which a thin insulating film constituting the programmable element is not destroyed by charges accumulated by ion implantation, or its characteristics are not deteriorated. It's about doing. [0024]

[Means for Solving the Problems] A programmable element of the present invention includes a first conductive layer, an insulating layer formed on the conductive layer, and a second conductive layer formed on the insulating layer. A programmable element comprising: an insulating layer having two window regions thinner than other regions; a first window region in the insulating layer; The regions where the second conductive layers overlap each other via the insulating layer include respective portions of the window regions. [0025] The device may further include a substrate on which another insulating layer is formed, and the first conductive layer may be a conductive layer formed on the other insulating layer. [0026] The first conductive layer may be a polycrystalline silicon layer. The first conductive layer may include a polycrystalline silicon layer and a metal silicide layer formed thereon. [0027] The insulating layer covers the top surface of the first conductive layer.
and a second part that covers an area other than the area where the first conductive layer is formed on the upper surface of the other insulating layer, and the window area of the insulating layer is the first part of the insulating layer. It may also extend over the second portion. [0028] Furthermore, the semiconductor substrate may be provided, and the first conductive layer may be an impurity diffusion layer formed in the semiconductor substrate. [0029] The insulating layer covers the top surface of the first conductive layer.
and a second portion covering an area other than the area where the first conductive layer is formed on the upper surface of the semiconductor substrate, and the window area of the insulating layer is formed between the first part and the second part of the insulating layer. The second conductive layer may cover the window region of the insulating layer. [00301 The insulating layer covers the top surface of the first conductive layer.
and a second portion covering an area other than the area where the first conductive layer is formed on the upper surface of the semiconductor substrate, and the window area of the insulating layer is formed between the first part and the second part of the insulating layer. The second conductive layer may cover a portion of the window region of the insulating layer. [0031] The method for manufacturing a programmable element of the present invention includes a step of selectively forming a field insulating film in an isolation region on one main surface of a semiconductor substrate, and a step of selectively forming a field insulating film in an isolation region on one main surface of a semiconductor substrate. a step of forming a first insulating film to constitute a programmable element on a first region of the semiconductor substrate; forming a second insulating film that functions as a protective insulating film and having a lower dielectric strength voltage than the first insulating film; The method includes a step of forming a conductive film on the second insulating film, and a step of doping the conductive film with impurities by ion implantation. [0032] Another method of manufacturing a programmable element of the present invention includes a step of selectively forming a field insulating film in an isolation region on one main surface of a semiconductor substrate, and a step of selectively forming a field insulating film on an isolation region on one main surface of a semiconductor substrate. forming a second insulating film having a lower dielectric strength voltage than the first insulating film and functioning as a protective insulating film on the second region; and forming an isolation region on one main surface of the semiconductor substrate. a step of forming a first insulating film constituting a programmable element on a first region of the other regions; The method includes a step of forming a conductive film on the second insulating film, and a step of doping the conductive film with impurities by ion implantation. [0033] Still another method of manufacturing a programmable element of the present invention includes the step of selectively forming a field insulating film in an isolation region on one main surface of a semiconductor substrate; A first insulating film constituting a programmable element is formed on a first region of the regions, and at the same time, a first insulating film is formed on a second region of the regions other than the isolation region. A step of forming a second insulating film which also has a low dielectric strength voltage and functions as a protective insulating film; The method includes a step of forming a conductive film on the second insulating film, and a step of doping the conductive film with an impurity using an ion implantation method. [0034] The second region may be formed within a scribe line region of the semiconductor substrate. [0035]

[Operation] According to the programmable element of the present invention, the insulating layer has two window regions thinner than other regions, and the first and second conductive layers overlap each other with the insulating layer interposed therebetween. includes a portion of each window area, the area of the program area made of a thin insulating film can be made smaller than the limit determined by the minimum processing size in manufacturing technology, and the parasitic capacitance of the program area can be reduced. reduced. Therefore, a semiconductor integrated circuit in which a large number of programmable elements of the present invention are integrated on the same semiconductor substrate has a short signal delay time and operates at high speed. [0036] Furthermore, according to the programmable element of the present invention, since the area of the program area does not change due to mask misalignment, the characteristics of the program element are unlikely to change. [0037] Furthermore, in one embodiment of the programmable element of the present invention, the parasitic capacitance between the lower electrode and the semiconductor substrate can be sufficiently reduced by separating the lower electrode from the semiconductor substrate by a sufficiently thick insulating layer. . According to this aspect, since a low resistance material can be used for the lower electrode, the sheet resistance of the lower electrode can be made sufficiently lower than the sheet resistance of the high impurity concentration diffusion layer. [0038] According to the method for manufacturing a programmable element of the present invention, the charge accumulated in the conductive film for electrodes on the insulating film by ion implantation flows only to the protected area of the semiconductor substrate, and the thin insulating film constituting the programmable element flows only to the protected area of the semiconductor substrate. It doesn't flow inside. Therefore, destruction of the thin insulating film constituting the programmable element and deterioration of characteristics can be prevented, and a highly reliable programmable element can be obtained. Furthermore, by providing the protection region in the scribe line region, similar excellent effects can be obtained without increasing the extra area for forming the protection region. [0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view of a programmable element according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line A--A in FIG. [00401 In actual semiconductor integrated circuits such as PROMs and PLDs, a large number of programmable elements as shown in FIG. 1 are integrated on the same semiconductor substrate.
Here, a single programmable element will be representatively explained.

[0041] As shown in FIG. 1, a field insulating film 13 is formed on a predetermined region (isolation region) of a P-type silicon substrate 11, which is a semiconductor substrate. On the surface of the silicon substrate 11, in a region where the field insulating film 13 is not formed, a lower electrode (first conductive layer) 12 made of an N-type diffusion layer (width, 2 μm) is formed. Lower electrode 1
2 is electrically isolated from other impurity diffusion layers (not shown) by a field insulating film 13. [00421 On the lower electrode 12, an insulating film 18 (FIG.
is not shown. (see FIG. 2) is formed. The upper surface of the silicon substrate 11 is covered with the insulating film 18 and the field insulating film 13. Hereinafter, this insulating film 18 and field insulating film 13 will be collectively referred to as an "insulating layer." This insulating layer electrically isolates the upper electrode 15 and the silicon substrate 11, which will be described later. This insulating layer has two window regions 14 having a thinner film thickness than other regions in a portion thereof (a portion where a programmable element is formed). In this embodiment, the window region 14 is formed in an insulating film 18 that constitutes an insulating layer. An example in which the window region 14 is formed across the insulating film 18 and the field insulating film 13 will be described later as a second embodiment. [0043] The average size of the window region 14 in this embodiment can be set to about the minimum processing size (about 1 μm) determined by the resolution of lithography and etching characteristics. The dimension of the window region 14 in this example is 1 μm. Regarding this dimension, an appropriate value less than or equal to the line width of the lower electrode 12 can be selected depending on the line width of the lower electrode 12. Further, the interval between two adjacent window regions 14 is 1 μm. Regarding this interval, an appropriate value less than or equal to the width of the upper electrode 15, which will be described later, can be selected depending on the width of the upper electrode 15, which will be described later. [0044] An upper electrode (second conductive layer) 15 made of a polycrystalline silicon layer (width 2 μm) is formed to span two adjacent window regions 14. The width of the shaded area (program area) 16 formed by the overlap of the upper electrode 15 and the window area 14 (the length of the side parallel to the A-A line among the sides of the area 16 shown in FIG. 1) In the end, a value of about 1100n is sufficient. In other words, even if mask misalignment between the upper electrode 15 and the window region 14 is taken into account, the width of the program area 16 is reduced to a value of about 1/2 to 1/3 of the normal minimum processing dimension. [0045] Then, as shown in FIG. 2, the lower electrode 12
An insulating film 18 having a thickness of about 1100 nm is formed on top of the insulating film 18, and a portion thereof becomes a window region 14 having a thin film thickness of about 10 nm. The window region 14 is composed of a program insulating film 17 made of an oxide film or a laminated film of an oxide film and a nitride film. The thickness of the program insulating film 17 is 15 to 2
The skin has a sufficiently thin thickness, for example, about 10 nm, that it can be destroyed by a voltage of about 0V. The programming insulating film 17 is
After the window region 14 of the insulating film 18 is removed by etching, a nitride film is formed on the lower electrode 12 by oxidizing the upper surface of the lower electrode 12 by, for example, a pyro-oxidation method or a dry oxidation method, or by a vapor-phase growth method. It is formed using a deposition method. [0046] As described above, the area of the insulating film 18 where the window area 14 and the upper electrode 15 overlap each other is the program area 16. According to such a structure, the dimensions of the program area 16 are approximately the minimum processing dimension in the direction in which the upper electrode 15 runs (the direction perpendicular to the line A-A in FIG. 1), and the dimension in the direction perpendicular to the upper electrode 15 Direction (AA in Figure 1
(direction parallel to the line), 1/2 to 1 of the minimum processing dimension
It can be made very small, about /3. Therefore, the area of the program area 16 of the programmable element of this embodiment is 0.
．． It becomes 3-0.5 μm2. This area is the area of the programmable region of the conventional programmable element (approximately 4 μm2
) is about 1/8 to 1/13. [0047] As can be seen from FIG. 2, the upper electrode 15 and the lower electrode 12 overlap each other in the insulating film 18 (
The opposing) portion is a relatively thin program insulating film 1.
7 and other relatively thick parts. This relatively thick portion can be formed to have an arbitrary thickness that is sufficiently thicker than the program insulating film 17. By making this portion thicker, the capacitance generated between the upper electrode 15 and the lower electrode 12 is reduced, and the parasitic capacitance of the semiconductor integrated circuit made up of this programming element is also reduced as a whole. [0048] In this embodiment, window regions 14 are formed in the insulating film 18 near both sides of the region where the upper electrode 15 is to be formed (see FIG. 1). Therefore, even if a positional shift occurs due to mask alignment between the position of the upper electrode 15 and the position of the window area 14 during the glue-filling process for forming the upper electrode 15, the two program areas The total area of 16 does not change, and stable program characteristics are always obtained. To explain in more detail, when the position of the upper electrode 15 shifts to the left in FIG. 1, the area of the left program area 16 increases, but the area of the right program area 16 increases by a corresponding amount. Decrease. Therefore, the total area of the two left and right program areas 16 will not fluctuate due to the positional deviation of the upper electrode 15. [0049] A second embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 shows the second embodiment of the present invention.
4 is a plan view of the embodiment, and FIG. 4 is a sectional view taken along line BB in FIG. 3. As shown in FIG. 3, a field insulating film 13 is formed on a predetermined region (isolation region) of a P-type silicon substrate 11, which is a semiconductor substrate. On the surface of the silicon substrate 11, a lower electrode 12 made of an N-type diffusion layer is formed in a region where the field insulating film 13 is not formed. The lower electrode 12 is electrically isolated from other impurity diffusion layers (not shown) by a field insulating film 13. An insulating film 28 (not shown in FIG. 3, see FIG. 4) having a thickness of about 1100 nm is formed on the lower electrode 12. An insulating layer consisting of the insulating film 28 and the field insulating film 13 covers the upper surface of the silicon substrate 11. This insulating layer has two window regions 2 which have a thinner film thickness than other regions in the part where the programmable element is to be formed.
It has 4. In this embodiment, each window region 24 straddles the insulating film 28 and the field insulating film 13. In other words, each of the window regions 24 straddles each of the two opposing sides of the lower electrode 12 shown in FIG. 3 . The average size of the window region 24 can be on the order of the minimum feature size determined by the lithography resolution and etching characteristics. In this example, the dimensions of the window region 24 are 1 μm. Regarding this dimension, an appropriate value less than or equal to the width of the upper electrode 15 can be selected depending on the width of the upper electrode 15. Further, the interval between two adjacent window regions 24 is 1 μm. Regarding this interval as well, an appropriate value less than or equal to the width of the lower electrode 12 can be selected depending on the width of the lower electrode 12. [00511 The thickness of the portion of the insulating film 28 where the window region 24 is formed, that is, the program region to be described later, is 1
0 nm, which is thinner than the thickness of other regions of the insulating film 28 (about 100 nm). Of the window area 24,
The portion overlapping with the lower electrode 12 constitutes a program area (shaded area in FIG. 3) 26. The width of the program area 26 determined by the window area 24 and the lower electrode 12 (the length of the side parallel to line B-B in FIG. 3 among the sides of the program area 26) is finally 110
About 0n is sufficient. Window area 24 and lower electrode 12
Even if mask alignment misalignment is taken into account, the width may normally be about 1/2 to 1/3 of the minimum processing dimension. [0052] The upper electrode 15 (width 2 μm) made of polycrystalline silicon completely covers each of the two adjacent program areas 26 . [00531 As shown in FIG. 4, most of the upper surface of the lower electrode 12 is covered with a thick insulating film 28 of about 1100 nm, but the lower electrode 12 and the window region 24 overlap on the upper surface of the lower electrode 12 Only the area covered by the program insulating film 27 is thin and has a thickness of about 10 nm. This program insulating film 27 constitutes a program region 26 of the insulating layer. [0054] According to this embodiment, the dimensions of the program area 26 are very small, approximately 1/2 to 1/3 of the minimum processing dimension in the direction parallel to the upper electrode 15 (the direction parallel to the B-B line). It can be made smaller. As a result, the area of the program area 26 of the programmable element of this embodiment is 0.3 to 0.5 .mu.m.sup.2. This area is approximately 1/8 to 4 μm of the programmable area of a conventional programmable element.
It is about 1/13. [0055] The thickness of the insulating film 28 in the region where the upper electrode 15 and the lower electrode 12 overlap each other in areas other than the program area 26 can be made sufficiently thicker than the thickness of the program insulating film 27. Electrode 15
The electrostatic capacitance generated between the programming element and the lower electrode 12 is reduced, and the parasitic capacitance of the semiconductor integrated circuit made up of this programming element is also reduced as a whole. [0056] Furthermore, in this embodiment, window regions 24 are formed in the insulating film 28 near both sides of the lower electrode 12 (see FIG. 3). Therefore, even if a positional shift occurs between the position of the window region 24 and the position of the lower electrode 12 due to misalignment of the mask during the glue finishing process for forming the window region 24, the two program regions Since the total area of 26 does not change, stable program characteristics can always be obtained. To explain more specifically, when the position of the window area 24 shifts upward in FIG. 3, the area of the upper program area 26 in the figure decreases, but the area of the lower program area 26 decreases accordingly. increases by the amount. Therefore, even if there is a positional shift in the window area 24, the total area of the two upper and lower program areas 26 will not change. [0057] FIG. 5 is a plan view of a third embodiment of the present invention. This embodiment allows the effects of the present invention to be exhibited even more markedly. [0058] As shown in FIG. 5, the main structural difference between this embodiment and the above-described first and second embodiments is that
4, and the rest are the same. [0059] In this embodiment, each window region 34 straddles the insulating film (not shown in FIG. 6) on the lower electrode 12 and the field insulating film 13. In other words, each of the window regions 24 straddles each of the two opposing sides of the lower electrode 12 shown in FIG. 5 . Furthermore, the window region 34 straddles each of the two opposing sides of the upper electrode 15. [00601] According to this configuration, the shape of the program area 36 shaded in FIG. 5 is determined by the area where the lower electrode 12, the window area 34, and the upper electrode 15 overlap with each other. Since the width of the overlapping portion of the window region 34 and the upper electrode 15 can be reduced to about 1/2 to 1/3 of the minimum processing dimension, the area of the program region 36 can be reduced to 0. 1~0.
It becomes 25 μm2. This area is approximately 1/1 of the area of the programmable region of a conventional programmable element (approximately 4 μm).
The size is reduced to about 6 to 1/40, and the effect of reducing the parasitic capacitance becomes very remarkable. [0061] Furthermore, according to this configuration, during the adhesive process for forming the window region 34, a positional shift occurs between the position of the window region 34 and the position of the lower electrode 12 due to mask misalignment. However, the total area of the two program areas 36 does not change. In addition, during the glue process for forming the upper electrode 15, the upper electrode 1
Even if a positional shift occurs between the position No. 5 and the position of the floor plan 34 due to mask misalignment, the total area of the two program areas 36 does not change. Therefore, according to the programmable element of this embodiment, more stable program characteristics can be obtained than those of the first and second embodiments. [0062] 1st. The lower electrodes 12 of the programmable elements of the second and third embodiments are both impurity diffusion layers formed on the silicon substrate 11. Example 4)
I will explain it to you. FIG. 6 is a cross-sectional view of a programmable element according to a fourth embodiment of the present invention. The planar configuration of this embodiment is substantially the same as that of the first embodiment (see FIG. 1). [0063] As shown in FIG. 6, a field insulating film 10 having a sufficient thickness, for example, about 500 nm, is formed on the semiconductor substrate 11. On the field insulating film 10 is a lower electrode 12 made of polycrystalline silicon.
is formed. The lower electrode 12 may be a layer having a stacked structure (polycide structure) of a polycrystalline silicon layer and a metal silicide layer formed thereon, in addition to the negative polycrystalline silicon layer. [0064] When the lower electrode 12 is a polycrystalline silicon layer with a thickness of about 400 nm formed using, for example, a low-pressure vapor deposition method, by doping the polycrystalline silicon layer with impurities at a high concentration, The sheet resistance of the lower electrode 12 is about 20Ω/hole. On the other hand, the lower electrode 12 has a film thickness of approximately 200 mm formed using, for example, a low pressure vapor phase epitaxy method.
In the case of a layer having a polycide structure in which a polycrystalline silicon layer with a thickness of about 150 nm and a tungsten silicide with a thickness of about 150 nm are sequentially laminated, the sheet resistance of the lower electrode 12 is about 5 Ω/hole. In this way, in any case, the sheet resistance of the lower electrode 12 of this example is equal to the sheet resistance (40
~50Ω/mouth). [0065] Most of the upper surface of the lower electrode 12 is 15 to 2
It is covered with an insulating film 18 having a sufficient thickness, for example, about 120 nm, so that it will not be destroyed by application of a program voltage of about 0.0 nm. Of the insulating film 18, the lower electrode 12
A region located on a predetermined region of the upper surface of the film constitutes a window region 14 having a thinner film thickness than other regions. This window region 14 is composed of a programming insulating film 17 made of an oxide film or a laminated film of an oxide film and a nitride film. The programming insulating film 17 has a sufficiently thin thickness that can be destroyed by a voltage of about 15 to 20 V, for example, about 10 nm. The programming insulating film 17 is formed by oxidizing the upper surface of the lower electrode (polycrystalline silicon layer) 12 using, for example, a pyro-oxidation method or a dry oxidation method, or by depositing a nitride film on the lower electrode 12 by a vapor-phase growth method or the like. formed using a method. [0066] An upper electrode (second conductive layer) 15 made of polycrystalline silicon is formed on the insulating film 18, and the upper electrode 15 covers a part of each window region 14 of the insulating film 18. There is. In the window region 14 of the insulating film 18, the upper electrode 1
The area covered by 5 functions as a program area 16. [0067] In the programmable element of this embodiment, the field insulating film 10 has a sufficiently thick film thickness of about 500 nm, so that the parasitic capacitance between the lower electrode 12 and the semiconductor substrate 11 is as low as that in the first embodiment of the present invention. example, and the parasitic capacitance of the prior art programmable element. Further, as described above, the sheet resistance of the lower electrode 12 is also lower than that of the lower electrode 2 of the prior art. In particular, when the lower electrode 12 has a polycide structure, the degree of this decrease in resistance is remarkable. [0068] For these reasons, the semiconductor integrated circuit in which a large number of programmable elements of this embodiment are integrated on the same semiconductor substrate can operate at high speed because the signal delay time is short. [0069] Since the programmable element of this embodiment has two window regions 14 similarly to the first embodiment, in addition to the above-mentioned advantages, it also has the same excellent advantages as the first embodiment. have. [00701] As described above, according to the programmable element of the present invention, the area of the program area made of a thin insulating film can be made smaller than the limit determined by the minimum processing size in manufacturing technology, thereby preventing irregularities in the program area. Capacity is reduced. Furthermore, since the area of the program area does not change due to mask misalignment, the characteristics of the program element are less likely to change. [0071] Furthermore, in the programmable element of the present invention, by separating the lower electrode from the semiconductor substrate by a sufficiently thick insulating layer, the parasitic capacitance between the lower electrode and the semiconductor substrate can be sufficiently reduced. . According to this aspect, since a low resistance material can be used for the lower electrode, the sheet resistance of the lower electrode can be made sufficiently lower than the sheet resistance of the high impurity concentration diffusion layer. [0072] Note that the dimensions (film thickness) and materials of each member constituting the programmable element of the present invention, the method of forming these members, etc. are not necessarily limited to those described above. [0073] When manufacturing the programmable element of the present invention having a thin insulating film as the program insulating films 17 and 27, during the process of implanting ions into the conductive film for forming the upper electrode 15, The charge accumulated in the conductive film may destroy the thin insulating film. Hereinafter, a method for manufacturing a programmable element that prevents destruction of the insulating film will be described with reference to FIGS. 10(a) to 10(d). [0074] First, as shown in FIG. 10A, a field oxide film 112 is formed by selectively oxidizing a predetermined region (isolation region) on the main surface of the P-type semiconductor substrate 111. As a method for forming a field oxide film, a method other than the local oxidation method described above, such as a method of forming a field oxide film (insulating film) by depositing and patterning an oxide film or other insulating film, may be used. [00751 On the main surface of the semiconductor substrate 111, the plurality of regions where the field oxide film 112 is not formed are electrically isolated from each other by the field oxide film 112. A program insulating film 114 is formed in a region (first region) located in the element region 113 of the semiconductor substrate 111 among a plurality of regions on the main surface of the semiconductor substrate 111 where the field oxide film 112 is not formed. [0076] On the other hand, among the regions where the field oxide film 112 is not formed, the region located in the protection region 115 (
In the second region), a protective insulating film 116 which is more susceptible to dielectric breakdown than the program insulating film 114 is formed. In order to make the dielectric breakdown voltage of the protective insulating film 116 lower than the dielectric breakdown voltage of the program insulating film 114, the thickness of the protective insulating film 116 may be made thinner than that of the program insulating film 114. For example, the thickness of the program insulating film 114 is 20 nm.
In this case, the thickness of the protective insulating film 116 is 10 to 15 nm.
It is sufficient to set it to a certain degree. [0077] Although not shown in FIG. 10A, a lower electrode made of an impurity diffusion layer is formed in the lower region (first region) of the program insulating film 114 in the semiconductor substrate 111. This impurity diffusion layer is formed before the step of forming the program insulating film 114. [0078] The protective insulating film 116 is, for example, an insulating film (
(not shown) can be selectively removed by a photoetching method and then formed again by oxidizing the upper surface of the protective region 115. [0079] Either of the process of forming the program insulating film 113 and the process of forming the protective insulating film 116 may be performed first. It is also possible to perform these steps simultaneously. When simultaneously oxidizing the first region and the second region of the semiconductor substrate 111, if the oxidation rate of the first region is made higher than the oxidation rate of the second region, the programming insulating film 114 and its A thinner protective insulating film 116 can be obtained at the same time. semiconductor substrate 11
In order to make the oxidation rates different between the first region and the second region of the semiconductor substrate 111 in this way, the impurity concentration in the first region of the semiconductor substrate 111 is set to be lower than the impurity concentration in the second region. Just make it higher. As described above, the semiconductor substrate 111
Since a high concentration impurity diffusion layer that will become the lower electrode is formed in the first region of the semiconductor substrate 111, if such a high concentration impurity diffusion layer is not formed in the second region of the semiconductor substrate 111, the semiconductor It is easily possible to make the impurity concentration in the first region of the substrate 111 higher than the impurity concentration in the second region. In this way, the program insulating film 114 and the protective insulating film 116 can be more easily formed in one oxidation process. According to this method, there is no need to perform a special process to form the protective insulating film 116, so there is an advantage that the number of manufacturing processes does not increase. [00801] Next, as shown in FIG. 10(b), a polycrystalline silicon film 117 is formed on the entire surface of the substrate 111, covering the field oxide film 112, the program insulating film 114, and the protective insulating film 116. [00811] Thereafter, the polycrystalline silicon film 117 is doped with impurities by a method such as heat treatment in a phosphorus oxychloride (POC13) atmosphere to impart conductivity. The amount of impurities only needs to be sufficient to make the polycrystalline silicon film 117 conductive, and there is no need to dope it to a very high concentration. Furthermore, the uniformity of the impurity concentration distribution in the film is not as important as other conditions. [0082] Next, as shown in FIG. 10(c), 1016/1016/
Arsenic ions are doped to about Cm2. In this step, arsenic ions are implanted into the polycrystalline silicon film 117.
Most of the charges accumulated therein are discharged to the substrate 111 through the relatively thin protective insulating film 116. This is because the protection region 115, which is a part of the main surface of the substrate 111, is doped with an impurity of a conductivity type opposite to that of the substrate 111, and the protection region 115 is electrically connected to the semiconductor substrate 111. Because there is. [0083] During the ion implantation process, the potential of the polycrystalline silicon film 117 with respect to the substrate 111 is lower than that of the protective insulating film 116.
It is fixed at about the dielectric breakdown voltage of . Therefore, almost no current flows through the program insulating film 14, which is thicker than the protective insulating film 116 and has a high dielectric breakdown voltage. [0084] Next, as shown in FIG. 10(d), the polycrystalline silicon film 117 is processed into a desired shape by photoetching to form an upper electrode 118. At this time,
As shown in the figure, if the polycrystalline silicon film on the protective region 115 is removed, or even if the polycrystalline silicon film is left, if it is separated from the upper electrode 118, the protective insulating film 1
Even if 16 is destroyed or deteriorated, the operation of the element will not be affected at all. [00851] Next, with reference to FIGS. 11(a) to 11(d), another manufacturing method of the present invention in which a protected area is provided within a scribe line area will be described. (0086) First, as shown in FIG. 11A, a field oxide film 122 is formed by selectively oxidizing a predetermined region (separation region) on the main surface of the P-type semiconductor substrate 121.Semiconductor substrate 121 The area on the main surface where the field oxide film is not formed is the field oxide film 122.
is separated into multiple areas. A normal program insulating film 123 is formed in a region (first region) located within the element region 123 of the semiconductor substrate 121 among a plurality of regions in the semiconductor substrate 121 where the field oxide film 122 is not formed. [0087] On the other hand, among the plurality of regions in the semiconductor substrate 121 where the field oxide film 122 is not formed,
A program insulating film 124 is provided in a region (second region) located within the scribe line region 125 of the semiconductor substrate 121.
A protective insulating film 126 is formed to be thinner than the above. Semiconductor substrate 1
In particular, the scribe line region 125 of No. 21 is not doped with an impurity of a conductivity type opposite to that of the semiconductor substrate 121. Therefore, the scribe line area 125 is
It is electrically connected to the inside of the semiconductor substrate 121 . [00881] Next, as shown in FIG. 11(b), a polycrystalline silicon film 127 is formed on the entire surface covering the field oxide film 122, the program insulating film 124, and the protective insulating film 126, and then this polycrystalline silicon film 127 is doped with impurities using a thermal diffusion method to give conductivity. [0089] Next, as shown in FIG. 11(c), 1016/
Dope about 2 cm of skin with arsenic ions. [00901] Next, as shown in FIG. 11(d), the polycrystalline silicon film 127 is processed into a desired shape by photoetching or the like to form an upper electrode 128. [00911 In this embodiment, since the protective insulating film 126 is formed on the scribe line region 125 of the semiconductor substrate 121, it is not necessary to provide a special region on the semiconductor substrate 121 for forming the protective region. . [0092] Here, for convenience of explanation, an example is given in which the entire scribe line region 125 of the semiconductor substrate 121 is used as a protection region, but sufficient effects can be obtained even if only a part of the scribe line region is used as a protection region. can be obtained. [0093] In the above embodiment, the semiconductor substrate 11
1. The protection region 115 of 121 or the scribe line region 125 is not particularly doped with impurities, but these regions are doped with impurities of the same conductivity type as the semiconductor substrates 111 and 121 at a high concentration. You may. [0094] In order to make the breakdown voltage of the protective insulating films 116, 126 lower than that of the program insulating films 114, 124, instead of making the protective insulating films 116, 126 relatively thin, You may change the material. For example, an oxide film may be used as the protective insulating films 116 and 126, and a composite film (multilayer film) of an oxide film and a nitride film may be used as the program insulating films 114 and 124. This is because, in general, when comparing an oxide film and a composite film of an oxide film and a nitride film, if both film thicknesses are approximately the same, the breakdown voltage of the latter is higher than that of the former. [0095] In this example, a polycrystalline silicon layer was used as the upper electrodes 118, 128, and conductivity was imparted to the polycrystalline silicon by a thermal diffusion method. For example, tungsten, molybdenum, titanium, tantalum or their silicides, aluminum, aluminum alloys, etc. may be used. Further, when using a polycrystalline silicon layer as the upper electrodes 118 and 128, impurities may be introduced into the growing polycrystalline silicon layer while the polycrystalline silicon layer is being grown in a vapor phase. . In addition, regarding the elements (ions) doped into the conductive films that will become the upper electrodes 118 and 128 by the ion implantation method and the dose thereof, etc.
The types and values are not limited to those shown in the examples. [0096] As described above, according to the method for manufacturing a programmable element of the present invention, the charges accumulated in the conductive film for electrodes on the insulating film by ion implantation flow only to the protected region of the semiconductor substrate, forming the programmable element. does not flow through a thin insulating film. Therefore, destruction of the thin insulating film constituting the programmable element and deterioration of its characteristics can be prevented, and a highly reliable programmable element can be obtained. Furthermore, by providing the protection area in the scribe line area, the area for forming the protection area can be avoided without increasing the extra area.
Similar excellent effects can be obtained. [0097] Note that this method of manufacturing a programmable element can also be used to manufacture a semiconductor element other than a programmable element, such as a MISFET, which has a thin insulating film that is prone to dielectric breakdown, such as a gate insulating film. .

[0098]

As described above, according to the programmable element of the present invention, the area of the program area made of a thin insulating film can be made smaller than the limit determined by the minimum processing size in manufacturing technology. The parasitic capacitance of is reduced. Therefore, a semiconductor integrated circuit in which a large number of programmable elements of the present invention are integrated on the same semiconductor substrate has a short signal delay time and can operate at high speed. [0099] Furthermore, according to the programmable element of the present invention, since the area of the program area does not change due to mask misalignment, the characteristics of the program element are unlikely to change.

Furthermore, in the programmable element of the present invention, by separating the lower electrode from the semiconductor substrate by a sufficiently thick insulating layer, the parasitic capacitance between the lower electrode and the semiconductor substrate can be sufficiently reduced. can. According to this aspect, since a low resistance material can be used for the lower electrode, the sheet resistance of the lower electrode can be made sufficiently lower than the sheet resistance of the high impurity concentration diffusion layer. [0101] According to the method for manufacturing a programmable element of the present invention, charges accumulated in the conductive film for electrodes on the insulating film by ion implantation flow only to the protected region of the semiconductor substrate, and the thin insulating film constituting the programmable element flows only to the protected area of the semiconductor substrate. It doesn't flow inside. Therefore, destruction of the thin insulating film constituting the programmable element and deterioration of characteristics can be prevented, and a highly reliable programmable element can be obtained. Furthermore, by providing the protection region in the scribe line region, similar excellent effects can be obtained without increasing the extra area for forming the protection region.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a programmable element that is a first embodiment of the present invention.

[Figure 2] Cross-sectional view taken along line A-A in Figure 1

FIG. 3 is a plan view of a programmable element that is a second embodiment of the present invention.

[Fig. 4] Cross-sectional view taken along line B-B in Fig. 3

FIG. 5 is a plan view of a programmable element that is a third embodiment of the present invention.

FIG. 6 is a cross-sectional view of a programmable element that is a fourth embodiment of the present invention.

[Fig. 7] Plan view of an example of a conventional programmable element

[Fig. 8] Cross-sectional view taken along line C-C in Fig. 7

[Figure 9]D- in Figure 7
Cross-sectional view along line D

FIG. 10 is a cross-sectional view of the device at each main process stage of the programmable device manufacturing method according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view of the device at each main process step of a method for manufacturing a programmable element according to another embodiment of the present invention.

[Fig. 12] Cross-sectional views of equipment at each main process stage of a conventional programmable element manufacturing method

[Explanation of symbols]

11 Silicon substrate 12 Lower electrode (first conductive layer) 13 Field insulation film 14 Window area 15 Upper electrode (second conductive layer) 16 Program area 17 Program insulation film 18 Insulating film 24 Window area 26 Program area 27 Program insulation film 28 Insulating film 34 Window area 36 Program area 111 Semiconductor substrate 112 Field oxide film 113 Element area 114 Program insulation film 115 Protected area 116 Protective insulation film 117 Polycrystalline silicon 118 Upper electrode 121 Semiconductor substrate 122 Field oxide film 123 Element area 124 Program insulation film 125 Scribe line area 126 Protective insulation film 127 Polycrystalline silicon 128 Upper electrode

[Figure 1]

[Figure 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8] cFigure 9]

[Figure 10]

[Figure 11]

[Figure 12]

Claims (12)

[Claims] 1. A semiconductor device comprising: a first conductive layer; a first insulating layer formed on the first conductive layer; and a second conductive layer formed on the first insulating layer. In the programmable element, the first insulating layer has two window regions thinner than other regions, and in the first insulating layer, the first conductive layer and the first A programmable element, wherein a region where two conductive layers overlap each other with the first insulating layer interposed therebetween includes a portion of each of the window regions. 2. A substrate having a second insulating layer formed on the upper surface;
a first conductive layer formed on the second insulating layer; a first insulating layer formed on the first conductive layer;
a second conductive layer formed on an insulating layer, the first insulating layer having two window regions thinner than other regions, 2. In the first insulating layer, a region where the first conductive layer and the second conductive layer overlap each other with the first insulating layer interposed therebetween includes a portion of each of the window regions. The programmable element described in . 3. The programmable element according to claim 2, wherein the first conductive layer is a polycrystalline silicon layer. 4. The programmable element according to claim 2, wherein the first conductive layer includes a polycrystalline silicon layer and a metal silicide layer formed on the polycrystalline silicon layer. 5. The first insulating layer covers a first portion covering the upper surface of the first conductive layer and a region other than the region where the first conductive layer is formed on the upper surface of the second insulating layer. a second portion covering a region, and the window region of the insulating layer covers the first region.
The programmable element according to claim 2, which straddles the first portion and the second portion of the insulating layer. 6. A semiconductor substrate, a first conductive layer made of an impurity diffusion layer formed on the semiconductor substrate, a first insulating layer formed on the first conductive layer, and a first insulating layer formed on the first conductive layer. a second conductive layer formed on an insulating layer, the first insulating layer having two window regions thinner than other regions; 2. In the first insulating layer, a region where the first conductive layer and the second conductive layer overlap each other with the first insulating layer interposed therebetween includes a portion of each of the window regions. Programmable element as described. 7. The first insulating layer includes a first portion that covers an upper surface of the first conductive layer and a second portion that covers an area other than the area where the first conductive layer is formed on the upper surface of the semiconductor substrate. 2 portions, the window region of the first insulating layer straddles the first portion and the second portion of the first insulating layer, and the second conductive layer has a second portion of the first insulating layer. 7. The programmable element of claim 6, wherein a first insulating layer covers the window area. 8. The first insulating layer includes a first portion that covers an upper surface of the first conductive layer and a second portion that covers an area other than the area where the first conductive layer is formed on the upper surface of the semiconductor substrate. 2 portions, the window region of the first insulating layer straddles the first portion and the second portion of the first insulating layer, and the second conductive layer has a second portion of the first insulating layer. 7. The programmable element of claim 6, wherein a first insulating layer covers a portion of the window area. 9. A step of selectively forming a field insulating film in an isolation region on one principal surface of a semiconductor substrate; A first region constituting a programmable element is formed on the region.
forming an insulating film on the main surface of the semiconductor substrate;
on the region, having a dielectric strength lower than that of the first insulating film,
a step of forming a second insulating film functioning as a protective insulating film; a step of forming a conductive film on at least the first insulating film and the second insulating film; A method for manufacturing a programmable element, comprising the step of doping a conductive film with an impurity. 10. A step of selectively forming a field insulating film in an isolation region on one principal surface of the semiconductor substrate; forming a second insulating film having a lower dielectric strength than the first insulating film and functioning as a protective insulating film on the region; A step of forming a first insulating film constituting a programmable element on a first region of the regions, and a step of forming a conductive film on at least the first insulating film and the second insulating film. and doping the conductive film with an impurity by ion implantation. 11. A step of selectively forming a field insulating film in an isolation region on one main surface of a semiconductor substrate, and a first region of the regions other than the isolation region on the - main surface of the semiconductor substrate. On top, a first
a second insulating film having a lower dielectric strength voltage than the first insulating film and functioning as a protective insulating film on a second region of the regions other than the isolation region; a step of forming a conductive film on at least the first insulating film and the second insulating film;
A method for manufacturing a semiconductor device, comprising the step of doping the conductive film with an impurity using an ion implantation method. 12. The method of manufacturing a programmable element according to claim 9, wherein the second region is formed within a scribe line region of the semiconductor substrate.