JPH04216212A - Static cmos flip-flop circuit - Google Patents

Abstract

PURPOSE:To enable a high-speed operation equal to a CMOS dynamic flip-flop by using the CMOS static flip-flop having the high stability of operations. CONSTITUTION:When a clock signal is changed from an 'L' level to an 'H' level, transfer gates 3, 4, 9 and 10 are turned to a conductive state and transfer gates 7, 8, 11 and 12 are turned to an inconductive state. Flip-flop elements on a master side are turned to the holding state of signals, and signals at the 'L' and 'H' levels are respectively transmitted from CMOS inverters 1 and 2 through the transfer gates 9 and 10, which are set in the conductive state, to slave side CMOS inverters 5 and 6. As the result, an output Q is inverted from the 'L' level to the 'H' level signal. Since potential difference between both the terminals of the transfer gate is always secured almost at a power supply voltage, a large current flows just after the gate is turned to the conductive state, and gate capacity can be charged/discharged in a short time.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to ultra-high-speed CMOS flip-flop circuits that operate in the GHz band, and in particular to low-power, ultra-high-speed prescaler ICs that are components of frequency synthesizers used in ultra-compact mobile phones and the like. The present invention relates to a preferred circuit configuration method.

0002

[Background Art] With the advancement of the information society, car telephones and
Demand for mobile communication devices such as mobile phones is rapidly increasing. The most effective way to reduce the size and weight of these mobile communication devices is to reduce battery volume and weight by reducing the power consumption of circuits used in frequency synthesizers such as prescalers. On the other hand, with the expansion of the use of mobile communications, the frequency bands allocated for this purpose are becoming increasingly high-frequency. In other words, from the conventional 800MHz band to 1.5GHz
Furthermore, a 3.0 GHz band is planned. In response to these trends, there is an increasing demand for faster speeds for the above-mentioned prescaler circuits and the like.

Under these circumstances, conventional prescaler circuits have been constructed of GaAs-ICs or Si bipolar ICs. From the viewpoint of reducing system cost and power consumption of mobile communication equipment, it is desirable to make the entire system completely CMOS, but it has been difficult for conventional CMOS circuits to operate stably and at high speed in the GHz band.

[0004] First, the conventional circuit technology for CMOS flip-flop circuits, which are the constituent elements of prescaler ICs, will be reviewed. Conventionally, there are two types of CMOS flip-flop circuits: a dynamic type that has excellent high-speed operation, and a static type that has excellent operational stability. Typical circuit examples are shown in FIGS. 4 and 6.

The dynamic flip-flop shown in FIG. 4 is composed of two clocked inverters, a master and a slave. In the figure, a P-channel transistor 41, an N-channel transistor 42, and a CMOS inverter 43 constitute a clocked inverter 44. A P-channel transistor 45, an N-channel transistor 46, and a CMOS inverter 47 constitute a clocked inverter 48 to obtain an output Q. CMOS inverter 49
constitutes a buffer circuit that obtains an inverted output Q'. This inverted output Q' is fed back to the input D. The CMOS inverter 50 constitutes a buffer circuit for obtaining an inverted signal C' of the clock signal C for controlling each of the clocked inverters.

In the circuit of FIG. 4, the initial state is defined as the clock signal=H (high level), the output A of clocked inverter 44=H, and the output Q of clocked inverter 48=L (low level). Then, the P-channel transistor 41 and the N-channel transistor 42 are both turned off (non-conductive), so that the clocked inverter 44 is in an inoperative state. Therefore, during the period when the clock signal is H, the charge stored in the composite capacitance Cl (=Cj+Cg) of the source-drain junction capacitance Cj of the CMOS inverter 43 and the gate capacitance output Cg of the CMOS inverter 47 at the next stage increases the 'H' level. Signal is maintained. On the other hand, since both the P-channel transistor 45 and the N-channel transistor 46 are in the on (conducting) state,
Clocked inverter 48 is in an operating state. Therefore, the clocked inverter 48 receives the output A='H' level of the previous stage clocked inverter 44, and goes 'L'.
Outputs a level signal. Further, this output is inverted by a CMOS inverter 49 to become an 'H' level and fed back to the input D. During the period when the clock signal = H, the combined capacitance C3 (=Cj+Cg) of the source-drain junction capacitance Cj of the CMOS inverter 49 and the gate capacitance Cg of the next stage CMOS inverter 43 is equal to the power supply voltage VD.
It is charged at D (same potential as 'H' level).

Next, when the clock signal changes to ``L'' level, clocked inverter 44 becomes active and clocked inverter 48 becomes inactive. As a result, the clocked inverter 44 receives the 'H' level of the input D and outputs the 'L' level. That is, clock signal =
During the L period, the combined capacitance Cl continues to be discharged. On the other hand, since the clocked inverter 48 is inactive, the output Q is held at an 'L' level signal by the composite capacitor C2. While the signal level of the output Q is kept at 'L' level and below the logic threshold of the CMOS inverter 49, '
The H' level is fed back to input D.

Next, when the clock signal changes to 'H' level, clocked inverter 44 becomes active and clocked inverter 48 becomes inactive. As a result, the output A of the clocked inverter 44 is maintained at the 'L' level, and the signal level of the output Q changes from the 'L' level to the 'H' level.
'level,' the signal level of the inverted output Q changes from 'H' level to 'L' level. Since similar changes are repeated due to changes in the clock signal as described above, the circuit operation of FIG. 4 becomes as shown in the waveform diagram of FIG. 5.

The circuit shown in FIG. 4 has excellent high-speed operation, and the inventors of the present application have developed a circuit with a gate length of 0.2 μm class.
The above circuit is constructed using a MOS process, and frequency division operation of 3.2 GHz has been confirmed at a power supply voltage (VDD) of 2 V. Figure 3 shows the dependence of the maximum operating frequency on the power supply voltage (Reference: Y. Kado, Y. Okazaki, M. Suzu
ki, and T. Kobyashi; Electro
nics Letters, 1990, Vol. 26,
No. 20, pp1684). This provides the prospect of realizing low-power consumption, ultra-high-speed CMOS/LSIs that operate in the GHz band, and will enable low-power 3G to be used in mobile communications in the future.
Application to Hz band frequency synthesizers is expected.

On the other hand, as a CMOS-structured static flip-flop with excellent operational stability, the one shown in FIG. 6 has been used. In the figure, transfer gates 61, 62, 65, 66 and inverters 63, 64
, 67, 68, 69, and 70 all have a CMOS configuration consisting of a P-channel transistor and an N-channel transistor. The inverter 64 and the transfer gate 62 constitute a feedback circuit with respect to the inverter 63, and have a function of holding a signal on the master side when the transfer gate 62 is in a conductive state. Similarly, inverter 67
, 68 and the transfer gate 66 have a function of holding a signal on the slave side when the transfer gate 66 is in a conductive state. Output Q on the slave side is inverted by inverter 69 and fed back to input D. CMOS inverter 7
0 constitutes a buffer circuit for obtaining an inverted signal C' of the clock signal C for controlling each of the transfer gates.

In the circuit shown in FIG. 6, the initial state is that the clock signal=H (high level) and the output Q=L (low level).
level). Since the transfer gate 61 becomes conductive and the transfer gate 62 becomes non-conductive, the inverter 63 on the master side receives an input of 'H' level and outputs 'L' level. On the other hand, on the slave side, the transfer gate 65 is in a non-conductive state,
Since the transfer gate 66 becomes conductive, the signal transmission path with the master side is cut off, and the output Q is maintained at a low level.

Next, when the clock signal changes to the 'L' level, the transfer gates 61 and 66 become non-conductive;
Transfer gates 62 and 65 become conductive. As a result, the 'L' level signal is held on the master side, and the transfer gate 6 is transferred from the master side to the slave side.
5, an 'L' level signal is transmitted. Therefore,
Output Q changes from 'L' level to 'H' level.

Next, when the clock signal changes to 'H' level, transfer gates 61 and 66 become conductive and transfer gates 62 and 65 become non-conductive. As a result, the 'H' level signal is held on the slave side, and the 'L' level signal is fed back to the input D from the slave side to the master side via the inverter 69. In order to repeat the same change due to the above clock signal change, as shown in Fig.
The circuit operation is as shown in the waveform diagram of FIG. FIG. 3 shows the dependence of the maximum divided operating frequency on the power supply voltage when the above circuit is constructed using a CMOS process having a gate length of 0.2 μm class. It is possible to operate at 2 GHz with a power supply voltage of 2 V, and because it has a flip-flop element that performs a signal holding operation, stable operation is possible from low frequencies.

[0014]

However, the conventional dynamic flip-flop shown in FIG. 4 has a problem in that the stability of its operation deteriorates as the frequency of the clock signal decreases. As described in the operation description above, signal retention by the flip-flop element is achieved by combining the source-drain junction capacitance Cj of the CMOS inverter 63 (or 67) and the gate capacitance output Cg of the next-stage CMOS inverter 67 (or 69). This is done by the charge stored in the capacitor Cl (=Cj+Cg). However, the accumulated charge decreases over time due to leakage current in the source-drain junction and gate oxide film, so as the signal period becomes longer, the maintained signal level decreases, eventually reaching the logic threshold of the next stage inverter. It becomes below. As a result, the inverter at the next stage is inverted and malfunctions. This period becomes more serious as the power supply voltage decreases, as the amount of charge charged to the composite capacitance Cl (=Cj+Cg) decreases. As described above, the conventional CMOS dynamic flip-flop has excellent high speed performance, but has a problem in stable operation at low frequencies.

On the other hand, the conventional static type flip-flop shown in FIG. 6 has a larger number of elements and an increased parasitic capacitance than the dynamic type, so its high-speed operation performance is poor as shown in FIG. Even with technology, 3G
It is difficult to apply this method to frequency synthesizers of small Hz-band mobile phones. Under these circumstances, there has been a need for CMOS flip-flop circuit technology that operates in the GHz band with a low power supply voltage and operates stably without depending on the operating frequency.

[0016] An object of the present invention is to provide a C
It is an object of the present invention to provide a static CMOS flip-flop circuit capable of operating at a high speed comparable to that of a CMOS dynamic flip-flop while having the advantages of a MOS static flip-flop circuit.

[0017]

[Means for Solving the Problems] In order to achieve the above object, the present invention improves the characteristics of the transfer gate that determines the operating speed in a CMOS static flip-flop circuit with excellent operational stability. improve,
The main structural feature is that a circuit means is provided to reduce the load capacity of the inverter constituting the flip-flop element.

00018

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a circuit diagram showing the same embodiment when the transfer gate is configured with CMOS.
It consists of a flip-flop circuit and a slave flip-flop circuit. That is, in the master flip-flop, the input and output terminals of CMOS inverter 1 are P-type channel MOS.
C through CMOS transistor gates 3 and 4 composed of a transistor and an N-type channel MOS transistor.
It is interconnected to the input and output terminals of the MOS inverter 2 to form a flip-flop element. Similarly, in the slave flip-flop, the input and output terminals of the CMOS inverter 5 are connected to the CM through the CMOS transfer gates 7 and 8.
It is interconnected to the input and output terminals of the OS inverter 6 to form a flip-flop element. The above commercial on the master side
The output signals of OS inverters 1 and 2 are transmitted to the input sides of slave-side CMOS inverters 5 and 6 via CMOS transfer gates 9 and 10, respectively. On the other hand, the output signals of CMOS inverters 5 and 6 on the slave side are CMOS
The signal is fed back via transfer gates 11 and 12 to the input terminals of CMOS inverters 1 and 2 on the master side. The positive phase timing pulse is transferred to transfer gates 7, 8, 1.
1, 12 PMOS and transfer gates 3, 4,
9 and 10, respectively, and on the other hand, a timing pulse with the opposite phase to the above timing pulse is supplied to the CMOS gate.
It is generated through an inverter 15 and supplied to the PMOS gates of transfer gates 3, 4, 9, and 10 and the NMOS gates of transfer gates 7, 8, 11, and 12, respectively. CMOS inverters 13 and 14 each constitute a buffer circuit that supplies outputs Q' and Q, respectively.

In explaining the circuit operation of FIG. 1, the initial state is the same as that of FIG. 6, that is, the clock signal is
(high level) and output Q=L (low level). Transfer gates 3, 4, 9, and 10 are in a conductive state, and transfer gates 7, 8, 11, and 12 are in a non-conductive state. The flip-flop element on the master side is in a signal holding state, and 'H' level and 'L' level signals are sent to the slave side CMOS inverters 5, 6 via the transfer gates 9, 10 which are in a conductive state. Each is being communicated. Also, C on the slave side
The outputs of the MOS inverters 5 and 6 are fed back to the flip-flop element on the master side.

Next, when the clock signal changes to ``L'' level, transfer gates 3, 4, 9, and 10 become non-conductive, and transfer gates 7, 8, 11, and 12 become conductive. As a result, the flip-flop element on the slave side is in a signal holding state, and 'L' and 'H' level signals are transmitted from the CMOS inverters 5 and 6 via the conductive transfer gates 12 and 11. The signals are fed back to the CMOS inverters 2 and 1 on the master side, respectively. Output Q is still at 'L' level.

Next, when the clock signal changes to ``H'' level, transfer gates 3, 4, 9, and 10 become conductive, and transfer gates 7, 8, 11, and 12 become non-conductive. The flip-flop element on the master side is in a signal holding state, and the transfer gates 9 and 10 are in a conductive state from the CMOS inverters 1 and 2.
``L'' level and ``H'' level signals are transmitted to slave side CMOS inverters 5 and 6, respectively. As a result, the output Q is inverted to an 'H' level signal. Since similar changes are repeated due to changes in the clock signal as described above, the circuit operation of FIG. 1 becomes as shown in the waveform diagram of FIG. 2.

The above is a brief explanation of the operation of the static flip-flop of the present invention, and the reasons why it operates faster than the conventional static flip-flop shown in FIG. 6 can be summarized into the following three points.

The first point is to increase the speed of signal transmission in transfer gates 9, 10, 11, and 12, which are responsible for signal transmission between flip-flop elements. In the circuit of the present invention, the potential difference between the ends of the transfer gate immediately before the transition from the non-conducting state to the conducting state (corresponding to the source-drain voltage of the MOS transistor constituting the transfer gate) is always approximately equal to the power supply voltage. (corresponding to the potential difference between High level and Low level). Therefore, a large current flows immediately after the timing pulse changes and the gate becomes conductive, so the next stage CMOS
The gate capacity of the inverter can be charged and discharged in a short time. Figure 6
Unlike the circuit of the present invention, the potential difference between the ends of the transfer gates 61 and 65 in the conventional static flip-flop circuit shown in FIG.

The second point is to increase the speed of signal propagation by reducing the capacitive load of the CMOS inverters 1 and 2 constituting the flip-flop elements. In the conventional static flip-flop circuit shown in FIG. 6, the gate capacitance of the CMOS inverter 64 and the junction capacitance of the transfer gate 65 exist as capacitive loads of the CMOS inverter 63. On the other hand, in the circuit of the present invention, the capacitive loads of CMOS inverters 1 and 2 are transfer gates 9, 4 and 10, respectively.
The junction capacitance is 3. As transistors become smaller and gate oxide films become thinner, junction capacitance becomes smaller than gate capacitance. Therefore, when a circuit is configured with transistors of the same size, the load capacitance of the circuit of the present invention is smaller.

The third point is that since the circuit of the present invention transmits both phase signals in parallel between the master flip-flop and the slave flip-flop, in order to generate the inverted signal of the output Q necessary for the frequency division operation, There is no need to use a CMOS inverter. As shown in FIG. 7, the outputs of the CMOS inverters 5 and 6 are fed back to signal lines of opposite phase. On the other hand, in the conventional circuit, the reverse phase signal is fed back via the CMOS inverter 69. Furthermore, in the case where the output of the transfer gate 65 is fed back, two stages of transfer gates are required in the signal path, which makes the operation unstable and at the same time increases the signal delay because there is no driving force.

CMOS with gate length of 0.2 μm class
FIG. 3 shows the dependence of the maximum divided operating frequency on the power supply voltage when the above circuit is constructed using the process. At a power supply voltage of 2V or more, the device exhibits high-speed operation performance comparable to that of the dynamic flip-flop shown in FIG. Even at a power supply voltage of 2V or less, it exhibits higher high-speed performance than the conventional static flip-flop shown in FIG. In addition, since it involves a signal holding operation in principle, it exhibits stable performance even during low frequency operation.

[0027]

[Effects of the Invention] As explained above, by using the static CMOS flip-flop circuit of the present invention, stable operation is ensured regardless of the operating frequency, and high-speed frequency division operation of up to 3 GHz is achieved with a low power supply voltage of 2 V. becomes possible. This will make it possible to implement CMOS prescaler circuits, etc. used in frequency synthesizers, etc. of next-generation mobile communication devices, so ICs used in these devices will be
It is possible to realize complete CMOS implementation of the system, and it is possible to reduce the power consumption and cost of the system.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the embodiment in FIG. 1;

FIG. 3 is a power supply voltage dependence characteristic diagram of the maximum divided operating frequency of a conventional circuit and a circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional CMOS dynamic flip-flop circuit.

FIG. 5 is a signal waveform diagram for explaining the operation of the conventional example shown in FIG. 4;

FIG. 6 is a circuit diagram showing an example of a conventional CMOS static flip-flop circuit.

7 is a signal waveform diagram for explaining the operation of the conventional example shown in FIG. 6; FIG.

[Explanation of symbols]

1, 2, 5, 6 CMOS inverter 3, 4, 7, 8
,9,10,11,12 CMOS transfer gate

Claims (1)

[Claims] Claim 1: An output terminal of a first CMOS inverter is connected to an input terminal of a second CMOS inverter via a first transfer gate, and an output terminal of the second CMOS inverter is connected via a second transfer gate. a master flip-flop element connected to the input terminal of the first CMOS inverter, and a fourth CMOS inverter connected to the output terminal of the third CMOS inverter via a third transfer gate.
connected to the input terminal of the fourth CMOS inverter, and connected to the input terminal of the fourth CMOS inverter.
a slave flip-flop element configured by connecting an output terminal of an S inverter to an input terminal of the third CMOS inverter via a fourth transfer gate; The output ends of the CMOS inverters are connected to the input ends of the third and fourth CMOS inverters of the slave flip-flop element through fifth and sixth transfer gates, respectively, and the output ends of the CMOS inverters of the slave flip-flop element The output signals of the third and fourth CMOS inverters are transferred to the second and first CMOS inverters of the master flip-flop element through seventh and eighth transfer gates.
The timing pulses are fed back to the input terminals of the S inverters, and the timing pulses are fed back to the gates of the first, second, fifth, and sixth transfer gates, and the timing pulses having a phase opposite to the timing pulses are fed back to the gates of the third, fourth, and sixth transfer gates. 7. A static CMOS flip-flop circuit configured to be supplied to the gate of the eighth transfer gate.