JPH04208564A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To see that the margin of alignment and the margin of contact size can be taken large by forming, in self alignment, a capacity contact at the word line, which is made of the first polysilicon film having an oxide film at the upper surface and a side wall oxide film at the side. CONSTITUTION:An oxide film 105 and a first polysilicon film are etched in order to form a word line 104 consisting of a first polysilicon film, subsequently an oxide film for side wall is stacked all over the surface, and it is etched back to form a sidewall oxide film 106. At this stage, a capacity contact 108 and a bit contact are formed in self alignment to the word line 104. Next, the second interlayer insulating film 110 on the second polysilicon film 109 made on the contact film 108 is dry-etched to form a contact hole, subsequently a third polysilicon film 111 and an insulating film 110 are anisotropically etched. Hereby, the margin degree to the alignment of the capacity contact and, contact size, etc., become high.

Description

[Detailed description of the invention]

[00011

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a DRAM having a stacked cell structure. [0002] [0002] DRA having a conventional stacked cell structure
The manufacturing method of M has generally been carried out by the first method shown in FIGS. 11 to 13 or the second method shown in FIGS. 14 to 16. [00031 The first method shown in FIGS. 11 to 13 will be described. First, a semiconductor substrate 2 made of p-type silicon
01 surface has LOGO3 oxide film 2O2, gate oxide film 20
After depositing a first polysilicon film and diffusing phosphorus into it, an oxide film 205 is formed on its surface. Next, using a photoresist (not shown) as a mask, the oxide film 205. Word lines 20 made of the first polysilicon film are formed by sequentially etching the first polysilicon film.
form 4. Subsequently, after removing the photoresist and implanting low concentration n-type impurity ions, a sidewall oxide film is deposited on the entire surface and then etched back to form a sidewall oxide film 206. . After forming an LDD-type impurity diffusion layer by ion-implanting high-concentration n-type impurities, a first interlayer insulating film 207 is deposited on the entire surface, and capacitance is etched using a photoresist (not shown) as a mask. FIG. 11] where the contact 208 is formed on the self-line. Next, a second polysilicon film 209 is deposited on the entire surface, and after making it n-type by diffusing phosphorus, a pattern of photoresist 212 is formed on the surface of the second polysilicon film 209 in the area where a charge storage node is to be formed. Form [Figure 12]. Next, the photoresist 212 is removed and the second polysilicon film 209 is anisotropically etched to remove the photoresist 212. The charge storage structure made of the second polysilicon film 209 is then completed. [FIG. 13]. [00041 The second method shown in FIGS. 14 to 16 will be explained. First, a semiconductor substrate 0 made of p-type silicon is
A LOCO3 oxide film 3O2 and a gate oxide film 33 are formed on one surface, a first polysilicon film is deposited, and a length is diffused therein. Apply photoresist (not shown) to the first layer using a mask.
By etching the polysilicon film, a word line 304 made of 21 polysilicon films is formed. Subsequently, the photoresist is removed, a low concentration n-type (impurity) ion is implanted, and an oxide film for sidewalls is deposited on the entire surface and then etched back to form an oxide film 306. After performing high concentration n-type (impurity ion implantation and forming an LDD type impurity diffusion layer),
A first interlayer insulating film 307 is deposited on the entire surface, and this layer 1 is planarized. Subsequently, a photo-l cyst 31 is deposited on the surface of the first interlayer insulating film 307 in an area other than the area where the capacitive contact is to be formed.
A mask pattern is formed according to 2 [FIG. 4]. Next, using the photoresist 312 as a mask, the first interlayer insulating film 307 is
Dry etching is performed to form a capacitive contact 308. Subsequently, after removing the photoresist 12, a second polysilicon film 309 is deposited on the entire surface, and this is made to be n-type by diffusion of phosphorus (FIG. 15).Subsequently, a photoresist (not shown) is applied using a mask. Second polysilicon film 309
Anisotropic etching is performed to form the second polysilicon film 309.
A charge accumulation node consisting of the following is completed (Fig. 16). [0005]

[Problems to be Solved by the Invention] In the first conventional semiconductor device manufacturing method described above, the capacitive contacts are connected to word 1.
An oxide film is formed on the word line 204 made of the first polysilicon film to form a self-line for the word line 204:
05 is formed, so the word line 204 portion is 2h.
It has a structure. Part of the word line 204 (
Since the film is thick, the step difference in this part becomes large, and the aspect ratio between war lines also becomes large. On the other hand, in order to obtain sufficient capacitance, it is necessary to increase the surface area of the charge storage node.For this purpose, it is necessary to increase the thickness of the second silicon film 209, which becomes the charge storage node. If,
In the part covering the step based on the word line 204 (
The thickness of the second polysilicon film 209 becomes particularly thick. When phosphorus is expanded into the second polysilicon film 209 having such a shape, the phosphorus concentration in the thicker part of the film becomes lower than the word line 0.
It becomes lower than the phosphorus concentration of 4. The charge storage node must be formed by anisotropic etching that minimizes the dimensional change from the mask design value in order not to reduce the capacitance. This means that, for example, the second polysilicon film 209, which has a low phosphorus concentration and is thick, formed on the region between the word lines that becomes a pit contact and in the part that spans the step portion based on the word line 204, It is difficult to perform etching with good dimensional accuracy without leaving any polysilicon residue on the stepped portion. [0006] Furthermore, in the second conventional semiconductor device manufacturing method described above, the second polysilicon film 3 for the charge storage node is
Since the lower part of 09 is flattened by the first interlayer insulating film 307, etching of the second polygonal film 309 for forming a charge storage node is easy. However, since the capacitive contact is not formed in a self-aligned manner with respect to the word line 304, there are problems in that there is little margin for alignment when forming the contact, and in that a fine contact hole must be formed. [0007]

[Means for Solving the Problems] In order to solve the problems of the prior art, the method for manufacturing a semiconductor device of the present invention provides a capacitor contact having an oxide film on the upper surface and a sidewall oxide film on the side surface. A step of forming a self-line on the word line formed by the first polysilicon film, a step of removing the first interlayer insulating film on the capacitive contact after forming the first interlayer insulating film, and a step of removing the first interlayer insulating film on the capacitive contact. a step of forming a second polysilicon film, a step of diffusing phosphorus into the second polysilicon film, a step of forming a second interlayer insulating film and planarizing it, and a step of etching back the second interlayer insulating film. , a step of removing the second interlayer insulating film on the capacitive contact, a step of forming a third polysilicon film, a step of diffusing phosphorus into the third polysilicon film, using a photoresist as a mask,
Third polysilicon film 7 Anisotropic etching is performed on the three layers of the second interlayer insulating film under the third polysilicon film and the second polysilicon film to form a charge storage node. There is. [00081

[Example] Next, the present invention will be explained with reference to the drawings. 1 to 7 are cross-sectional views for explaining a first embodiment of the present invention, and these figures are shown in the order of steps. [0009] First, a LOCO3 oxide film 102. is formed on the surface of a semiconductor substrate 101 made of p-type silicon. Gate oxide film 1
After a first polysilicon film is deposited and phosphorus is diffused into it, an oxide film 105 is formed on its surface. Next, using a photoresist (not shown) as a mask, the oxide film 105. Word lines 1 made of the first polysilicon film are formed by sequentially etching the first polysilicon film.
Form 04. Subsequently, after removing the photoresist and implanting low concentration n-type impurity ions, a sidewall oxide film is deposited on the entire surface and then etched back to form a sidewall oxide film 106. . At this stage, capacitive contact 108. and bit contacts are formed on the self-line to the word line 104. Perform ion implantation of high concentration n-type impurity
After forming the DD type impurity diffusion layer, the first interlayer insulating film 107 is deposited on the entire surface, and the first interlayer insulating film 107 on the capacitive contact 108 is removed by etching using a photoresist (not shown) as a mask. [Figure 1] [00101 Next, after depositing a second polysilicon film 109 with a thickness of, for example, 100 cm, the second polysilicon film 1
In step 09, phosphorus is diffused to make the layer resistance of the second polysilicon film 109 about 60Ω/R. Subsequently, a BPSG film, for example, is deposited by about 1.011 mm as the second interlayer insulating film 110, and the second interlayer insulating film 110 is formed by a glue flow at 900°C.
flatten the surface [Figure 2]. [00111 Next, the second interlayer insulating film 110 is etched back, and a film of 100 to 150 nm is etched back on the second polysilicon film 109.
The second interlayer insulating film 110 having a thickness of about 100 m is left (FIG. 3). [0012] Next, a second interlayer insulating film 110 is formed on the second polysilicon film 109 formed on the capacitive contact 108.
Dry etching is performed to form contact holes. Subsequently, a third polysilicon film 1 having a thickness of, for example, 800 nm is formed.
11 is formed, phosphorus is diffused therein, and heat treatment is performed in a nitrogen atmosphere at 900° C. so that phosphorus becomes uniform in the third polysilicon film 111 (FIG. 4). [0013] Next, using the photoresist 112 as a mask, the third polysilicon film 111. Next, the second interlayer insulating film 1
10 is anisotropically etched. A second polysilicon film]0 is used as an etching stopper for the second interlayer insulating film 110.
9 is used [Figure 5]. [00141] Next, the second polysilicon film 109 is removed by anisotropic etching. At this time, since the second polysilicon film 109 is thin, it is etched so that no polysilicon remains at the stepped portions (FIG. 6). [00151 Finally, the photoresist film 112 is removed. As a result, the second polysilicon film 109. Second interlayer insulating film 110. A charge storage node consisting of the third polysilicon film 111 is formed (FIG. 7). [0016] FIGS. 8 to 10 are cross-sectional views for explaining the second embodiment of the present invention, and these views are shown in the order of steps. The basic steps and structure of this embodiment are the same as those of the first embodiment of the present invention. The following description will focus on steps different from those in the first embodiment of the present invention. [00171 First, FIG. 2 in the first embodiment of the present invention
After forming the structure shown in FIG. 8, a coated oxide film 113 is formed on the second interlayer insulating film 110, and the surface is completely planarized (FIG. 8). [00181 Next, apply oxide film 113. Then, the second interlayer insulating film 110 is etched back so that the second interlayer insulating film 110 with a thickness of about 100 to 150 nm remains on the second polysilicon film 109 (FIG. 9). [00191] Thereafter, by going through the steps shown in FIGS. 4 to 7, the charge storage node is completed [FIG. 10]. [0020] In this embodiment, since the coated oxide film 113 is formed and the surface is completely flattened, the elatin backing is performed, so that it is not possible to completely flatten the base of the thick third polysilicon film 111. Patterning of photoresist for formation of electrode storage node, third polysilicon film 1
This has the advantage that etching of No. 11 becomes easier. [00211] [Effects of the Invention] As explained above, in the present invention, since a capacitive contact is formed in a self-line with respect to a word line, when forming a contact hole again in this part, there is no need for alignment margin and contact size. You can have a lot of leeway. In addition, although there is a large step difference due to the word lines etc. on the area that will become the bit contact sandwiched between word lines, first a thin second polysilicon film is formed, and then a second polysilicon film is formed on it.
In order to flatten the interlayer insulating film, a thick third policy J is used.
Processing of the membrane can be done easily. Furthermore, the second
Since the charge storage node is formed by etching the thin second polysilicon film after etching the interlayer insulating film, the risk of residual polysilicon is avoided.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an intermediate process for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 4 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 5 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 6 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 7 is a sectional view of the final step for explaining the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of an intermediate step for explaining a second embodiment of the present invention.

FIG. 9 is a sectional view of an intermediate process for explaining a second embodiment of the present invention.

FIG. 10 is a sectional view of the final step for explaining the second embodiment of the present invention.

FIG. 11 is a cross-sectional view of an intermediate process for explaining a first example of the conventional technology.

FIG. 12 is a sectional view of an intermediate process for explaining a first example of the conventional technology.

FIG. 13 is a sectional view of the final step for explaining a first example of the conventional technique.

FIG. 14 is a sectional view of an intermediate process for explaining a second example of the conventional technology.

FIG. 15 is a sectional view of an intermediate process for explaining a second example of the conventional technique.

FIG. 16 is a sectional view of the final step for explaining a second example of the conventional technique.

[Explanation of symbols]

101.201,301 Semiconductor substrate 102.20
2,302 LOCO3 oxide film 103.203,3
03 Gate oxide film 104.204,304
Word line 105.205, 305 Oxide film 106.206, 306 Sidewall oxide film 1
07.207,307 First interlayer insulating film 108.2
08,308 Capacitive contact 109.209,3
09 Second polysilicon film 110 Second interlayer insulating film 111 Third polysilicon film 112, 212, 312 Photoresist 213
Coated oxide film

Claims (1)

[Claims] 1. In the step of forming a DRAM stack cell on a semiconductor substrate, a word line is formed using a first polysilicon film having an oxide film on the upper surface and a sidewall oxide film on the side surfaces, and a capacitive contact is formed. a step of forming a self-aligned film with respect to the word line; a step of forming a first interlayer insulating film; a step of removing the first interlayer insulating film on the capacitor contact; and a step of forming a second polysilicon film. , a step of diffusing phosphorus into the second polysilicon film, a step of forming and planarizing a second interlayer insulating film, a step of etching back the second interlayer insulating film, and a step of covering the capacitive contact. forming a contact hole in the second interlayer insulating film on the second polysilicon film in the portion; forming a third polysilicon film; and diffusing phosphorus into the third polysilicon film. , using a photoresist as a mask, perform anisotropic etching on three layers: the third polysilicon film, the second interlayer insulating film under the third polysilicon film, and the second polysilicon film; 1. A method of manufacturing a semiconductor device, comprising: forming a charge storage node.