JPH04207055A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the capacitance between wirings, minimize time constant during charge/discharge time and ensure a high speed operation of devices and circuits by installing a cavity on an insulation film between wirings which connect said devices. CONSTITUTION:First and second interlayer films 6 and 7 of CVD oxide films are deposited between a first wiring layer 4 and a second wiring layer 5. A silica-made wiring interlayer insulation 14 is buried in the first wiring layer in order to flatten the level difference of the first wiring layer and maintain the evenness of the first wiring layer bed. On the side wall of the first wiring layer 4, there is formed a CVD oxide film-based side wall insulation film 9 where a cavity 10 is formed between the specified wiring layers 4. A wiring to wiring capacitance of the first wiring layers 4 is reduced compared with a case when there is no cavity provided. Furthermore, a higher speed operation of the devices is ensured. In addition, with regards to the first wiring layers 4 where the wiring to wiring capacitance is not so important, no cavity is provided between the wirings. The wiring interlayer insulation film 14 is made to remain while the structural strength is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having an insulating film between wirings formed on a semiconductor substrate, and a method for manufacturing the same.

A conventional multilayer wiring structure and its formation method will be explained with reference to the drawings.

FIG. 3 is a sectional view thereof. In the figure, a semiconductor substrate 1
1 has a substrate protection insulating film 2 made of a CVD oxide film on the surface of a substrate on which elements have been formed.

First, a contact hole 3 is formed in the substrate protection insulating film 2 by photolithography. Next, metal such as aluminum is deposited on the semiconductor substrate 1 in which the contact holes have been formed by vapor deposition or sputtering, and patterned by photolithography to form the first layer wiring 4. After forming the first layer wiring 4, a first interlayer insulating film 6 is deposited by CVD method or the like. Next, in order to flatten the surface, a silica coating liquid is applied to the surface by a spin-on method, and after baking, the entire surface is dried. Etching is performed, the depression between the first layer wirings 4 and 4 is filled with a flattening insulating film 14 made of silica, and further CV
A second interlayer insulating film 7 is deposited by method D, and the interlayer film forming process is completed.

Next, the first layer wiring 4 formed earlier and the second layer wiring 4 formed next.
After forming through holes 8 for connecting layer wiring 5 by photolithography, metal such as aluminum is deposited by vapor deposition or sputtering, and patterning is performed by photolithography to form second layer wiring 5. It is formed on the interlayer insulating film 7.

The layers above the third layer wiring are formed up to the required number of layers by repeating the above steps.Finally, a cover insulating film 11 for surface protection is formed, and a window 13 for bonding is opened in the bonding pad portion 12. After completing the cover hole drilling process, the wiring process is completed.

By the way, in the wiring structure described above, as the dimensions of elements, wiring, and inter-wirings become smaller, the capacitance between wirings can no longer be ignored with respect to the high-speed operation of elements and circuits. There was a problem that the operation could not be realized.

In order to solve the above-mentioned problems, a semiconductor device of the present invention is characterized in that, in a semiconductor device having wirings connecting elements, a cavity is provided in an insulating film between the wirings.

Further, in the method of manufacturing a semiconductor device of the present invention, an insulating film sidewall is formed on the wiring, an insulating film having a higher etch rate than the insulating film is buried, and then an insulating film having an etch rate lower than the insulating film having a higher etch rate is further provided. After laminating the insulating film, a gap forming step is performed in which a window is opened to reach the insulating film with a high etch rate, and the insulating film with a high etch rate is removed by etching to form a void in the buried portion, and an insulating film is further laminated. The method is characterized in that it includes a cavity forming step of forming a cavity in the insulating film by closing the window.

In the semiconductor device having the above structure, even if a high-frequency current flows through the wiring connected to a required element during high-speed operation, the capacitance between the wirings is reduced due to the cavities formed between the wirings.
The charging/discharging time constant becomes small, ensuring high-speed operation of elements and circuits.

Further, in the method for manufacturing a semiconductor device of the present invention, in a semiconductor substrate on which an element is formed, an insulating film sidewall is formed on the wiring, and the space between the wirings is filled with an insulating film having a larger etch layer than the insulating film sidewall, and further, as described above. After stacking an insulating film with a lower etch rate than an insulating film with a higher etch rate, a window is opened that reaches the insulating film with a higher etch rate, and the insulating film with a higher etch rate is removed by etching to form a void. can. After forming the void,
When an insulating film is further laminated in the cavity forming step, the window is closed and a cavity can be formed in the inter-wiring insulating film.

misfortune Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. In the figure, a semiconductor substrate 1 has a substrate protection insulating film 2 made of a CVD oxide film on the surface of the substrate on which elements have been formed.
It has the following. The contact hole 3 is a window formed in the substrate protection insulating film 2 by photolithography. The first layer wiring 4 and the second layer wiring 5 are formed by depositing aluminum by sputtering and patterning by photolithography. A first interlayer insulating film 6 and a second interlayer insulating film 7 made of CVD oxide films are deposited, and in order to reduce the level difference of the first layer wiring and ensure the flatness of the base of the first layer wiring, a wiring made of silica is deposited. An interlayer insulating film 14 is embedded between the first layer wirings.

Further, the first layer wiring 4 and the second layer wiring 5 are connected through a through hole 8 formed by opening a window in the first interlayer insulating film 6 and the second interlayer insulating film 7 by photolithography. 1st
A side wall insulating film 9 made of a CVD oxide film is formed on the side wall of the layer wiring 4, and a cavity 10 is formed between predetermined first layer wirings 4, 4.

Further, a cover insulating film 11 made of a CVD oxide film is deposited on the top layer of this semiconductor device, and a bonding window 13 is opened in the cover insulating film 11 in the bonding pad portion 12 by photolithography. are doing.

In such a semiconductor device, the inter-wiring capacitance of the first layer wiring 4 is reduced compared to a case without a cavity, and high-speed operation of the device is ensured. In addition, the first
Regarding the layered wiring 4, no cavities are formed between the wirings, and the interwiring insulating film 14 is left to ensure structural strength.

Specifically, the semiconductor device of the present invention is manufactured in the following order. That is, as shown in FIG. 2(A), aluminum is deposited by sputtering on the semiconductor substrate 1 in which contact holes 3 have already been opened, and first layer wiring 4 is formed by photolithography. Next, as shown in FIG. 2(b), after depositing an oxide film that will become the insulating film 9 for forming a sidewall insulating film by the CVD method, the surface of this insulating film 15 for forming a sidewall insulating film is etched by anisotropic dry etching. The entire surface is etched, and Figure 2 (c)
A sidewall insulating film 9 is formed as shown in FIG. Next, as shown in FIG. 2(d), silica is applied over the entire surface by a spin-on method and baked to form an inter-wiring insulating film 14. Then, as shown in FIG. 2(e), the film thickness B of the inter-wiring insulating film 14 is reduced by anisotropic dry etching with a sufficient selection ratio between the inter-wiring insulating film 14 and the sidewall insulating film 9. Etching is performed until the side wall insulating film 9 is about 3/4 of the dimension A below. Next, as shown in FIG.
After depositing the oxide film that will become the first interlayer insulating film 6 by the VD method,
A photoresist 18 is applied to the first interlayer insulating film 6, and a cavity forming window 16 reaching the interwiring insulating film 14 is opened by photolithography by anisotropic dry etching. ), the inter-wiring insulating film 14 is etched from the cavity forming window 16 by wet etching,
A gap 17 is formed between the first layer wirings 4, 4. Next, as shown in FIG. 2(H), the second interlayer insulating film 7 is
Deposit an oxide film and use the overhang to form the first
A cavity 10 is formed by closing the cavity forming window 16 opened in the interlayer insulating film 6. Next, as shown in FIG. 2, through holes 8 are opened at predetermined positions by photolithography, aluminum is deposited by sputtering, and second layer wiring 5 is formed by photolithography. form. Finally CVD
An insulating film that will become the cover insulating film 11 is deposited by a method, and a bonding window 13 is opened in the bonding pad portion 12 to complete the entire process.

According to the above manufacturing method, the semiconductor substrate 1 on which elements are formed
A cavity can be reliably formed between the upper predetermined first layer wirings 4, 4.

Further, although the present invention has been described regarding the formation of a cavity between the first layer wirings 4, 4, by applying a similar process to the second layer wiring or higher, a cavity can be formed between a predetermined second layer wiring. be.

! Results As is clear from the above description, the semiconductor device of the present invention reduces the inter-wiring capacitance, which is a problem during high-speed operation of elements and circuits, by using the cavity formed in the inter-wiring insulating film, and the device It is also possible to provide a semiconductor device that ensures high-speed circuit operation.

Further, according to the manufacturing method of the present invention, it is possible to reliably form a cavity in the inter-wiring insulating film.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an embodiment of a semiconductor device of the present invention, and FIGS. 3 is a schematic cross-sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film for substrate protection, 3... Contact hole, 4... First layer wiring, 5... ...Second layer wiring, 6...First interlayer insulating film, 7...Second interlayer insulating film, 8...Through hole, 9... Side wall insulating film, 10...Cavity, 1-1...Cover insulating film, 12...Ponding pad, Step 3...
・Window for bonding pad, 14... Insulating film between wiring, 15... Insulating film for forming side wall insulating film, 16...
...Void, window for cavity formation, 17...Void, 18...Resist, 19...Insulating film for planarization. Patent applicant Kansai NEC Co., Ltd. 1 Figure 1 Chiku 2 Figure) 2 Figure 113

Claims (2)

[Claims] (1) A semiconductor device having wiring connecting elements, characterized in that a cavity is provided in an insulating film between the wirings. (2) In a semiconductor substrate on which elements and wiring are formed, a step of forming a sidewall insulating film on the wiring and embedding between the wirings with an insulating film having a higher etch rate than the sidewall insulating film; After embedding the membrane,
Furthermore, after laminating an insulating film with a lower etch rate than the insulating film with a higher etch rate, a window is opened that reaches the insulating film with a higher etch rate, and the insulating film with a higher etch rate is removed by etching to fill the buried portion. A method for manufacturing a semiconductor device, comprising: a void forming step of forming a void; and a cavity forming step of forming a void in the insulating film between the wirings by further laminating an insulating film to close the window. .