JPH04206867A - Semiconductor dynamic ram - Google Patents
Semiconductor dynamic ramInfo
- Publication number
- JPH04206867A JPH04206867A JP2337442A JP33744290A JPH04206867A JP H04206867 A JPH04206867 A JP H04206867A JP 2337442 A JP2337442 A JP 2337442A JP 33744290 A JP33744290 A JP 33744290A JP H04206867 A JPH04206867 A JP H04206867A
- Authority
- JP
- Japan
- Prior art keywords
- line
- conductor
- vss
- power
- supply voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体ダイナミックＲＡＭにおける電源ノイ
ズの低減に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to reduction of power supply noise in semiconductor dynamic RAM.
第３図は従来のアルミ電源線（以下Ｖｃｅ線と呼ぶ）を
示したパターン図であり、ｖＣＣ線ｆｌ）とＧＮＤ線（
以下Ｖｓｓ線と呼ぶ）（２）は平行（ａ）図、または重
なっていた（ｂ）図。Fig. 3 is a pattern diagram showing a conventional aluminum power supply line (hereinafter referred to as Vce line), with a vCC line fl) and a GND line (
(hereinafter referred to as the Vss line) (2) is a parallel view (a) or an overlapping view (b).
Ｖｃｅ線（１）のノイズ対策はＶｃｅ線（１）とＶｓｓ
線（２）のアルミ幅を大きくすることによって行ってい
た。Vce line (1) noise countermeasures are Vce line (1) and Vss
This was done by increasing the aluminum width of line (2).
従来の半導体ダイナミックＲＡ、 Ｍは以上のようにア
ルミ線を太くしないといけないので、半導体集積回路（
以下ＩＣと呼ぶ）のチップ面積が大きくなってしまい又
太くするｔｌけでは容易に、ノイズが消ぜないという問
題点があった。Conventional semiconductor dynamic RA, M requires thick aluminum wire as described above, so semiconductor integrated circuits (
There is a problem in that the chip area (hereinafter referred to as IC) becomes large, and noise cannot be easily eliminated by increasing the thickness.
この発明は上記のような問題点を解決するためになされ
たもので、Ｖｃｅ線のノイズを低減することのできる半
導体ダイナミックＲＡ、 Ｍを得ろ乙とを目的とする。This invention was made to solve the above-mentioned problems, and its object is to obtain a semiconductor dynamic RA, M that can reduce noise on the Vce line.
し課題を解決するための手段〕
この発明に係る半導体ダイナミックＲＡＭは、Ｖｃｅ線
とＶｓｓ線をツイストしたものである。Means for Solving the Problem] A semiconductor dynamic RAM according to the present invention has a twisted Vce line and a Vss line.
乙の発明におけるＶｃｅ線またはＶｓｓ線は、ノイズＩ
・させることによりＶｃｅ線、Ｖｓｓ線間に寄生容量が
生し、その容量のカプリングによって電源ノイズを低減
することが出来る。The Vce line or Vss line in B's invention is noise I
- By doing so, a parasitic capacitance is generated between the Vce line and the Vss line, and power supply noise can be reduced by coupling this capacitance.
以下、この発明一実施例を図について説明する。 An embodiment of this invention will be described below with reference to the drawings.
第１図はこの発明の一実施例であるＶＣｃ線Ｖｓｓ線の
パターン図で、図において、（１）ばアル５Ｖｃｃ線、
（２）はアルミＶｓｓ線、（３１＋コ′２つの異なるア
ルミを連結するコンタクト（以下スルホールと呼ぶ）で
ある。FIG. 1 is a pattern diagram of a VCc line and a Vss line according to an embodiment of the present invention.
(2) is an aluminum Vss wire, (31+C') a contact (hereinafter referred to as a through hole) that connects two different aluminum wires.
次に動作について説明する。Next, the operation will be explained.
図に示すように、２層アルミパターン作成プロセス技術
を使い、Ｖｃｅ線（１）、Ｖｓｓ線（２）を図示の如く
ツイストさせ、この時に出来るＶｃｃ−Ｖｓｓ間寄生容
量のカプリングを利用して、電源ノイズを低減させるこ
とが出来る。As shown in the figure, the Vce line (1) and Vss line (2) are twisted as shown in the figure using the two-layer aluminum pattern creation process technology, and the coupling of the parasitic capacitance between Vcc and Vss that is created at this time is used to Power supply noise can be reduced.
なお上記実施例では、Ｖｃｅ線（１）、Ｖｓｓ線（２）
のツイストを第１図のようにした場合を示したが、第２
図のようにしても同様の効果が得られる。In the above embodiment, the Vce line (1) and the Vss line (2)
Figure 1 shows the case where the twist is as shown in Figure 1, but the second
A similar effect can be obtained by doing as shown in the figure.
〔発明の効果〕
以上のように乙の発明によれば、電源線（Ｖｃｅ線Ｖｓ
ｓ線）をツイストさぜることによって電源ノイズを低減
することができろという効果がある。[Effect of the invention] As described above, according to the invention of Party B, the power supply line (Vce line Vs
Twisting the S-line has the effect of reducing power supply noise.
第１図はこの発明の一実施例である電源のパターンを示
す平面図、第２図はこの発明の他の実施例を示す電源線
パターンの平面図、第３図（、）（ｂ）は従来の電源線
パターンの平面図である。図において、（１）はアル５
Ｖｃｃ線、ｆ２］ ｉＪアルミＶｓｓ線、（３）はスル
ーホールを示す。
なお、図中、同一符号は同一、または相当部分を示す。Fig. 1 is a plan view showing a power supply pattern according to an embodiment of the present invention, Fig. 2 is a plan view showing a power supply line pattern showing another embodiment of the invention, and Figs. FIG. 3 is a plan view of a conventional power line pattern. In the figure, (1) is Al5
Vcc line, f2] iJ aluminum Vss line, (3) indicates a through hole. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
導体装置において、前記電源電圧線をツイストしたこと
を特徴とする半導体ダイナミックＲＡＭ。1. A semiconductor dynamic RAM, characterized in that, in a two-layer aluminum process semiconductor device having a power supply voltage line and a GND line, the power supply voltage line is twisted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2337442A JPH04206867A (en) | 1990-11-30 | 1990-11-30 | Semiconductor dynamic ram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2337442A JPH04206867A (en) | 1990-11-30 | 1990-11-30 | Semiconductor dynamic ram |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04206867A true JPH04206867A (en) | 1992-07-28 |
Family
ID=18308674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2337442A Pending JPH04206867A (en) | 1990-11-30 | 1990-11-30 | Semiconductor dynamic ram |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04206867A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007533258A (en) * | 2004-04-12 | 2007-11-15 | ソニー エリクソン モバイル コミュニケーションズ， エービー | A wireless communication device including a circuit board on which a partially superimposed conductor is mounted connected to a power source and a power amplifier system |
-
1990
- 1990-11-30 JP JP2337442A patent/JPH04206867A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007533258A (en) * | 2004-04-12 | 2007-11-15 | ソニー エリクソン モバイル コミュニケーションズ， エービー | A wireless communication device including a circuit board on which a partially superimposed conductor is mounted connected to a power source and a power amplifier system |
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