JPH04206837A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04206837A JPH04206837A JP2338171A JP33817190A JPH04206837A JP H04206837 A JPH04206837 A JP H04206837A JP 2338171 A JP2338171 A JP 2338171A JP 33817190 A JP33817190 A JP 33817190A JP H04206837 A JPH04206837 A JP H04206837A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- manufacturing
- semiconductor device
- semiconductor
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、透光性基板の上に低温(< 600℃)で薄
膜トランジスタ(以下TPTと称する)を形成する半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a thin film transistor (hereinafter referred to as TPT) is formed on a transparent substrate at a low temperature (<600° C.).
従来の技術
多結晶シリコンを゛1′−導体層に用いたi゛F Tに
おいて多結晶シリコンの形成方法には、石英等の基板の
七にL P −CV D (Low Pressure
−ChemicalVapor Deposition
:低圧化学気相堆積)法等により600℃以上の温度で
直接多結晶シリコン薄膜を堆積する方法と水素化アモル
ファスシリコン薄膜等をレーザー光等のエネルギー源を
用いて溶融。Conventional technology The method for forming polycrystalline silicon in an iF T using polycrystalline silicon as the conductor layer includes applying L P -CV D (Low Pressure) to a substrate such as quartz.
-Chemical Vapor Deposition
A method of directly depositing a thin polycrystalline silicon film at a temperature of 600°C or higher using a low-pressure chemical vapor deposition method, etc., and a method of melting a hydrogenated amorphous silicon thin film using an energy source such as a laser beam.
多結晶化して多結晶シリコン窒化膜を形成する方法があ
る。There is a method of forming a polycrystalline silicon nitride film by polycrystallization.
またレーザー光を用いて溶融、結晶化を行ない多結晶シ
リコンT P Tを作製する場合、素子の構成としては
ケート電極を半導体層の上部(チャネル領域が半導体層
の上部)に形成する順スターガ型か、またはコプレーナ
型が半導体層への1−ピングを容易に行なえるため主流
となっている。In addition, when producing polycrystalline silicon TPT by melting and crystallizing using laser light, the device configuration is a forward starga type in which the gate electrode is formed on the top of the semiconductor layer (the channel region is on the top of the semiconductor layer). Alternatively, the coplanar type is the mainstream because it allows easy 1-ping to the semiconductor layer.
発明が解決しようとする課題
しかしながら上記従来の直接基板の−1−に多結晶シリ
コン薄膜を堆積する方法で多結晶シリコンTPTを作製
する場合、基板を最低でも600 ’C程度に加熱する
必要があり、T FTに用いる基板か限定されてしまう
等の課題を有していた。Problems to be Solved by the Invention However, when manufacturing a polycrystalline silicon TPT using the above-mentioned conventional method of directly depositing a polycrystalline silicon thin film on a substrate, it is necessary to heat the substrate to at least 600'C. However, the number of substrates that can be used for TFTs is limited.
また従来の多結晶シリコンTPTの素子構成の主流であ
る順スクガ型、コプレーナ型ではゲート絶縁膜が半導体
層の−L部に形成されるため、半導体層を堆積した後に
ゲート絶縁膜を堆積するごとになる。しかし低温プロセ
スでTPTを作製する場合、ダメージの少ない熱酸化膜
等の高温プロセスを用いることができない。そこで、ゲ
ート絶縁■Qとして例えばプラズマCVD法でシリコン
窒化膜を堆積した場合、下地となる水素化アモルファス
シリコン薄膜表面にプラズマによるダメージを与えるこ
とになり良好なチャネルを形成することが困難であると
いう課題を有していた。これは、デーl−絶縁膜として
スパッタ法等で二酸化シリコン(S i O□)や酸化
クンタル(Ta20x)等を堆積したときにも同様なこ
とが言える。In addition, in the conventional polycrystalline silicon TPT device configurations, which are the mainstream type and the coplanar type, the gate insulating film is formed on the -L part of the semiconductor layer, so the gate insulating film is deposited after the semiconductor layer is deposited. become. However, when manufacturing TPT using a low-temperature process, it is not possible to use a high-temperature process such as a thermal oxide film that causes less damage. Therefore, if a silicon nitride film is deposited as the gate insulator Q by plasma CVD, for example, the plasma will damage the surface of the underlying hydrogenated amorphous silicon thin film, making it difficult to form a good channel. I had an issue. The same thing can be said when silicon dioxide (SiO□), quantal oxide (Ta20x), or the like is deposited as a dielectric film by sputtering or the like.
一方現行の水素化アモルファスシリコンを半導体層とし
て用いたTPTでは逆スタガ型を用いて作製する場合が
主流であり、この水素化アモルファスシリコンTPTの
半導体層を多結晶シリコン薄膜に置き換えた場合や多結
晶シリコンTPTと水素化アモルファスシリコンTFT
を同−MW上に構成する場合を考えると、類スタガ型や
コプレーナ型では現行プロセスとの整合性がとれないな
どの課題がある。On the other hand, current TPTs using hydrogenated amorphous silicon as the semiconductor layer are mainly manufactured using an inverted staggered type. Silicon TPT and hydrogenated amorphous silicon TFT
When considering the case of configuring the same MW on the same MW, the staggered type and coplanar type have problems such as inability to maintain consistency with the current process.
さらに、レーザー光照射による多結晶シリコンTPTで
はnチャネルまたはpチャネルトランジスタを作製する
際に、従来の方法では半導体層を堆積した後、チャネル
領域に不純物をトープする工程を導入すると成膜プロセ
スが複雑となり、マスク枚数が現行の逆スタガ型水素化
アモルファスシリコンTPTプロセスと比較してかなり
増加するという課題を有していた。Furthermore, when manufacturing n-channel or p-channel transistors using polycrystalline silicon TPT using laser light irradiation, the film formation process becomes complicated when conventional methods introduce a step of doping the channel region with impurities after depositing the semiconductor layer. Therefore, there was a problem in that the number of masks was considerably increased compared to the current inverted staggered hydrogenated amorphous silicon TPT process.
本発明は上記従来の課題を解決するもので、低温プロセ
ス(<600℃)による多結晶シリコンを用いたTPT
を製作する半導体装置の製造方法を提供することを目的
とする。The present invention solves the above-mentioned conventional problems, and consists of TPT using polycrystalline silicon through a low-temperature process (<600°C).
An object of the present invention is to provide a method for manufacturing a semiconductor device.
課題を解決するだめの手段
この目的を達成するために本発明では、逆スタガ型の構
造を採用し、ケート絶縁膜と半導体薄膜(水素化アモル
ファスシリコン薄膜等)を連続成膜し、さらに多結晶シ
リコン薄膜形成に関してはレーザー光照射による水素化
アモルファスソリコン薄膜の溶融、結晶化を行なってい
る。Means for Solving the Problem In order to achieve this object, the present invention adopts an inverted staggered structure, sequentially deposits a gate insulating film and a semiconductor thin film (such as a hydrogenated amorphous silicon thin film), and further forms a polycrystalline film. Regarding silicon thin film formation, hydrogenated amorphous silicon thin films are melted and crystallized by laser beam irradiation.
さらにゲート絶縁膜の」二に堆積する半導体薄膜に予め
不純物を低濃度でトープし、次にチャネル領域を薄膜で
マスクした状態で高濃度の不純物元素を半導体薄膜表面
にイ」着または半導体薄膜中に注入した後、マスク用薄
膜をエンチングしてレーザー光を照射する構成を有して
いる。Furthermore, the semiconductor thin film to be deposited on top of the gate insulating film is doped with impurities at a low concentration in advance, and then, with the channel region masked by the thin film, high concentration impurity elements are doped onto the surface of the semiconductor thin film or into the semiconductor thin film. After injecting the mask, the mask thin film is etched and laser light is irradiated.
作用
上記の構成のように、レーザー光を照射して多結晶シリ
コン薄膜を形成することにより、低温(<600℃)で
多結晶シリコン薄膜を形成できるため基板の選択範囲が
広がる。Effect As in the above structure, by forming a polycrystalline silicon thin film by irradiating laser light, the polycrystalline silicon thin film can be formed at a low temperature (<600° C.), which widens the range of substrate selection.
また逆スタガ型構造を採用することにより、半導体薄膜
をゲート絶縁膜の上に形成できるためチャネル領域が半
導体層の下部となり、プラズマのダメージを受りること
なく良好なチャネルを形成することができる。In addition, by adopting an inverted staggered structure, the semiconductor thin film can be formed on the gate insulating film, so the channel region is located below the semiconductor layer, making it possible to form a good channel without being damaged by plasma. .
さらに、ゲート絶縁膜の−1−に堆積する半導体薄膜に
予め不純物を低濃度で1−プし、次にチャネル領域以外
に高濃度の不純物元素を(=J着または注入することに
より、その後のレーザー光照射による溶融、結晶化で低
濃度のチャネル領域と高濃度のソース、lレイン領域を
容易に形成することが可能である。また、チャネル領域
の不純物濃度の制御も堆積する半導体薄膜の不純物濃度
を変化させることにより容易に行なうことができる。Furthermore, impurities are pre-doped at a low concentration into the semiconductor thin film deposited on the -1- side of the gate insulating film, and then high-concentration impurity elements are deposited or implanted in areas other than the channel region. It is possible to easily form a low-concentration channel region and high-concentration source and l-rain regions by melting and crystallization by laser beam irradiation.In addition, the impurity concentration of the channel region can be controlled by controlling the impurity concentration of the deposited semiconductor thin film. This can be easily done by changing the concentration.
実施例
以下本発明の一実施例について、図面を参照し2ながら
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例における半導体装置の製造方
法を示す工程断面図である。ますnチャネル多結晶シリ
コン窒化膜であるが、第1図(a)に示すように、透光
性基板1の上にスパッタ法等により金属薄膜を堆積した
後、所定の形状にエツチングし、ゲート電極2を形成す
る。透光性基板1にばガラスや石英等をゲート電極2を
構成する金属薄膜にはクロム(Cr)等を用いる。FIG. 1 is a process sectional view showing a method of manufacturing a semiconductor device in an embodiment of the present invention. This is an n-channel polycrystalline silicon nitride film. As shown in FIG. 1(a), a thin metal film is deposited on a transparent substrate 1 by sputtering or the like, and then etched into a predetermined shape to form a gate. Electrode 2 is formed. Glass, quartz, or the like is used for the transparent substrate 1, and chromium (Cr) or the like is used for the metal thin film forming the gate electrode 2.
次に同図(b)に示すよ・うに、透光11基板1の上に
絶縁膜3aおよび3bと半導体薄膜5を堆積した後、マ
スク用薄膜5をチャネル領域に形成する。Next, as shown in FIG. 2B, after insulating films 3a and 3b and semiconductor thin film 5 are deposited on transparent substrate 1, masking thin film 5 is formed in the channel region.
絶縁膜3aにはスパッタ法または陽極酸化法等により形
成したTa20Xが常圧CVD法等で成膜した5i02
等を用いる。絶縁膜3bと半導体薄膜5はプラズマCV
D装置によりシリコン窒化膜とホロン(B)を10+1
−107cm’ ドープした低濃度のp型水素化アモル
ファスシリコン薄膜(以下符号5で示す)を連続成膜す
ることにより形成する。ここでp型水素化アモルファス
シリコン薄膜5の膜厚は300〜3000人とする。こ
のようにしてシリコン窒化膜3bの上に水素化アモルフ
ァスシリコン薄膜5を連続成膜することにより、シリコ
ン窒化膜3bと水素化アモルファスシリコン薄膜5の界
面を大気中にさらすことなく形成できるため自然酸化膜
の影響がない。さらに、通常プラズマCVD法でシリコ
ン窒化膜3bと水素化アモルファスシリコン薄膜5を堆
積する場合、高周波電力密度は水素化アモルファスシリ
コン薄膜5を堆積する時に比べてシリコン窒化膜3bを
堆積する時の方が10倍程度大きいため、水素化アモル
ファスシリコン薄膜5の」二にシリコン窒化膜3bを堆
積する場合に比べて、シリコン窒化膜3bの上に水素化
アモルファスシリコン薄膜5を堆積する場合の方が膜表
面へのプラズマにょるダメージが少なく、良好な界面を
形成することかできる。また、水素化アモルファスシリ
コン薄膜5OBfi度を変化させることによりチャネル
領域の不純物濃度を制御することができる。マスクm1
膜4はフメトレジスl〜をシリコン窒化膜等を用いる。The insulating film 3a includes Ta20X formed by sputtering or anodic oxidation, and 5i02 formed by atmospheric pressure CVD.
etc. are used. The insulating film 3b and the semiconductor thin film 5 are formed by plasma CV
Silicon nitride film and holon (B) are 10+1 using D equipment.
-107 cm' A low concentration p-type hydrogenated amorphous silicon thin film (hereinafter denoted by reference numeral 5) doped with 5 is formed by successive deposition. Here, the thickness of the p-type hydrogenated amorphous silicon thin film 5 is 300 to 3000. By continuously forming the hydrogenated amorphous silicon thin film 5 on the silicon nitride film 3b in this way, the interface between the silicon nitride film 3b and the hydrogenated amorphous silicon thin film 5 can be formed without exposing it to the atmosphere, resulting in natural oxidation. No influence of membrane. Furthermore, when depositing the silicon nitride film 3b and the hydrogenated amorphous silicon thin film 5 using the normal plasma CVD method, the high frequency power density is higher when depositing the silicon nitride film 3b than when depositing the hydrogenated amorphous silicon thin film 5. Because it is about 10 times larger, the film surface is larger when the hydrogenated amorphous silicon thin film 5 is deposited on the silicon nitride film 3b than when the silicon nitride film 3b is deposited on the second part of the hydrogenated amorphous silicon thin film 5. There is little damage to the plasma caused by the plasma, and a good interface can be formed. Further, by changing the hydrogenated amorphous silicon thin film 5OBfi degree, the impurity concentration in the channel region can be controlled. mask m1
For the film 4, a silicon nitride film or the like is used.
次に同図(C)に示すように、マスク用薄膜4をマスク
にして不純物元素供給ガスを用いて水素化アモルファス
シリコン薄膜5に不純物イオン6を注入する。この不純
物元素の供給源には例えばPH8(0,1〜10%水素
希釈)を用いる。さらにこのPH3をプラズマ分解して
イオン化した後、水素化アモルファスシリコン薄膜5へ
注入ずろ。Next, as shown in FIG. 4C, impurity ions 6 are implanted into the hydrogenated amorphous silicon thin film 5 using the masking thin film 4 as a mask and using an impurity element supply gas. For example, PH8 (0.1 to 10% hydrogen dilution) is used as the source of this impurity element. Furthermore, this PH3 is ionized by plasma decomposition and then implanted into the hydrogenated amorphous silicon thin film 5.
このようにしてりん(P)イオンを注入された水素化ア
モルファスシリコン薄膜5はPを10”〜10”cm−
’ドープされた高濃度のn型となる。The hydrogenated amorphous silicon thin film 5 into which phosphorus (P) ions have been implanted in this way has a P concentration of 10" to 10" cm-
'It becomes a highly doped n-type.
ここで不純物元素はイオン注入以外の方法で半導体薄膜
の表面に付着さ一部てもよい。次に同図(d)に示すよ
うに、レーザー光7の照射により半導体薄膜5を溶融、
結晶化する。レーザー光7には、エキシマレーザ−やA
rレーザー等を用いる。ここでレーザー光7を照射する
前に、透光性基板1を真空容器に保持した状態で排気し
なから透光性基板1を300〜500℃に加熱して水素
化アモルファスシリコン薄膜5の脱水素処理を行なって
おく必要がある。これは、脱水素処理を行なわない水素
化アモルファスソリコン薄膜5をレーリ′−光7で溶融
すると、膜中の水素が2激に加熱されて膜外−・放出さ
れる際に膜に大きなダメージを与えるためである。また
、レーデ−光7を照射した後の多結晶シリコン薄膜8a
Aよ、形成された粒界にダングリングボンドが多数存在
しているために良好な電気特性を示さない。そこで、レ
ーザー光7を照射した後透光性基板1を100〜400
℃に加熱した状態で水素雰囲気中または水素プラズマ雰
囲気中で処理してダングリングホントを減少させ、電気
特性を向上させる。以上のような処理を行なうこよによ
り、高濃度n型多結晶ソリコン薄膜(ソースまたはトレ
イン領域)8と低濃度p型子結晶シリコン薄膜(チャネ
ル領域)9を形成することができる。次に同図(e)に
示すように、チャネル領域9の上に絶縁膜10を所定の
形状に形成する。この絶縁膜にはプラズマCVD装置で
堆積したシリコン窒化膜等を用いる。次に同図(f)に
示すように、金属薄膜を形成した後、金属薄膜と多結晶
シリコン窒化膜8,9を所定の形状乙こエツチングして
ソース電極11とトレイン電極12を形成する。これら
の電極11.12にはアルミ(Δ℃)モリブデンシリサ
イド(MoSi)、またはチタン(Ti)等を用いる。Here, the impurity element may be attached to the surface of the semiconductor thin film by a method other than ion implantation. Next, as shown in FIG. 7(d), the semiconductor thin film 5 is melted by irradiation with laser light 7.
crystallize. The laser beam 7 includes excimer laser and A
r laser etc. is used. Here, before irradiating the laser beam 7, the transparent substrate 1 is held in a vacuum container and is heated to 300 to 500° C. without evacuation, thereby dehydrating the hydrogenated amorphous silicon thin film 5. It is necessary to perform basic processing. This is because when a hydrogenated amorphous solicon thin film 5 that is not subjected to dehydrogenation treatment is melted using Rayleigh's light 7, the hydrogen in the film is heated rapidly and released from the film, causing great damage to the film. This is to give Also, the polycrystalline silicon thin film 8a after being irradiated with the radar light 7
A does not show good electrical properties because there are many dangling bonds in the formed grain boundaries. Therefore, after irradiating the laser beam 7, the transparent substrate 1 was
It is treated in a hydrogen atmosphere or a hydrogen plasma atmosphere while being heated to 0.degree. C. to reduce dangling spots and improve electrical characteristics. By performing the above-described processing, a highly doped n-type polycrystalline silicon thin film (source or train region) 8 and a lightly doped p-type subcrystalline silicon thin film (channel region) 9 can be formed. Next, as shown in FIG. 3E, an insulating film 10 is formed in a predetermined shape on the channel region 9. For this insulating film, a silicon nitride film or the like deposited using a plasma CVD apparatus is used. Next, as shown in FIG. 2F, after forming a metal thin film, the metal thin film and polycrystalline silicon nitride films 8 and 9 are etched into a predetermined shape to form a source electrode 11 and a train electrode 12. These electrodes 11 and 12 are made of aluminum (Δ° C.), molybdenum silicide (MoSi), titanium (Ti), or the like.
次に、PチャZ・ル多結晶シリコンTPTの作製プロセ
スを説明する。pチャネルTPTの作製プロセスは、第
1図に示ず°(′導体?3IN9.5の代わりにP(リ
ン)を10” 〜] 0’ cm3トープした低濃度の
n型水素化アモルファスシリコン薄膜を、また不純物イ
オン6の供給源としてB2H6(0,1〜10%水素希
釈)を用いて、あとは第1図と同様のプロセスを行なう
ことにより作製することができる。Next, the manufacturing process of Pchal Z·l polycrystalline silicon TPT will be explained. The fabrication process of the p-channel TPT is not shown in Fig. 1. (10''~]0'cm3 of P (phosphorous) instead of the conductor 3IN9.5) A low concentration n-type hydrogenated amorphous silicon thin film doped with 0'cm3 is used. , and can be manufactured by using B2H6 (0.1 to 10% diluted with hydrogen) as a source of impurity ions 6 and performing the same process as shown in FIG.
発明の効果
以上のように本発明による多結晶シリコンTPTを作製
するプロセスは以下の効果を奏するものである。Effects of the Invention As described above, the process for manufacturing polycrystalline silicon TPT according to the present invention has the following effects.
(])半導体薄膜(水素化アモルファスシリコン薄膜)
をレーザー光により溶融、結晶化して多結晶シリコンを
薄膜形成することにより低温(<600℃)プロセスが
可能となり、基板選択の幅が広がる。(]) Semiconductor thin film (hydrogenated amorphous silicon thin film)
By melting and crystallizing polycrystalline silicon using laser light to form a thin film of polycrystalline silicon, a low-temperature (<600° C.) process becomes possible, expanding the range of substrate selection.
(2)素子の構造を逆スタガ型とすることによりゲート
絶縁膜と半導体薄膜の界面を良好に形成することができ
る。(2) By making the element structure inverted staggered, it is possible to form a good interface between the gate insulating film and the semiconductor thin film.
(3)不純物を含んだ半導体薄膜(水素化アモルファス
シリコン薄膜)の上にマスク用FIIIRを用いて不純
物元素を所定の領域に付着または注入した後、レーザー
光を照射して溶融、結晶化するこきにより所定の不純物
濃度のチャネル領域およびソース、ドレイン領域を有す
る多結晶シリコン′rI?Tを容易に形成することがで
きる。(3) After attaching or implanting an impurity element to a predetermined area on a semiconductor thin film (hydrogenated amorphous silicon thin film) containing impurities using a FIIIR mask, it is irradiated with laser light to melt and crystallize it. Polycrystalline silicon 'rI?' having a channel region, source, and drain regions with a predetermined impurity concentration. T can be easily formed.
第1図(a)〜(f)は本発明の一実施例における半導
体装置の製造方法を示す工程断面図である。
1・・・・・・透光性基板、2・・・・ゲート電極(電
極)、3a、3b・・・・絶縁膜〔絶縁性aT膜〕、4
・・・・・・マスク用薄膜(薄膜)、5・・・・・・水
素化アモルファスシリコン薄膜(半導体7!IJ膜)、
6・・・・・不純物イ第ン、7・・・・・・レーザー光
。
代理人の氏名 弁理士小鍜冶明 ほか2名AFIGS. 1(a) to 1(f) are process cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1... Transparent substrate, 2... Gate electrode (electrode), 3a, 3b... Insulating film [insulating aT film], 4
... Thin film for mask (thin film), 5... Hydrogenated amorphous silicon thin film (semiconductor 7! IJ film),
6...Impurity number 7...Laser light. Name of agent: Patent attorney Yoshiaki Ogata and 2 others A
Claims (7)
1の工程と、前記透光性基板と前記電極の上に絶縁性薄
膜を堆積する第2の工程と、前記絶縁性薄膜の上に半導
体薄膜を堆積する第3の工程と、前記半導体薄膜の上の
一部領域に薄膜を形成する第4の工程と、不純物元素を
前記半導体薄膜の表面に付着または前記半導体薄膜中に
注入する第5の工程と、前記透光性基板の一部領域にレ
ーザー光を照射する第6の工程とを少なくとも有する半
導体装置の製造方法。(1) A first step of forming an electrode in a predetermined shape on a transparent substrate, a second step of depositing an insulating thin film on the transparent substrate and the electrode, and a step of depositing an insulating thin film on the transparent substrate and the electrode. a third step of depositing a semiconductor thin film on the thin film; a fourth step of forming a thin film on a partial region on the semiconductor thin film; and a third step of depositing an impurity element on the surface of the semiconductor thin film or in the semiconductor thin film. A method for manufacturing a semiconductor device, the method comprising at least a fifth step of injecting laser light into a region of the transparent substrate, and a sixth step of irradiating a partial region of the light-transmitting substrate with a laser beam.
6)等の主原料ガスと不純物元素を含有するガスとを混
合した混合ガスをプラズマ分解、熱分解または光分解の
うちの何れかの手段を用いて半導体薄膜を堆積すること
を特徴とする請求項1記載の半導体装置の製造方法。(2) Silane (SiH_4), disilane (Si_2H_
6) A claim characterized in that a semiconductor thin film is deposited using any one of plasma decomposition, thermal decomposition, or photodecomposition of a mixed gas in which a main source gas such as the above and a gas containing an impurity element are mixed. Item 1. A method for manufacturing a semiconductor device according to item 1.
_3)またはジボラン(B_2H_6)の何れかとH_
2との混合ガスであることを特徴とする請求項2記載の
半導体装置の製造方法。(3) The gas containing impurity elements is phosphine (PH
_3) or diborane (B_2H_6) and H_
3. The method of manufacturing a semiconductor device according to claim 2, wherein the gas is a mixture of 2 and 3.
よりも第5の工程で不純物元素を表面に付着または注入
された領域の不純物濃度を高くすることを特徴とする請
求項1記載の半導体装置の製造方法。(4) The method according to claim 1, characterized in that the impurity concentration in the region where the impurity element is attached to the surface or implanted in the fifth step is higher than the impurity concentration in the semiconductor thin film deposited in the third step. A method for manufacturing a semiconductor device.
特徴とする請求項1記載の半導体装置の製造方法。(5) The method of manufacturing a semiconductor device according to claim 1, wherein the second step and the third step are performed in a vacuum.
体薄膜の表面に付着または半導体薄膜中に注入した後に
、真空中、窒素雰囲気中または水素雰囲気中のうちの何
れかの状態のもとで 200〜600℃の温度範囲で熱処理を行なうことを特
徴とする請求項1記載の半導体装置の製造方法。(6) After depositing the semiconductor thin film or after attaching an impurity element to the surface of the semiconductor thin film or implanting the impurity element into the semiconductor thin film, it is heated for 200 minutes in a vacuum, in a nitrogen atmosphere, or in a hydrogen atmosphere. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in a temperature range of 600 DEG C.
100〜400℃、10^3〜10Torrの水素雰囲
気中または水素プラズマ雰囲気中で水素処理を行なうこ
とを特徴とする請求項1記載の半導体装置の製造方法。(7) After irradiating the laser beam, hydrogen treatment is performed in a hydrogen atmosphere or a hydrogen plasma atmosphere at a temperature of 100 to 400° C. and 10^3 to 10 Torr of the transparent substrate. A method of manufacturing the semiconductor device described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2338171A JPH04206837A (en) | 1990-11-30 | 1990-11-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2338171A JPH04206837A (en) | 1990-11-30 | 1990-11-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04206837A true JPH04206837A (en) | 1992-07-28 |
Family
ID=18315586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2338171A Pending JPH04206837A (en) | 1990-11-30 | 1990-11-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04206837A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6479331B1 (en) * | 1993-06-30 | 2002-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| US7320905B2 (en) | 1998-08-21 | 2008-01-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same |
| JP2008098653A (en) * | 1998-08-21 | 2008-04-24 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
| US7622335B2 (en) | 1992-12-04 | 2009-11-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a thin film transistor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893243A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Improvement of polysilicon thin film semiconductor |
| JPS59113667A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS60105216A (en) * | 1983-11-11 | 1985-06-10 | Seiko Instr & Electronics Ltd | Manufacture of thin film semiconductor device |
| JPH01290264A (en) * | 1988-05-18 | 1989-11-22 | Fujitsu Ltd | Thin film transistor |
| JPH02130837A (en) * | 1988-11-10 | 1990-05-18 | Casio Comput Co Ltd | Thin film transistor and its manufacturing method |
| JPH02177443A (en) * | 1988-12-28 | 1990-07-10 | Sony Corp | Manufacture of thin film transistor |
-
1990
- 1990-11-30 JP JP2338171A patent/JPH04206837A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893243A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Improvement of polysilicon thin film semiconductor |
| JPS59113667A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS60105216A (en) * | 1983-11-11 | 1985-06-10 | Seiko Instr & Electronics Ltd | Manufacture of thin film semiconductor device |
| JPH01290264A (en) * | 1988-05-18 | 1989-11-22 | Fujitsu Ltd | Thin film transistor |
| JPH02130837A (en) * | 1988-11-10 | 1990-05-18 | Casio Comput Co Ltd | Thin film transistor and its manufacturing method |
| JPH02177443A (en) * | 1988-12-28 | 1990-07-10 | Sony Corp | Manufacture of thin film transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6872605B2 (en) | 1992-12-04 | 2005-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| US7622335B2 (en) | 1992-12-04 | 2009-11-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a thin film transistor device |
| US6479331B1 (en) * | 1993-06-30 | 2002-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| US7238558B2 (en) | 1993-06-30 | 2007-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| US7320905B2 (en) | 1998-08-21 | 2008-01-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same |
| JP2008098653A (en) * | 1998-08-21 | 2008-04-24 | Semiconductor Energy Lab Co Ltd | Manufacturing method of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7354811B2 (en) | Semiconductor device and process for fabricating the same | |
| US5834071A (en) | Method for forming a thin film transistor | |
| JP3402380B2 (en) | Semiconductor circuit and manufacturing method thereof | |
| JP2734587B2 (en) | Method for manufacturing thin film transistor | |
| JPH11307777A (en) | Top gate type thin-film transistor and manufacture thereof | |
| JPH0738110A (en) | Method for manufacturing semiconductor device | |
| JPH03194937A (en) | Manufacture of thin film transistor | |
| JPH04206837A (en) | Manufacture of semiconductor device | |
| JP3211340B2 (en) | Method for manufacturing thin film transistor | |
| JPH0766415A (en) | Manufacture of semiconductor device and thin-film transistor | |
| JPS6230314A (en) | Manufacture of crystalline semiconductor thin film | |
| JPH11354441A (en) | Method for manufacturing semiconductor device | |
| US8034671B2 (en) | Polysilicon film, thin film transistor using the same, and method for forming the same | |
| JPS63250178A (en) | Method for manufacturing thin film semiconductor devices | |
| JPH08316487A (en) | Manufacture of thin-film semiconductor device | |
| JP3535465B2 (en) | Method for manufacturing semiconductor device | |
| JP3075498B2 (en) | Method for manufacturing thin film transistor | |
| JP3063018B2 (en) | Method for manufacturing thin film transistor | |
| JP2535654B2 (en) | Method of manufacturing thin film transistor | |
| KR0140665B1 (en) | Method of manufacturing thin film transistor | |
| JPH05235039A (en) | Method of manufacturing thin film transistor | |
| JPH04186735A (en) | Manufacture of semiconductor device | |
| JP3417182B2 (en) | Method for manufacturing thin film semiconductor device and method for manufacturing electronic equipment | |
| JP3346060B2 (en) | Method for manufacturing thin film semiconductor device | |
| JPH06244203A (en) | Manufacture of thin film transistor |