JPH04196635A - Data multiplex system utilizing time division multiplex bus - Google Patents

Abstract

PURPOSE:To reduce the scale of the hardware at an exchange section by using plural composition sections to apply time division multiplex to asynchronous data of plural channels and transferring the result to a data bus at a band assigned in advance to itself. CONSTITUTION:A composition section 11n uses composition circuits 15n1-15nk to compose k-channels of data as prescribed asynchronous data separately and applies time division multiplex to them at a multiplex section 14n. Then composition sections 111-11n transfer data subject to time division multiplex to a data bus 13 at a band assigned to the data bus 13 itself. Thus, number of synchronizing circuits and memories by accommodated channels are not required for an exchange section 12 and number of the buffer memories and the synchronizing circuits the same as the number (n) of the composition sections 111-11n is provided and data are extracted and stored for each allocated band and when one data is stored in each buffer memory, exchange is attained. Thus, the hardware scale of the exchange section is reduced.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a data multiplexing method using a time division multiplexed bus that multiplexes and transfers asynchronous data onto a synchronous transfer mode data bus, and aims to reduce the hardware scale of the switching section. In a data multiplexing method using a time division multiplex bus, in which asynchronous data multiplexed in a synchronous transfer mode is transferred between a plurality of asynchronous data assembling units and a switching unit using a data bus in a synchronous transfer mode, The plurality of assembling units each have a multiplexing unit that time-division multiplexes the assembled asynchronous data of the plurality of channels, and the multiplexing units transfer the multiplexed data from the multiplexing unit to the data bus in a band that is pre-assigned to the multiplexing unit. Configure.

[Industrial application field]

The present invention relates to a data multiplexing method using a time division multiplex bus, and more particularly to a data multiplexing method in which asynchronous data is also multiplexed and transmitted on a data bus in a synchronous transfer mode.

In recent years, as users' demands for information and communications have become more sophisticated,
There is a need for a high-speed multimedia communication network that can transmit large amounts of data at high speed and handle multiple types of media in an integrated manner. For this reason, a technology such as asynchronous transfer mode (ATM) in which information generation timing is asynchronous between terminals is required, and in order to perform ATM-like communication using existing lines, synchronous transfer mode within the device is required. (STM
) It is necessary to time-division multiplex asynchronous data onto the data bus.

[Conventional technology]

, FIG. 5 shows a schematic configuration diagram of an example of a data multiplexing method using a conventional time division multiplexed bus. In the same figure, 11 to 14
are cell assembly sections, respectively, and are provided corresponding to the channels. The cell assembling units 11 to 14 receive various types of media information (hereinafter collectively referred to as data) such as audio, data, and moving images that differ in bearer speed and burstiness, and convert these into fixed-length chunks into cells. (packetized) and adds a header containing routing information such as destination to this information to assemble units called "cells", and then FI
Stored in FO2 and FO24 respectively.

When data of a certain length is stored in each of the PIFs 021 to 24, the cell assembling units 11 to 14 send out the stored data (cells) to the data bus 3 at a predetermined timing. here,
Data frame (Fram) transmitted on data bus 3
e) is 5 time slots (TS) from 0 to 511.
Assuming that there are 12 time slots, the data of the first channel CH#1 from the FIFO 21 is shown in FIG. It is transmitted at the timing of the predetermined time slot shown by .

Similarly, other FIFOs 22, 23 and 2. The data of each channel CH#2 to CH#4 is transmitted at the timing of separate time slots assigned in advance, as shown by 7 and 74 in the same figure.

Thereafter, the above operation is repeated in units of frame synchronization.

The fifth cell switching section 4 receives the time-division multiplexed data (including headers) from the data bus 3 separately through cell synchronization sections 51 to 54 provided for each channel.
An error check is performed using a redundancy check (CRC) code, etc., and if there is no error, it is determined that the input data is synchronized, and the input data is transferred to the next stage FIF.
Supplied to O6, ~64.

The data stored in the PIFOs 6 and 64 is routed based on the information obtained by autonomously reading the header of the data in the cell switching section 4 by each unit switch hardware in the communication path.

[Problem to be solved by the invention]

However, in the above conventional system, the cell synchronization section 5. in the cell switching section 4. ~5. and FIFO6, ~6. f) <, Cell assembly section 1. Since the number of input data channels is 1 to 1, the hardware scale of the cell switching section 4 increases as the number of accommodated channels increases, resulting in an increase in cost.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a data multiplexing method using a time division multiplexed bus that can reduce the hardware scale of the switching unit.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. The present invention provides an assembly section 11. ~11. In a data multiplexing method in which time-division multiplexed asynchronous data is transferred between the assembling unit 1 and the exchange unit 12 using the data bus 13 in synchronous transfer mode, the assembling unit 1
1. ~11. Each of the multiplexing units 14 . .about.148, and multiplexing sections 141-14. The multiplexed data is transferred to the data bus 13 using a band assigned in advance to itself.

[Effect]

In FIG. 1, an assembling unit 111 assembles l-channel data separately into predetermined asynchronous data using assembling circuits 15,1 to 15.1, and then assembles the data into a multiplexer (MUX) 14.
．． time division multiplexing. Similarly, assembling section 113 assembles channel data into assembling circuits 15.1 to 15.1. After assembling them as predetermined asynchronous data separately in the multiplexer (
MUX) 14, time division multiplexing is performed.

Assembly section 111-11. Next, the multiplexer 14. The data time-division multiplexed in steps 1 to 14 are transferred to the data bus 13 using the band assigned to the data bus 13 itself. FIG. 2 is a diagram explaining the bandwidth allocation of the data bus 13 at this time, and the multiplexed data from the assembling unit 11+ is
+1st and x+2nd time slots TS,.

The multiplexed data from the assembling unit 111 is transferred at TS1□ and is sent to the y+1st, y+2nd, and y+3rd time slots TS in l frame.

This indicates that the data is transferred via TS A+ and TS A+2.

Therefore, in the present invention, the exchange unit 12 to which the above-mentioned time-sharing data is input via the data bus 13 does not require synchronization circuits and memories for the number of accommodated channels, and the assembly units 111 to 1
1. Develop the same number of buffer memories and synchronization circuits as the number n, extract and store data for each of the above allocated bands, and exchange data when one piece of data is accumulated in each buffer memory. I can do it.

〔Example〕

FIG. 3 shows a configuration diagram of an embodiment of the present invention. In this embodiment, the above-mentioned assembly section 11. The numbers l and k of channels 111 to 111 are each "4", and this is an example of multiplexing of ATM cells. In FIG. 3, data generated asynchronously at the terminals of the first channel to the fourth channel is transmitted to the terminal interface (INF) 21.
．． ．． 2It to the data bus 22, and then to the cell assembly/disassembly section 23. (corresponding to the assembly section 111)
ATV cells of several bytes are assembled for each channel in cell assembly units 241 to 244 in the cell assembly section. Cell assembly section 241-2
The ATMs from 44 are stored in the corresponding FIFOs 25 and 254 as buffer memories, and then sent to the multiplexer (
MUX)26. will be forwarded to.

Similarly, data generated asynchronously at the terminals of the fifth to eighth channels is transmitted via the terminal INF 212 or 214 and the data bus 22 to the cell assembly/disassembly unit 23. (corresponding to the aforementioned assembly section 11.), and is input into the cell assembly section 24. for each channel. FIFO 25 as a buffer memory after being assembled into an ATM cell at ~24°, ~25. via M
Transferred to UX26. Although there are a total of n cell assembly/disassembly sections, only two are shown in FIG. 3 for convenience of illustration.

The data bus 27 is a bus for transferring time division multiplexed data.
As shown in FIG. 4, for the cell assembly/disassembly section 23, in one frame consisting of 512 time slots (TS) in total,
, TS, , , and cell assembly/disassembly section 23 . For the y+1st and y+2nd time slots TS A and TS A in l frame. Bandwidth is allocated in advance to .

As a result, as shown in FIGS. 4(A) to 4(C), after each data of the first channel and the fifth channel is sequentially transferred in two predetermined time slots in each frame,
As shown in E), the data of the second channel and the seventh channel are sequentially transferred in two predetermined time slots in each frame. Next, as shown in Fig. 4 (F) to (H), the third
After each data of the channel and the fifth channel is transferred sequentially at a predetermined two time float in each frame,
, (I), the data of the fourth channel and the sixth channel are sequentially transferred. Thereafter, the same operation as above is repeated.

The cells time-division multiplexed on the data bus 27 in this manner are input to the cell synchronization sections 291 to 29 in the cell switching section 28 in FIG. 3 (corresponding to the switching section 12 in FIG. 1), where they are Based on the band of the data bus 27, the multiplexing units 26+, 2
6t, the cells from the multiplexer 261 are extracted by the cell synchronizer 29], and the cells from the multiplexer 26.6t are extracted by the cell synchronizer 29]. Cells from the cell synchronization section 29. After being extracted and further synchronized to find the beginning of each data, the FIFO 301
~80. The data are stored in the corresponding FIFOs 30, 3L, respectively. Note that the cell assembly/disassembly section 23j (not shown)
23. Cells from cell synchronization units 298-29. is input.

When data of one or more cells is accumulated in the FIFOs 30, 30s, the switch unit 31 transfers the PIFs 0301 to 30. Performs switching to distribute data from. The data from the switch unit 31 is stored in the first FTFO among the FIFOs 32, -328, and then transferred to the data bus 3.
3 to the line INF.

Note that the data from the other party is sent to the cell synchronization units 341 to 34.34 in the cell switching unit 28. , the data of each allocated band is extracted, and after synchronization is established to find the beginning of the data, the FIFOs 35, -35 . The signal is input to the switch section 31 through. The data switched by the switch section 31 is passed through the PIFO 36 to the cell assembly/disassembly section 23. , 23. Separation section (DMUX) within
(not shown) and accommodates the specified channel.
Extracted based on header in UX.

〔Effect of the invention〕

As described above, according to the present invention, the number of synchronization circuits and buffer memories in the exchange section can be reduced to the number of assembly sections that multiplex data of multiple channels, rather than the number of accommodation channels. This has the advantage of being able to reduce the hardware scale of the section and reducing the cost of the device.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is an explanatory diagram of band allocation of the data bus of the present invention, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is the data bus of Fig. 3. FIG. 5 is a schematic configuration diagram of an example of the conventional method. FIG. 6 is an explanatory diagram of data bus bandwidth assignment in the conventional method. In the figure, 111-11. 12 is an assembly section, 12 is a switching section, 13 is a data bus, and 141 to 141 are multiplexing sections (MUX). Patent Applicant: Fujitsu Ltd.\J: Municipal Bond Fallen Lease Figure 1 Figure 2 Figure 5

Claims (1)

[Claims] A synchronous transfer mode data bus (
In the data multiplexing method using a time division multiplex bus that transfers asynchronous data that has been time division multiplexed using 13), the plurality of assembling units (11_1 to 11_n) respectively assemble asynchronous data of a plurality of channels. It has a multiplexing unit (14_1 to 14_n) that performs time division multiplexing, and the multiplexing unit (14_n)
_1 to 14_n) is transferred to the data bus (13) in a pre-assigned band to the data bus (13).