JPH04188877A - Power mosfet of high breakdown strength - Google Patents
Power mosfet of high breakdown strengthInfo
- Publication number
- JPH04188877A JPH04188877A JP2319449A JP31944990A JPH04188877A JP H04188877 A JPH04188877 A JP H04188877A JP 2319449 A JP2319449 A JP 2319449A JP 31944990 A JP31944990 A JP 31944990A JP H04188877 A JPH04188877 A JP H04188877A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- trench
- breakdown voltage
- layer
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、低オン抵抗化、高耐圧化をはがっな縦形パワ
ーＭＯＳＦＥＴに関するものである。DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a vertical power MOSFET that has low on-resistance and high breakdown voltage.
〈従来の技術〉
第６図〜第８図は縦形ＭＯＳＦＥＴの従来構造を示す断
面図である。即ち、第６図は２重拡散縦形ＭＯＳＦＥＴ
の一般的な構造を示すもので、高耐圧化するために、高
抵抗の厚いＮ−エビ層１を有する為ＭＯＳＦＥＴのオン
抵抗低縞に限界がある。また、ｐｎ接合部２が湾曲して
いる為逆電圧を加えた場合、この接合部分２で電界集中
が起こりやすくなり耐圧が低下する。<Prior Art> FIGS. 6 to 8 are cross-sectional views showing the conventional structure of a vertical MOSFET. That is, FIG. 6 shows a double diffused vertical MOSFET.
This shows a general structure of the MOSFET, which has a thick N-layer 1 with high resistance in order to achieve high breakdown voltage, so there is a limit to the low on-resistance stripes of the MOSFET. Furthermore, since the pn junction 2 is curved, when a reverse voltage is applied, electric field concentration tends to occur at this junction 2, resulting in a decrease in breakdown voltage.
第７図はＶ溝縦形ＭＯＳＦＥＴを示すもので。Figure 7 shows a V-groove vertical MOSFET.
ゲート部を７字状に加工する。しかしこの形状において
は■溝光ｒ４Ａ３で電界集中し易く、耐圧を向上させる
ことができない。Process the gate part into a figure 7 shape. However, in this shape, the electric field tends to concentrate in the groove light r4A3, making it impossible to improve the breakdown voltage.
また、第８図は矩形溝形構造と呼ばれるもので。Also, Fig. 8 shows what is called a rectangular groove structure.
基板に清を掘り、その清の中に酸化膜からなるサイドウ
オール（ＳｉＯ２）４を形成している。この構造は第１
図、第２図のものに比較してチャネルが纒に形成されて
いるため、隣接する素子の距離を短くすることができる
。そのためセルの充填効率が良くなり、オン抵抗を低減
させることができ、数十■耐圧の素子で数ｍΩのオン抵
抗を実現している。A clear layer is dug in the substrate, and a side wall (SiO2) 4 made of an oxide film is formed in the clear layer. This structure is the first
Since the channels are formed in a straight line compared to those in FIGS. 2 and 2, the distance between adjacent elements can be shortened. This improves the cell filling efficiency and reduces the on-resistance, achieving an on-resistance of several milliohms with a device with a withstand voltage of several tens of micro-ohms.
〈発明が解決しようとする課題〉
しかしながら、上記第８図の従来例においては溝の底面
のエッチで電界集中が生じ、耐圧を向上させることがで
きないという問題があった。<Problems to be Solved by the Invention> However, in the conventional example shown in FIG. 8, electric field concentration occurs due to the etching of the bottom surface of the groove, making it impossible to improve the withstand voltage.
本発明は上記従来技術の問題を解決するために成された
もので、縦形ＭＯＳＦＥＴの低オン抵抗化及び高耐圧化
をはかったパワーＭＯＳＦＥＴを提供することを目的と
する。The present invention has been made to solve the problems of the prior art described above, and an object of the present invention is to provide a power MOSFET that achieves lower on-resistance and higher breakdown voltage than a vertical MOSFET.
く課趙を解決するための手段〉
上記従来技術の間組を解決する為の本発明の構成は、シ
リコン基板に溝を形成し、この溝の側面もしくは溝の側
面及び底面に酸化膜を形成し、前記溝の側面にゲート電
極を形成した矩形溝形ＭＯＳＦＥＴにおいて、前記溝の
底面に前記酸化膜より比誘電率の高い膜を形成したこと
を特徴とするものである。Means for Solving Problems> The structure of the present invention for solving the problem of the prior art is to form a groove in a silicon substrate and form an oxide film on the sides of the groove or on the sides and bottom of the groove. , a rectangular trench MOSFET in which a gate electrode is formed on the side surface of the trench, characterized in that a film having a dielectric constant higher than that of the oxide film is formed on the bottom surface of the trench.
く作用〉
ゲートを極の底面に比誘電率の高い膜を設けたので、ゲ
ート・ソース電極間に逆電位を加えた時１この膜中の等
ポテンシャル線の本数が減りＳｉの境界部で急激な絞り
込みかなくなるので、電界集中を押えることができる。A film with a high dielectric constant is provided at the bottom of the gate electrode, so when a reverse potential is applied between the gate and source electrodes, the number of equipotential lines in this film decreases and the film suddenly appears at the Si boundary. Since there is no narrowing down, electric field concentration can be suppressed.
また、従来の構造に比較して同一の耐圧を得るために電
界集中が低減される構造である為ｎ−エと層の比抵抗を
低減させることが可能なのでオン抵抗を低減させること
ができる。Furthermore, since the structure reduces electric field concentration in order to obtain the same withstand voltage compared to the conventional structure, it is possible to reduce the specific resistance of the n-layer and the layer, thereby reducing the on-resistance.
〈実施例〉
以下１図面に従い本発明を説明する。第１図は本発明の
一実施例を示す縦形ＭＯＳＦＥＴの断面図であり基本構
造は第８図の従来例と同様である。<Example> The present invention will be described below with reference to one drawing. FIG. 1 is a sectional view of a vertical MOSFET showing an embodiment of the present invention, and the basic structure is the same as the conventional example shown in FIG.
第１図において１１は結晶方位（１００）のｎ形Ｓｔウ
ェハー上に形成されたドリフト層であり。In FIG. 1, 11 is a drift layer formed on an n-type St wafer with a crystal orientation (100).
高抵抗（不純物濃度は低い）のｎ−形エビ層である。５
はチャネルを構成する２層でドリフト層１の上にイオン
注入やエピタキシャル成長で形成され１表面にソース取
り出し用ｎ＋層６がイオン注入ななどにより形成されて
いる。It is an n-type shrimp layer with high resistance (low impurity concentration). 5
are two layers constituting a channel, and are formed on the drift layer 1 by ion implantation or epitaxial growth, and an n+ layer 6 for taking out the source is formed on the surface of the first layer by ion implantation or the like.
次にＲＩＥ （リアクティブイオンエツチング）等によ
り矩形の溝７を形成し、この溝７の中に酸化Ｗ１（Ｓ
ｉ ０２ ） ８．ポリシリコンからなるゲート電極９
を形成することによりＭＯＳＦＥＴのチャネル１０が形
成される。なお、清７の底部には比誘電率の高い膜１１
（例えばＳｉ３Ｎ４の比誘電率ｚ８ 、 Ｓ ｉ ０２
七４ ）が形成されている。Next, a rectangular groove 7 is formed by RIE (reactive ion etching) or the like, and oxidized W1 (S
i 02 ) 8. Gate electrode 9 made of polysilicon
By forming the channel 10 of the MOSFET. Note that a film 11 with a high dielectric constant is provided at the bottom of the cell 7.
(For example, relative dielectric constant z8 of Si3N4, S i 02
74) has been formed.
チャンネルｌＯを形成しているｐｎ接合の深さｄは第２
図に示す様に膜１１の厚さｅの１層２程度の位置に制御
する。その結果９等ポテンシャルの絞り込みが厚さｅを
中心に均等に分散されることになり、電界集中がより低
減される。The depth d of the pn junction forming the channel IO is the second
As shown in the figure, the film 11 is controlled to a position of about 2 layers in thickness e. As a result, the narrowing of the nine equal potentials is evenly distributed around the thickness e, and electric field concentration is further reduced.
第３図は本発明の他の実施例を示すもので１この例にお
いては第８図に示す従来例において、溝７の中に酸化膜
からなるサイドウオール８を形成した後、高比誘電率の
膜１１を形成する。この様な構成においても第１図のも
のと同様の効果がある。FIG. 3 shows another embodiment of the present invention.1 In this example, in the conventional example shown in FIG. 8, after forming a sidewall 8 made of an oxide film in the groove 7, A film 11 is formed. Such a configuration also has the same effect as the one shown in FIG.
第４図は本発明のＭＯＳＦＥＴと第６図、第８図に示す
従来例の各構造のドレイン−ソース間の耐圧を実際の形
状を与えてシミュレーションした結果を示すもので１図
中のプレインｐｎ接合とはｐｎ接合の湾曲がなく平面な
接合の場合の理論耐圧を示している。Figure 4 shows the results of simulating the breakdown voltage between the drain and source of the MOSFET of the present invention and the conventional structures shown in Figures 6 and 8 by giving actual shapes. Junction indicates the theoretical withstand voltage in the case of a flat pn junction with no curve.
図から明らかな様に本発明のＭＯＳＦＥＴは従来のＭＯ
ＳＦＥＴに比較して１５〜２０％の耐圧の向上が見られ
、プレインｐｎ接合の理論耐圧に近い耐圧を示している
。As is clear from the figure, the MOSFET of the present invention is similar to the conventional MOSFET.
The breakdown voltage is improved by 15 to 20% compared to the SFET, and the breakdown voltage is close to the theoretical breakdown voltage of a plain pn junction.
第５図（ａ）〜（ｃ）はソース、ゲート電極を０■とし
、ドレイン電極に逆電圧を印加した場合の等ポテンシャ
ル図であり、それぞれゲート部の断面形状を示している
。FIGS. 5(a) to 5(c) are equipotential diagrams when the source and gate electrodes are set to 0.times. and a reverse voltage is applied to the drain electrode, and each shows the cross-sectional shape of the gate portion.
（ａ）は第６図に示す従来のＭＯＳＦＥＴ、（ｂ）は第
８図に示す従来のＭＯＳＦＥＴ、（ｃ）は本発明のＭＯ
ＳＦＥＴのシミュレーション図である。(a) is the conventional MOSFET shown in FIG. 6, (b) is the conventional MOSFET shown in FIG. 8, and (c) is the MOSFET of the present invention.
It is a simulation diagram of SFET.
（ａ）、（ｂ）で示す従来のＭＯＳＦＥＴは等ポテンシ
ャル線が湾曲して集中する部分が生じて電界が集中する
構造になっており、耐圧が低下する。The conventional MOSFETs shown in (a) and (b) have a structure in which the equipotential lines are curved and concentrated, and the electric field is concentrated, resulting in a decrease in breakdown voltage.
これに対し本発明のＭＯＳＦＥＴはポテンシャル線の湾
曲がなく、電界集中か少ないことを示している。On the other hand, in the MOSFET of the present invention, there is no curvature of the potential line, indicating that the electric field concentration is small.
このことは本発明で用いた比誘電率の高い膜１１により
この中の等ポテンシャル線の本数が減少しＳｔの境界部
で急激な絞り込み部がなく電界集中の発生を抑止してい
るからである。This is because the film 11 with a high dielectric constant used in the present invention reduces the number of equipotential lines therein, and there is no sharp narrowing part at the boundary of St, suppressing the occurrence of electric field concentration. .
〈発明の効果〉
以上実施例とともに具体的に説明した様に本発明によれ
ば、Ｓｉ境界部での急激な絞り込みかないので理論耐圧
に近付けることができ、そのためエピタキシャル層の比
抵抗が低くても目標耐圧を得ることかできるので、縦形
ＭＯＳＦＥＴの低オン抵抗化及び高耐圧化をはかったパ
ワーＭ ＯＳ ＦＥＴを実現することができる。<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, there is no rapid narrowing down at the Si boundary, so the breakdown voltage can be approached to the theoretical breakdown voltage, so even if the resistivity of the epitaxial layer is low, Since the target breakdown voltage can be obtained, it is possible to realize a power MOS FET with lower on-resistance and higher breakdown voltage than the vertical MOSFET.
第１図は本発明の一実施例を示す断面図、第２図は第１
図のＡ部の拡大図、第３図は他の実施例を示す拡大図、
第４図はｐｎ接合の理想的な耐圧と本発明及び従来例を
比較した場合の耐圧のシュミレーション結果を示す図、
第５図は等ポテンシャル図、第６図〜第８図は従来例を
示す断面図である。
１・・・ドリフト層、５・・・９層、６・・・ｎ＋層、
７・・・溝、８・・・ゲート酸化膜、９・・・ゲート電
極、１０・・・チャネル、１１・・・高比誘電体層。
代理人 弁理士 小 沢 信 絋
゛パ≦
第１区
第２区
第３図
第４図
第乙 区
第１FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
An enlarged view of part A in the figure, FIG. 3 is an enlarged view showing another embodiment,
FIG. 4 is a diagram showing simulation results of the breakdown voltage when comparing the ideal breakdown voltage of the pn junction with the present invention and the conventional example,
FIG. 5 is an equipotential diagram, and FIGS. 6 to 8 are cross-sectional views showing conventional examples. 1...Drift layer, 5...9 layer, 6...n+ layer,
7... Groove, 8... Gate oxide film, 9... Gate electrode, 10... Channel, 11... High relative dielectric layer. Agent Patent Attorney Nobuo Kozawa ≦ Ward 1, Ward 2, Figure 3, Figure 4, Ward 1
Claims (1)
側面及び底面に酸化膜を形成し、前記溝の側面にゲート
電極を形成した矩形溝形ＭＯＳにおいて、前記溝の底面
に前記酸化膜より比誘電率の高い膜を形成したことを特
徴とする高耐圧パワーＭＯＳＦＥＴ。In a rectangular trench type MOS in which a trench is formed in a silicon substrate, an oxide film is formed on the side surfaces of the trench, or a side surface and a bottom surface of the trench, and a gate electrode is formed on the side surface of the trench, the oxide film is formed on the bottom surface of the trench. A high voltage power MOSFET characterized by forming a film with a high dielectric constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319449A JPH04188877A (en) | 1990-11-22 | 1990-11-22 | Power mosfet of high breakdown strength |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2319449A JPH04188877A (en) | 1990-11-22 | 1990-11-22 | Power mosfet of high breakdown strength |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04188877A true JPH04188877A (en) | 1992-07-07 |
Family
ID=18110328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2319449A Pending JPH04188877A (en) | 1990-11-22 | 1990-11-22 | Power mosfet of high breakdown strength |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04188877A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710401B2 (en) | 1994-02-04 | 2004-03-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a trench with at least one of an edge of an opening and a bottom surface being round |
| KR100450652B1 (en) * | 1997-08-22 | 2004-12-17 | 페어차일드코리아반도체 주식회사 | Trench type power MOSFET and manufacturing method thereof |
| JP2007110125A (en) * | 2005-10-12 | 2007-04-26 | Qimonda Ag | Microelectronic device and manufacturing method thereof |
| WO2012105611A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor power device and method for producing same |
| JP2016164906A (en) * | 2015-03-06 | 2016-09-08 | 豊田合成株式会社 | Semiconductor device and manufacturing method of the same, and power converter |
| JP2019186506A (en) * | 2018-04-17 | 2019-10-24 | 株式会社東芝 | Semiconductor device |
-
1990
- 1990-11-22 JP JP2319449A patent/JPH04188877A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710401B2 (en) | 1994-02-04 | 2004-03-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a trench with at least one of an edge of an opening and a bottom surface being round |
| US7067874B2 (en) | 1994-02-04 | 2006-06-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round |
| KR100450652B1 (en) * | 1997-08-22 | 2004-12-17 | 페어차일드코리아반도체 주식회사 | Trench type power MOSFET and manufacturing method thereof |
| JP2007110125A (en) * | 2005-10-12 | 2007-04-26 | Qimonda Ag | Microelectronic device and manufacturing method thereof |
| US9947536B2 (en) | 2011-02-02 | 2018-04-17 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| JP5858934B2 (en) * | 2011-02-02 | 2016-02-10 | ローム株式会社 | Semiconductor power device and manufacturing method thereof |
| US9472405B2 (en) | 2011-02-02 | 2016-10-18 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| WO2012105611A1 (en) * | 2011-02-02 | 2012-08-09 | ローム株式会社 | Semiconductor power device and method for producing same |
| US10515805B2 (en) | 2011-02-02 | 2019-12-24 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US10840098B2 (en) | 2011-02-02 | 2020-11-17 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US11276574B2 (en) | 2011-02-02 | 2022-03-15 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US12009213B2 (en) | 2011-02-02 | 2024-06-11 | Rohm Co., Ltd. | Semiconductor power device and method for producing same |
| US12469704B2 (en) | 2011-02-02 | 2025-11-11 | Rohm Co. Ltd. | Semiconductor power device and method for producing same |
| JP2016164906A (en) * | 2015-03-06 | 2016-09-08 | 豊田合成株式会社 | Semiconductor device and manufacturing method of the same, and power converter |
| JP2019186506A (en) * | 2018-04-17 | 2019-10-24 | 株式会社東芝 | Semiconductor device |
| US10847649B2 (en) | 2018-04-17 | 2020-11-24 | Kabushiki Kaisha Toshiba | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6580123B2 (en) | Low voltage power MOSFET device and process for its manufacture | |
| CN1823421B (en) | vertical semiconductor device | |
| US6849880B1 (en) | Power semiconductor device | |
| CN111081779B (en) | A shielded gate trench MOSFET and its manufacturing method | |
| US6677641B2 (en) | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability | |
| CN1209822C (en) | Channel metallic-oxide-semiconductor device and terminal structure | |
| US6833583B2 (en) | Edge termination in a trench-gate MOSFET | |
| US6916712B2 (en) | MOS-gated device having a buried gate and process for forming same | |
| JP4685297B2 (en) | Trench metal oxide semiconductor device and method of manufacturing termination structure | |
| US7489011B2 (en) | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics | |
| CN100334731C (en) | Trench DMOS transistor with built-in Trench Schottky rectifier | |
| KR102186290B1 (en) | Semiconductor device with needle-shaped field plates and a gate structure with edge and node portions | |
| CN101800243B (en) | Manufacture method of trench dmos transistor having a double gate structure | |
| JPH01192174A (en) | Manufacturing method of semiconductor device | |
| JPS62272570A (en) | Vertical gate semiconductor device and its manufacturing method | |
| JPH08250731A (en) | Trench-type MOSFET with high breakdown voltage and low on-resistance | |
| US20120175702A1 (en) | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same | |
| JP3369388B2 (en) | Semiconductor device | |
| CN1909245A (en) | Semiconductor structure with improved on resistance and breakdown voltage performance | |
| CN115881797A (en) | Silicon carbide device and preparation method thereof | |
| CN105118852A (en) | Super junction structure, super junction MOSFET and manufacturing method thereof | |
| CN113851523A (en) | Shielding gate MOSFET and manufacturing method thereof | |
| US7276405B2 (en) | Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same | |
| CN118763119A (en) | A super junction power device and a method for manufacturing the same | |
| JPH0582783A (en) | Lateral insulated-gate field-effect semiconductor device |