JPH04179166A - Insulated gate semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable an insulated gate semiconductor device to be lessened in loss and kept high in reliability by a method wherein semiconductor layers which form channel regions are connected to each other and arranged adjacent to a source electrode or a drain electrode. CONSTITUTION:In a MOSFET, a P-type semiconductor layer 100 formed on a semiconductor substrate 10 through the intermediary of a thermal oxide film 20 is made to serve as a base layer of a MOSFET. A voltage is applied to a gate electrode 30 through the intermediary of a gate oxide film 60, whereby a channel is formed on the base layer to control a current between a source 40 and a drain 50. As mentioned above, semiconductor layers which form channel regions are connected to each other and arranged adjacent to a source electrode 41 or a drain electrode 51, so that a MOSFET of this design can be enhanced in packing density, and heat can be dissipated through the source electrode 41 and the drain electrode 51. In result, the MOSFET can be lessened in ON-state resistance per unit area and sharply enhanced in thermal breakdown strength and reliability as compared with a conventional one. A MOSFET of this structure is small in junction capacitance between a drain and a source, so that it is excellent in high-frequency characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power semiconductor device, and particularly to an insulated gate semiconductor device suitable for achieving low loss and high frequency characteristics.

[Conventional technology]

Conventionally, an insulated game (-type field effect 1 to transistor (MOSF''ET)) suitable for obtaining low loss and high frequency characteristics was described in 1989 by I.D.E.M.

34.5 (IEDM' 89.-34.5).

In this structure, a channel is provided in a semiconductor layer that is substantially perpendicular to a substrate formed on an insulating film, and the direction of current flowing through the channel is made almost parallel to the surface of the substrate, and the height of the semiconductor layer is By increasing the channel width, a large current can be achieved by increasing the channel width.

[Problem to be solved by the invention]

With the above conventional technology, there is a limit to the ability to operate at a higher current, that is, to obtain a structure with lower loss, and no consideration is given to heat dissipation. There were some problems in maintaining it.

An object of the present invention is to provide a low on-resistance MO3FET with low loss and high reliability.

[Means to solve the problem]

The above object is achieved by interconnecting the semiconductor layers forming a plurality of channel regions and arranging them adjacent to source or drain electrodes.

[Effect]

By interconnecting the semiconductor layers forming multiple channel regions and placing them in instantaneous contact with the source or drain electrodes, packaging density and reliability can be improved.
Heat can be dissipated from the drain electrode. Thereby, MOSF
ET can reduce on-resistance, significantly improve heat dissipation, and achieve high reliability.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
Figure (a) is a plan view of the MOSFET, (b) is its A-A
'Cross-sectional structural diagram; (c) is a BB' cross-sectional structural diagram. 1
0 is a p-type semiconductor substrate with a resistivity of ]OΩ・CIll, 20
1 is a thermal oxide film with a thickness of 1 μm, 30 is a polycrystalline silicon mesh-like gate electrode, 100 is a mesh-like p-type semiconductor layer with a height of 0.4 μm and a width of 0.2 μm, and 40 is a highly doped n-type semiconductor layer. 50 is a high concentration ■1 type train region,
60 is a gate oxide film with a thickness of 2 On +n, /1.1
．． 51 are source and drain electrodes, 31 are gate extraction electrodes, and 42.52 are source and drain contactors I to electrodes, respectively. Further, 70 is a polyimide resin film used as a one-layer protective film.

Next, in order to clarify the operating principle of this structure, M O
A bird's-eye view of the main parts of SFET is shown in Figure 2.

] 100 p-type semiconductor layers formed on the 0 semiconductor substrate via 20 thermal oxide films serve as the so-called base layer of the MOS FET. By applying a voltage to the base layer through the gate oxide film 60 and the gate electrode 30, a channel is formed and the current between the source and the train is controlled.

The feature of this structure is that the semiconductor layers forming multiple channel regions are interconnected and placed adjacent to the source or drain electrodes, which improves the packaging density and allows heat to be dissipated from the source and drain electrodes. It is. As a result, the on-resistance per unit area was reduced, and the thermal breakdown strength and reliability were significantly improved compared to the conventional example. Furthermore, since this structure has a small drain-source junction capacitance, it also has excellent high frequency characteristics.

According to this embodiment, the power MO8 of the 0.5 mm rotary tube is
In the FET, the train breakdown voltage is 8V and the on-resistance is Lo.
omΩ and a cutoff frequency of 10 GHz was obtained.

Next, another embodiment of the present invention will be described with reference to FIG.

Figure 3 (a) is a plan view of the MOSFET, (b) is its A
-A' is a cross-sectional structural diagram, and (e) is a BB' cross-sectional structural diagram. Here, 11 has a resistivity of 0. In the n-type semiconductor substrate of o1Ω·an, 1.2 is the n-shaded region connected to the source region. Further, a source electrode 43 is arranged on the back surface of the substrate, and a drain electrode 53 is arranged on the entire surface. The rest is almost the same as in FIG. 1.

The feature of this structure is that the source electrode is arranged on the back surface of the substrate, and the drain electrode is arranged on the entire surface. the result,
The heat generated in the channel can be easily dissipated, and the thermal breakdown strength has been significantly improved compared to the conventional example. Furthermore, since this structure has a small source inductance, it also has excellent high frequency characteristics.

Next, another embodiment of the present invention will be described using FIG. 4.

FIG. 4 is a cross-sectional structural diagram of the MOSFET. here,
10 is a p-type semiconductor substrate with a resistivity of 1.0Ω·cm, and 55 is a p-type semiconductor substrate with an impurity concentration of 1.0Ω·cm. This is a low concentration drain region of about X i O''/ca3.Other parts are almost the same as in FIG.

A feature of this structure is that it has a lightly doped drain region. As a result, the drain breakdown voltage was improved to 15V.

Next, another embodiment of the present invention will be described using FIG. The figure is a sectional view of the main part of the MOSFET.

Here, the source electrode 45 is structured to cover the lightly doped train region 55 via the gate electrode 30 and the insulating film 70, thereby relieving the electric field concentration in the lightly doped drain region near the end of the gate electrode. As a result, we were able to improve the train breakdown voltage while minimizing the deterioration of other properties.

In this example, a 0.5mm rotary power MOSFE is used.
At T, the drain breakdown voltage is 20V.

An on-resistance of 150 mΩZ was obtained.

Next, another embodiment of the present invention will be described using FIG. 6. The figure is a block diagram of an intelligent driver LSI having the power MO8FET of FIG. 1 in the output stage. 20
1 is an input/output control section, 202 is a computer section, 203 is a nonvolatile memory section, 204 is a power MOS driver section having an H-bridge configuration, and 205 is various protection function sections. Although each of these functional sections is arranged on the same chip, each device is separated by an insulating film as shown in FIG. 1, so there is no problem of noise due to mutual interference.

When this chip was used for a small motor control device for a magnetic disk, the output was 5W at an operating frequency of 20Kllz.
, an efficiency of 95% was obtained. Also overvoltage.

During overcurrent and overtemperature operation tests, a self-diagnosis circuit was activated to prevent element destruction.

Next, another embodiment of the present invention will be described using FIG. 7. The figure shows the MOSFE i' formed on the insulating film shown in Figure 1.
FIG. 2 is a cross-sectional structural diagram of a main part of a power LSI having a power MO3FET formed on a semiconductor substrate. Here, the power MOSFET has a vertical structure with the substrate as the drain, 14 has a depth of 3 μm, and a surface concentration of 5×1017/a.
Base region of I-, 44 is 0.3 μm deep, surface concentration I
x 10"/an" source region, 64 is 20n thick
56 is a low concentration drain region with a thickness of 8 μm and an Il type impurity concentration of 5×10''/mark 3, 57 is a high concentration drain region, and 46° 58.34 are source, drain, and gate electrodes, respectively. With this structure, a power MOSFET capable of handling high voltage and high power and a MOSFET capable of handling high frequencies with low loss can coexist on the same chip.

According to this embodiment, the power MO5FET has a drain breakdown voltage of 60V and a train current of 20A, and the drain breakdown voltage of the M and OSFET formed on the insulating film is 8V.
V, on-resistance is 1. OOmΩ, cut 1 to off frequency 1. OG Hz, and was able to produce a composite power chip that can handle high power and high frequency.

Next, another embodiment of the present invention will be described. MOS in Figure 1
In FET, a rectangular mesh-like plane pattern was shown, but the structure shown in FIG. 8 is also shown. Figure 8 shows a case in which the semiconductor layer formed on the insulating film is hexagonal.
The gate electrode has a triangular mesh-like planar structure.

Next, another embodiment of the present invention will be described. MOSF in Figure 1
In ET, polycrystalline silicon was used as the gate electrode material, but here molybdenum was used. After forming the molybdenum gate electrode, arsenic ion implantation was performed at 50 kV and I x 10''' to form the source and drain regions.
After forming a protective insulating film under the conditions of '/■2, heat treatment was performed at 900°C to activate impurities in the implanted ions.11 According to this example, the cutoff frequency of the power MO8FET became 20 GIIz, making it possible to use ultra-high frequencies. We were able to create a chip that could handle it.

Next, another embodiment of the present invention will be described. MOS in Figure 1
In the FET, a silicon oxide film was used as the gate insulating material, but here a high dielectric constant composite film containing a tantalum oxide film was used. As a result, without changing the electrical characteristics,
Since the thickness of the gate insulating film can be increased, reliability regarding gate dielectric breakdown has improved by more than an order of magnitude.

Although the above embodiments have been explained using an n-channel MO8FET as an example, a p-channel MO8FET has similar effects. Further, although a high dielectric constant composite film containing a silicon oxide film and a tantalum oxide film was used as the gate edge film, other high dielectric constant composite films such as a film containing a titanium oxide film or an oxyti-1-lite film may also be used. Other materials as gate electrodes,
For example, changes may be made to aluminum, tungsten, tungsten silicide, molybdenum silicide, and titanium silicide without departing from the spirit of the present invention.

[Effects of the Invention] According to the present invention, a plurality of channel regions can be mounted with high density, so that current density can be increased and on-resistance can be reduced. Further, since heat can be dissipated more efficiently than from the source or drain electrode, there is an effect that the thermal breakdown resistance is increased.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 1(a) shows M, O
The plan view of SFET, Fig. 1(b) is the same as Fig. 1(a).
1(c) is a BB' vertical sectional view of Fig. 1(a), Fig. 2 is a bird's-eye view of the main part of Fig. 1, and Fig. 3 is the book. In another embodiment of the invention, FIG. 3(a) shows a MOSF
The plan view of ET, FIG. 3(b), is A- in FIG. 3(a).
A' vertical sectional view, Figure 3(c) is BB' in Figure 3(a)
A vertical cross-sectional view, FIG. 4 is a MOSFET of another embodiment of the present invention.
FIG. 5 is a vertical sectional view of the main part of M of another embodiment of the present invention
FIG. 6 is a block diagram of another embodiment of the present invention, and FIG. 7 is a longitudinal cross-sectional view of the main part of the OSFET.
A vertical cross-sectional view of the main parts of OS FET. Furthermore, FIG. 8 is a plan view of the main parts of a MOSFET according to another embodiment of the present invention. . 10.11 ・Semiconductor substrate, 20... thermal oxide film, 3
0°31.34...gate electrode, 40.44...n
Shape source area, 50.57 Shape train area, 6
0゜64...Glue-insulating film, 70...Interlayer protective film,
100°14...p-type base region, 41,4.2,4.
3,45°46...source electrode, 51,52,53.
58...Do 3 Z Plan view B-B document CrATE DPΔ71 SOIJgCl
:/θ 55 5 Figure B-B' cross section

Claims (1)

[Claims] 1. A source electrode and a drain electrode are provided on a substrate, and a channel is further provided between the source electrode and the drain electrode, and a gate electrode that exerts an electric field effect is provided in the channel via an insulating film. , the channel is adjacent to the source or drain electrode in a semiconductor device having a field effect transistor, at least a portion of which is provided in a semiconductor layer substantially perpendicular to the substrate, and the direction of current flowing through the channel is substantially parallel to the substrate. An insulated gate semiconductor device characterized in that a plurality of channel layers are arranged. 2. The insulated gate semiconductor device according to claim 1, characterized in that the source or drain electrode is taken out from the back surface. 3. The insulated gate semiconductor device according to claim 1, further comprising a drain lightly doped impurity layer in the semiconductor portion between the drain and the gate. 4. An insulated gate semiconductor device according to claim 3, characterized in that the vicinity of the gate end of the drain lightly doped impurity layer is covered with a gate or source electrode via an insulating film. 5. An insulated gate semiconductor device, wherein the semiconductor device according to claim 1 and an integrated circuit formed in a substrate are formed on the same chip. 6. The insulated gate semiconductor device according to claim 1, which is used for high frequency amplifier applications of 1 GHz or higher. 7. The insulated gate semiconductor device according to claim 1, wherein the gate electrode includes a metal material having a high melting point temperature of 800° C. or higher. 8. The insulated gate semiconductor device according to claim 1, wherein the gate insulating film contains a substance having a dielectric constant of 4 or more.