JPH04178037A - Function test method in frame format of digital transmission system and test circuit - Google Patents

Abstract

PURPOSE:To confirm the function of a required byte at a real speed by starting count from a head of control information of a frame format by a counter, outputting a prescribed signal from a detection circuit detecting its end and loading a new initial value to the counter. CONSTITUTION:When a frame detection section 30 detects a frame in a state that no frame synchronization is taken, a signal CASE goes to H and a clock pulse is outputted. A pulse signal CASE is generated in a timing when the frame is detected and becomes a load signal of a counter 40. As soon as the signal CASE and a frame are detected, the counter 40 starts counting, 0 is loaded and the counter is counted sequentially and when a decoder 41 decodes 8, an AND gate 41 is made 'through' and an H pulse is outputted. The initial value of the counter receiving the pulse is switched and a signal T8 circulated through a negative feedback loop 43 becomes a load signal. Thus, bytes not requiring the test are skipped and only the required byte function is confirmed in a real speed.

Description

[Detailed description of the invention] [1! The present invention relates to a method for testing the IN capability of LSI in the frame format of repeaters and terminal equipment that control information transmission in a digital transmission system, and a test circuit for the same. The purpose is to shorten the test time to confirm the processing function of each byte. Frames are detected from the input signal from the digital transmission path, the frames are counted in response to the detected frame synchronization pulse, and the test mode is set. When determining the settings of the test mote, select only the control information in the frame and generate internal timing corresponding to that control information.
The present invention provides a frame function test method and test circuit for a digital transmission system that makes it possible to test a frame control signal according to its internal timing.

[Industrial Field of Application] The present invention relates to a test method and a test circuit for LSI used in repeaters and terminal equipment that comply with the 5ONET standard as a broadband ISDN. The present invention relates to a functional test method and test circuit in a frame/t-mat of a digital transmission system for the purpose of confirming parallel frame synchronization protection and processing ability of each byte within a frame.

[Prior art] SOS ET (Sync
hro-nous 0ptical NETwork)
is a network that directly interconnects high-capacity, digital exchanges, multiplexing equipment, etc. at the 5TS-N level to form an economical optical fiber synchronous network, and is constructed based on North American standards that comply with CCITT. , 5ONET multiplexing involves multiplexing N 5TS-1s using synchronous octet multiplexing, which is called 5TS-N.Currently, the multiplicities considered for 5ONET are 1.3, 9, 12, . +8.24°36.
48, and there is a tendency for further multiplexing to occur in the future.

Regarding LSIs used in repeaters or terminal equipment in such networks, at the time of software release, parallel frame synchronization protection and processing of each byte within the frame were implemented for the multiplexed 5OSET frame format. Functionality is being checked. Note that a frame is two cycles of a multiplexed bit signal string.

During multiplexing, a frame synchronization bit pattern is inserted so that the beginning and end of one frame can be identified, and the operation of detecting the frame synchronization bit pattern placed within a frame is called frame synchronization. In addition, in synchronization control, the bit string pattern of the received signal is compared with the frame synchronization bit pattern, and when the patterns match a certain number of times (number of protection stages), it is considered to be synchronous. This is called backward protection, and the number of mismatches is When a certain number of times (number of protection steps) is exceeded, it is considered out of synchronization, which is called forward protection.

Problem 2 to be Solved by the Invention Taking the above-mentioned conventional frame synchronization protection function check as an example, if the protection type is 2 stages of rear protection and 4 stages of forward protection,
To see all of these possible conditions, 16
In the case of bit parallel processing, there are 16 detection patterns for frame detection alone, as shown in FIG. 6(a).

The frame structure of 5OSET is 5TS-IX12 multiplexed, and if you try to process 77760 bits (for 1 frame) in one serial, it corresponds to 600M of norial data, which is impossible to process with a CMOS LSI, so it is usually 0MO3. Lower the frequency to 39M that can be processed with 1
6 parallel processing is performed. Therefore, if the human data is noreal data, #11°312 shown in Figure 6(b)
, ;:l, You only need to check #2, but in the case of 16 parallels, you don't know how the input bits will be received in different patterns, and if they are received in a pattern shifted by l hits, this will occur in 16 ways. 486 for Shiku+Frame
0 hatan) have to do those simulations. Frame detection is not confirmed unless all 16 types of detection are performed. Specifically, the frame synchronization better information consists of 8 bits of F
6 (till 0110), F 6 (f
ill 011 (ln, 2 B (HID)
1000), 2 8 (00101000) patterns. In this way, the input bit string is an asynchronous pattern, and when converting from 600M to 39M, it is not always separated at the beginning of F, so if it is shifted by 1 hit vertically, 16 patterns will be created. will occur.

By adding each protection state to such frame detection, the result is that an enormous amount of time is spent to verify the processing aia of each byte in the frame. Therefore, such long-term software development often results in increased development man-hours and higher costs.

The present invention has been made in consideration of the above circumstances, and in order to solve the problems of the conventional technology, it is possible to skip unnecessary bytes for testing in an I frame and check the functionality of only necessary bytes at actual speed. The purpose of this paper is to provide a frame format test circuit for a digital transmission system and a test method thereof.

[Means for solving the problem] Figure 1 shows a frame diagram of the digital transmission system of the present invention.
This is a basic block diagram of a functional test circuit in the format, and FIG. 2 is an electrical block diagram of the frame counter section shown in FIG. 1. The test circuit in the present invention is S ON
Suitable for repeaters and terminal equipment in ET.

In both figures, the present invention detects frames from the input signal from the digital transmission path, counts frames in response to the detected frame synchronization pulse, determines the test mode setting, and determines the test mode setting when the test mode is set. This is to select only the control information within a frame, generate internal timing corresponding to that control information, and test the frame control signal based on that internal timing. a detection section (30) that detects a frame synchronization pulse from an input signal of the frame counter, a frame counter section (31) that counts frames in response to the detected frame synchronization pulse, and a timing generation section (32) that generates each internal timing. ) and a frame synchronization protection unit (33) that performs frame synchronization protection according to the generated timing.
), the iJa frame counter unit (31) includes a register (34) that stores a plurality of setting values corresponding to the beginning and end of control information in a frame, and a register (34) that stores a plurality of setting values corresponding to the beginning and end of control information in a frame, and A switching circuit (35) that selectively outputs a specific set value, and a counter (35) that loads the selectively outputted set value from the load terminal, counts frames from the set value, and outputs various internal timings.
40), a detection circuit (37) that outputs a predetermined signal when the counter (40) counts the end of the control signal;
It consists of a switching circuit (35) and a circuit that negatively feeds back a predetermined signal to the load terminal in order to start counting from the beginning of the control signal.

[Operation] According to the present invention, the counter (40) starts counting from the beginning of the control information in the frame format, and when the end of the control information is counted, the detection circuit (37) outputs a predetermined signal and The feedback circuit inputs a predetermined signal into the switching circuit (35) and the load terminal of the counter (40), and a new initial value is loaded into the counter (40). This new initial value corresponds to the beginning of the control information,
Therefore, it is possible to check the functionality by selecting only the overhead in the frame format, and the time required to test the functionality of each byte within the frame can be reduced.

[Example] The present invention will be described in detail below based on the example shown in the figures. Note that the present invention is not limited thereby.

First, FIG. 3 shows the structure of the frame format of 5TS-12 of 5ONET. In the figure, one frame is composed of 1080 bytes x 9 rows, and is divided into an overhead section for transmitting a frame synchronization signal and various auxiliary signals, and a payload section for transmitting information signals. The frame repetition period is 125 μs. The overhead includes all signals necessary for transmitting multiple electrical signals, such as frame synchronization signals, error monitoring codes, channel identification signals, maintenance channels, and alarm signals. Also, the frame! Taking the row 1 as an example, the overhead A1. A2. CI is #1~#
It consists of up to 12 bytes, each byte consisting of 8 bits.

This frame format confirmation function will be explained using an example of parallel format synchronization protection.

First, the test method will be explained. By converting to 16-bit parallel data, ■frame (125μ5)
In the frame format formed by 4860 bits, in order to check the frame detection and synchronization protection in a short time, the overheads Al, A2,
It is sufficient to check only the CI byte. To further limit the number, since the 01 byte is a channel identification signal, it may be removed and only A1 and A2 may be checked.

In other words, in this embodiment, by checking only the overhead data in the frame format, it is possible to check the functionality of each byte in the frame format in 1/270 of the time required in the normal test mode. .

Next, a circuit for carrying out this test method will be explained. FIG. 1 is a diagram showing the basic configuration of a frame format test circuit. The frame detection section 30 detects frames from the received 16-bit parallel data and provides a frame pattern to the frame counter section 31. The frame counter unit 31 is configured to set a mode, that is, a test mode (
T S T =High) and gives the data to each internal timing generation section 32 , and the timing generation section 32
The frame synchronization protection unit 33 is configured to operate according to the timing generated by the frame synchronization protection unit 33.

Figure 2 shows the characteristics of this embodiment. ! FIG. 2 is an electrical circuit diagram of a frame counter section, which is a part of FIG. In the same figure, 40 is +oa
There is a 13-pit counter with d (load, read data) function, and the inputs are signal 00F and signal C.
ASEL, signal CASE, 39M parallel data input and signal TST (test pin). This counter 40 can be switched to a load mode or a count mode using a counter/σ-code input terminal, and in the case of the load mode, the states of data inputs D0 to DI2 are read. This load mode is used to set the state in which you want to start counting, and after loading, applying a clock pulse will start counting from the read state.

First, the frame synchronization is not established, that is, the signal 00F is high and the signal CASEL is high.
When a frame is detected by the frame detection unit 30 in the state of h<Low, the signal CASE becomes High and a 39M width clock pulse is output. In the time chart of FIG. 4, symbol F located to the left of the clock input is the timing at which a frame is detected for the first time.

Then, a pulse is generated in the signal CASE at the timing when the frame is detected, and this pulse becomes the load signal for the counter 40.

Inputs D0 to DI of the counter 40! is the initial setting counter value, and the initial setting is to select from @0 to 4851'', and initially select 0''. Thereby the signal CA
At the same time as SE detects a frame, that 10" is loaded. After that, the load is released and the count is counted up in order from "0' to 11", "2", and "3". In the test mode, Since the input TST is in the High state, the counter 40 counts up, and when the decoder 41 decodes 18@, the AND gate 41 becomes through, and a High pulse is output.

Upon receiving this High pulse, the initial setting of the counter 40 is switched to "4BSL". Simultaneously with the switch to "4851", the signal T8 that has passed through the negative feedback loop 43 becomes the load signal. The fact that it becomes a load signal means that "4851" is loaded into the counter 40, which means that "485[,"
The count is counted up in the order of ``4852'' and ``4853.'' Next, the decoder 44 connected to the LOAD terminal
At the same time as decoding “4859”, “0” is loaded. As a result, the counter 40 counts up again from "0", and when "8" is counted, "4851" is counted up.
”, and repeats the counting operation of counting “4859” and returning to 0.

The above counter value "4851" corresponds to the beginning of the A] byte shown in Figure 3, "4859" corresponds to the end of the A1 byte, "0" corresponds to the beginning of the A2 byte, and "8" corresponds to the beginning of the A2 byte. Corresponds to the end of the Cl byte. Therefore, the frame counting operation repeats from "0° → "8" → "4851". Note that if the test mote is not used, even if the decoder 41 detects "8", the loop 43 will not provide feedback. .

In addition, in FIG. 5(i), the symbol F is A on the frame.
This is the position of t5A2 bytes. In normal mode, 0”
The count is counted up to "4859", and the count is repeated. However, in the test mode according to this embodiment, only the A1 and A2 bytes (including the Cl byte) are checked and feedback is applied as described above. Therefore, compared to the normal mode, the test time can be reduced to 1/27Q.

In addition, as shown in the 51st ffl(b), if the frame format includes a code K, which is the second hit of f, which detects a line break and issues an alarm, F. It is also possible to carry out a test by performing NB, then skipping to the K position, checking, and returning to the F position.

[Effects of the Invention] As described above, according to the present invention, the test time conventionally required to confirm the function of a frame format, that is, the test time of 125 μs per frame, can be reduced by about 1 /
It can be shortened to 27Q. Therefore, the number of development steps can be reduced by significantly shortening test time, and the cost of repeaters and terminal equipment can be reduced. Furthermore, by changing the settings in the test mode, it is possible to select a variety of combinations of the function confirmation portions of each byte within the frame.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a circuit diagram of the frame counter shown in FIG. 1, and FIG. 3 is a schematic diagram showing the frame format in one implementation.
FIG. 4 is a time chart of one embodiment, FIG. 5 (λ) is an explanatory diagram showing a method of checking frame synchronization, FIG. FIG. 6(a) is an explanatory diagram showing a synchronization detection pattern of parallel data in a conventional example, and FIG. 6(b) is an explanatory diagram showing synchronization detection of norial data in a conventional example. 30...Frame detection unit, 31...Frame counter unit, 32...Internal timing generation unit, 33...Frame synchronization protection unit, 34...Register, 35...・Switching circuit, 37... Detection circuit, 40... ・Counter. Figure 6 (a)

Claims (1)

[Claims] 1. When a frame is detected from an input signal from a digital transmission line, the frames are counted in response to the detected frame synchronization pulse, and the test mode setting is determined, and there is a test mode setting. A frame function testing method for a digital transmission system that selects only control information within a frame, generates internal timing corresponding to the control information, and tests a frame control signal according to the internal timing. 2. A detection unit (30) that detects a frame synchronization pulse from an input signal from a digital transmission path, a frame counter unit (31) that counts frames in response to the detected frame synchronization pulse, and generates various internal timings. A timing generation unit (32) and a frame synchronization protection unit (32) that performs frame synchronization protection according to the generated timing.
33), and the frame counter section (31) comprises:
A register (34) that stores a plurality of setting values corresponding to the beginning and end of control information in a frame, and a switching circuit (35) that selectively outputs a specific setting value from the register (34) every time a predetermined signal is received. ), a counter (40) that loads the selected output setting value from the load terminal, counts frames from the set value, and outputs various internal timings, and a counter (40) that counts the end of the control signal. A frame of a digital transmission system consisting of a detection circuit (37) that outputs a predetermined signal when the control signal is detected, and a circuit that feeds back the predetermined signal negatively to the switching circuit (35) and the load terminal to start counting from the beginning of the control signal.・Test circuit in format.